Preparation method and structure of Josephson junction array based on superconducting bridge junction

Abstract

The present application relates to a method and structure for preparing a Josephson junction array based on a superconducting bridge junction. Through multiple nanobridges, multiple first superconducting wire film substructures form a superconducting bridge junction array of a single layer of superconducting film, thereby obtaining a Josephson junction array structure. Since the Josephson junction array structure is formed by multiple first superconducting wire film substructures, the size of a single layer of superconducting film can be regulated, thereby reducing the periodic size of the smallest junction in the lateral dimension. Through the superconducting bridge junction array of a single layer of superconducting film, more layers can be stacked in sequence to increase the number of longitudinal layers as much as possible. Compared with the traditional sandwich structure Josephson junction array chip, the Josephson junction array of the present application can highly integrate more Josephson junctions on the same chip size, increasing the number of junctions by an order of magnitude to meet the market demand for output voltage. Moreover, when the number of Josephson junctions is the same, the size of the chip can be greatly reduced.

Description

Technical Field

[0001] The present application relates to the technical field of electronic devices, and in particular to a method and structure for preparing a Josephson junction array based on a superconducting bridge junction. Background Art

[0002] The Josephson voltage standard is a metrological standard that reproduces the voltage value based on the Josephson effect. Compared with the traditional physical standard based on the standard Weston saturated battery, the quantum voltage standard has the advantages of high precision, high reproducibility and easy storage. The core of the quantum voltage standard is the large-scale integrated Josephson junction array chip. Among them, the amplitude of the quantum voltage is V = n·f / KJ = n·f·h / 2e, where the International Committee for Weights and Measures Electrical Consultative Committee recommends the Josephson constant as KJ = 483597.9GHz / V, h represents Planck's constant, e represents the electron charge, and n is the number of Josephson junctions. When the irradiated microwave frequency is fixed, the more junctions on the chip, the higher the output voltage. For example, when the microwave frequency is 16GHz, about 30,225 junctions are required to output 1V voltage.

[0003] However, the traditional method of preparing Josephson junction arrays uses superconducting tunnel junctions, that is, a sandwich structure of superconductor / insulator / superconductor to achieve weak coupling. At this time, the lateral size of the superconducting tunnel junction is a minimum period of 5μm or more. When integrated on a chip with a length of millimeters (such as 15mm), the number of junctions that can be integrated on a microwave line does not exceed 1,000, and space for other microwave components must be reserved. Therefore, when highly integrated on a chip, the number of superconducting tunnel junctions is limited, which in turn limits the output voltage, making it difficult to meet the needs of practical applications. Summary of the invention

[0004] Based on this, it is necessary to provide a method and structure for preparing a Josephson junction array based on superconducting bridge junctions that can integrate more Josephson junctions and have a higher degree of integration in order to address the above problems.

[0005] In order to achieve the above-mentioned object, on the one hand, the present application provides a method for preparing a Josephson junction array based on a superconducting bridge junction, comprising the following steps:

[0006] providing a substrate;

[0007] Preparing a first layer of superconducting thin film on the surface of the substrate;

[0008] Etching the surface of the first superconducting film away from the substrate until the surface reaches the substrate to prepare a plurality of first superconducting film structures;

[0009] preparing an insulating layer on a surface of the plurality of first-layer superconducting thin film structures away from the substrate and a surface of the substrate close to the plurality of first-layer superconducting thin film structures;

[0010] Etching the surface of the insulating layer away from the substrate to the first superconducting thin film structure to form a plurality of insulating layer structures, wherein the plurality of insulating layer structures surround a plurality of connection hole structures;

[0011] Preparing a superconducting wire thin film on the surface of the plurality of insulating layer structures away from the substrate and in the plurality of connection hole structures;

[0012] Etching the surface of the superconducting lead film away from the insulating layer structure until the insulating layer structure is reached to prepare a first superconducting lead film structure and a second superconducting lead film structure;

[0013] According to the bridge pattern, the surface of the first superconducting lead film structure away from the insulating layer structure is etched until the insulating layer structure is reached, a plurality of nanobridges are prepared, a superconducting bridge array is formed, and a Josephson junction array structure based on superconducting bridges is obtained.

[0014] In one embodiment, the surface of the superconducting lead film away from the insulating layer structure is etched until the insulating layer structure is reached to prepare a first superconducting lead film structure and a second superconducting lead film structure. After the steps, the method further comprises:

[0015] A terminal resistance structure is prepared near the second superconducting lead thin film structure.

[0016] In one embodiment, preparing a first layer of superconducting thin film on the surface of the substrate comprises the following steps:

[0017] The first layer of superconducting film is prepared on the surface of the substrate by using a magnetron sputtering method, setting the argon sputtering pressure in the range of 4mTorr to 10mTorr, and setting the superconducting material sputtering power in the range of 400W to 600W.

[0018] In one embodiment, etching the surface of the first superconducting film away from the substrate until it reaches the substrate to prepare a plurality of first superconducting film structures comprises the following steps:

[0019] According to the photoresist mask pattern, spin-coating a positive ultraviolet photoresist on the surface of the first superconducting film away from the substrate, and preparing a first photoresist structure by using a contact ultraviolet alignment exposure technology;

[0020] According to the first photoresist structure, a reactive ion etching method is used, the gas pressure range is set to 10mTorr to 15mTorr, the power range is set to 40W to 100W, and the etching gas SF6 range is set to 20sccm to 40sccm, and the surface of the first superconducting film away from the substrate is etched;

[0021] An optical endpoint detection method is used to monitor and control the etching process, and the etching is performed until the substrate is formed to prepare the plurality of first-layer superconducting thin film structures.

[0022] In one embodiment, according to the bridge pattern, the surface of the first superconducting lead thin film structure away from the insulating layer structure is etched until the insulating layer structure is reached, a plurality of nanobridges are prepared, a superconducting bridge array is formed, and a Josephson junction array structure based on superconducting bridges is obtained, including the following steps:

[0023] According to the bridge junction pattern, a focused ion beam etching method is used, and a voltage range is set to 20KV to 40kV to accelerate gallium ions, bombarding the surface of the first superconducting lead film structure away from the insulating layer structure, etching to the insulating layer structure, preparing the multiple nanobridges, and forming the superconducting bridge junction array.

[0024] In one embodiment, according to the bridge pattern, the surface of the first superconducting lead thin film structure away from the insulating layer structure is etched until the insulating layer structure is reached, a plurality of nanobridges are prepared, a superconducting bridge array is formed, and a Josephson junction array structure based on superconducting bridges is obtained, including the following steps:

[0025] According to the bridge pattern, a second photoresist structure is prepared on the surface of the first superconducting wire thin film structure away from the insulating layer structure by using an electron beam lithography method;

[0026] According to the second photoresist structure, a reactive ion etching method is adopted, the etching gas pressure range is set to 10mTorr to 20mTorr, the power range is set to 40W to 100W, and the etching gas SF6 range is set to 20sccm to 40sccm, the surface of the first superconducting lead film structure away from the insulating layer structure is etched, and the surface is etched to the insulating layer structure to prepare the multiple nanobridges and form the superconducting bridge junction array.

[0027] In one embodiment, the insulating layer is formed on the surface of the plurality of first-layer superconducting thin film structures away from the substrate and on the surface of the substrate close to the plurality of first-layer superconducting thin film structures, comprising the following steps:

[0028] A low-temperature plasma-assisted chemical vapor deposition method is adopted, with the deposition temperature range set to 50°C to 70°C, the pressure range to 5mTorr to 10mTorr, the oxygen flow range to 10sccm to 50sccm, and the silane flow range to 40sccm to 60sccm, to deposit a silicon dioxide film on the surfaces of the multiple first-layer superconducting thin film structures away from the substrate and on the surfaces of the substrate close to the multiple first-layer superconducting thin film structures to form the insulating layer.

[0029] In one embodiment, the present application provides a Josephson junction array structure based on a superconducting bridge junction, comprising a substrate, a plurality of first-layer superconducting film structures, a plurality of insulating layer structures, a plurality of first superconducting wire film substructures, and a plurality of nanobridges. The plurality of first-layer superconducting film structures are spaced apart on the surface of the substrate. The plurality of insulating layer structures are arranged between two adjacent first-layer superconducting film structures. The plurality of first superconducting wire film substructures are located on the surface of the insulating layer structure at the middle surface of the substrate. The plurality of nanobridges are located on the surface of the insulating layer structure at the middle surface of the substrate. The plurality of nanobridges are connected to the plurality of first superconducting wire film substructures in sequence to achieve a weak connection.

[0030] In one embodiment, the nanobridge comprises a superconducting wire thin film layer.

[0031] In one embodiment, the nanobridge is nanoscale in size.

[0032] In the above-mentioned method and structure for preparing a Josephson junction array based on superconducting bridge junction, the substrate is a substrate with high resistivity, small roughness and flatness. Specifically, the substrate includes but is not limited to a magnesium oxide single crystal substrate, a silicon substrate or a sapphire substrate. The material of the first layer of superconducting film is a superconducting material.

[0033] A dry etching method, such as ion milling etching, plasma etching, reactive ion etching, etc., is used to etch the surface of the first superconducting film away from the substrate, which has the advantages of both anisotropy and good selectivity, and multiple first superconducting film structures can be prepared. At this time, multiple first superconducting film structures are arranged at intervals on the substrate.

[0034] The insulating layer may be SiO2. The insulating layer covers the multiple first-layer superconducting film structures, thereby isolating each of the first-layer superconducting film structures, thereby playing an insulating isolation role. The insulating layer is etched at positions corresponding to the first-layer superconducting film structures. At this time, multiple insulating layer structures are formed by etching the insulating layer, and the multiple insulating layer structures surround and form multiple connecting hole structures, exposing the multiple first-layer superconducting film structures. Furthermore, the multiple first-layer superconducting film structures can be connected through the multiple connecting hole structures.

[0035] The multiple insulating layer structures are covered with the surface away from the substrate by the superconducting lead film. The superconducting lead film is deposited in the multiple connection hole structures to cover the multiple connection hole structures. At this time, the multiple insulating layer structures and the multiple first-layer superconducting film structures are covered by the superconducting lead film to achieve connection between the multiple first-layer superconducting film structures. The first-layer superconducting film structure is a Nb film structure, including a microwave coplanar waveguide (CPW) structure, a power divider structure, a phase shifter structure, and a bottom layer of an inductor and a capacitor structure.

[0036] The surface of the superconducting lead film away from the insulating layer structure is etched until the insulating layer structure is reached, thereby preparing the first superconducting lead film structure and the second superconducting lead film structure. The second superconducting lead film structure is located on both sides of the first superconducting lead film structure, and each inductor coil is disposed on the surface of each of the second superconducting lead film structures, thereby forming an electronic device (see Figure 5 shown).

[0037] According to the bridge diagram (see Figure 2 ), the surface of the first superconducting lead film structure away from the insulating layer structure is etched to expose the insulating layer structure, and a plurality of the nanobridges and a plurality of first superconducting lead film substructures are formed. At this time, the plurality of nanobridges and the plurality of first superconducting lead film substructures are sequentially connected to achieve weak connection, and the Josephson effect exists, forming a superconducting bridge junction array of a single superconducting film, and obtaining a Josephson junction array structure. In addition, the size of a single superconducting film can be regulated, thereby reducing the period size of the smallest junction in the lateral size, and a structure with a period of 100nm can be achieved.

[0038] At the same time, through the superconducting bridge array of a single superconducting film, more layers (more than 2 layers) can be stacked in sequence to increase the number of layers in the longitudinal direction as much as possible. Since a single superconducting film forms a superconducting bridge array, when multiple layers are stacked in the longitudinal direction, the heat dissipation problem will also be effectively alleviated.

[0039] Therefore, compared with the traditional sandwich-structured Josephson junction array chip, the Josephson junction array prepared by the superconducting bridge-junction-based Josephson junction array preparation method can highly integrate more Josephson junctions on the same chip size, increasing the number of junctions by an order of magnitude to meet the market demand for output voltage. Moreover, when the number of Josephson junctions is the same, the chip size can be greatly reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0041] Figure 1 The figure is a schematic diagram of the process flow of a method for preparing a Josephson junction array based on a superconducting bridge junction provided in one embodiment.

[0042] Figure 2 A schematic diagram of a superconducting bridge junction provided in one embodiment.

[0043] Figure 3 The diagram is a schematic diagram of etching an etching region of a first superconducting wire thin film structure using a focused ion beam etching method provided in an embodiment.

[0044] Figure 4 The diagram is a schematic diagram of the structure of the etching area and device for preparing the first superconducting wire thin film structure by using the focused ion beam etching method provided in one embodiment.

[0045] Figure 5 Schematic diagram of the structure of an electronic device provided in one embodiment.

[0046] Figure 6 The diagram is a top view of etching a first superconducting wire thin film structure using an electron beam lithography method and a reactive ion etching method provided in an embodiment.

[0047] Figure 7 Schematic diagram of a nanobridge and a first superconducting wire film substructure in a first superconducting wire film structure provided in an embodiment.

[0048] Explanation of the accompanying drawings: providing a substrate-10, a first superconducting film-20, a first superconducting film structure-210, an insulating layer-30, an insulating layer structure-310, a connecting hole structure-40, a superconducting lead film-50, a first superconducting lead film structure-511, a nanobridge-5111, a first superconducting lead film substructure-5112, a second superconducting lead film structure-512, a terminal resistance structure-60, a first photoresist structure-70, a second photoresist structure-80, a third photoresist structure-90, a fifth photoresist structure-920, an etching area-930, and an inductor coil-200. DETAILED DESCRIPTION

[0049] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0050] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0051] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. On the contrary, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0052] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0053] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0054] Embodiments of the application are described herein with reference to cross-sectional views that are schematic diagrams of ideal embodiments (and intermediate structures) of the application, so that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, embodiments of the application should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. Therefore, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shapes of the regions of the device, and do not limit the scope of the application.

[0055] See also Figure 1 The present application provides a method for preparing a Josephson junction array based on a superconducting bridge junction, comprising the following steps:

[0056] S10, providing a substrate 10;

[0057] S20, preparing a first superconducting thin film 20 on the surface of the substrate 10;

[0058] S30, etching the surface of the first superconducting film 20 away from the substrate 10, until the surface reaches the substrate 10, to prepare a plurality of first superconducting film structures 210;

[0059] S40, forming an insulating layer 30 on a surface of the plurality of first-layer superconducting thin film structures 210 away from the substrate 10 and a surface of the substrate 10 close to the plurality of first-layer superconducting thin film structures 210;

[0060] S50, etching the surface of the insulating layer 30 away from the substrate 10, etching to the first superconducting thin film structure 210, forming a plurality of insulating layer structures 310, wherein the plurality of insulating layer structures 310 surround a plurality of connection hole structures 40;

[0061] S60, preparing a superconducting wire film 50 on the surface of the plurality of insulating layer structures 310 away from the substrate 10 and in the plurality of connecting hole structures 40;

[0062] S70, etching the surface of the superconducting lead film 50 away from the insulating layer structure 310, until the insulating layer structure 310 is reached, to prepare a first superconducting lead film structure 511 and a second superconducting lead film structure 512;

[0063] S80, according to the bridge junction pattern, etching the surface of the first superconducting lead film structure 511 away from the insulating layer structure 310, etching to the insulating layer structure 310, preparing a plurality of nanobridges 5111, forming a superconducting bridge junction array, and obtaining a Josephson junction array structure based on superconducting bridge junctions.

[0064] See also Figure 1 In this embodiment, in S10, the substrate 10 is a substrate with high resistivity, small roughness and flatness. Specifically, the substrate 10 includes but is not limited to a magnesium oxide single crystal substrate, a silicon substrate or a sapphire substrate. In S20, the material of the first superconducting film 20 is a superconducting material.

[0065] In the S30, a dry etching method, such as ion milling etching, plasma etching, reactive ion etching, etc., is used to etch the surface of the first superconducting film 20 away from the substrate 10, which has the advantages of both anisotropy and good selectivity. Through the S30, a plurality of the first superconducting film structures 210 can be prepared. At this time, the plurality of the first superconducting film structures 210 are arranged at intervals on the substrate 10.

[0066] In the S40, the insulating layer 30 may be SiO2. The insulating layer 30 covers the multiple first-layer superconducting film structures 210, so that each of the first-layer superconducting film structures 210 can be isolated from each other, thereby playing an insulating isolation role. In the S50, the insulating layer 30 is etched at the position corresponding to the first-layer superconducting film structure 210. At this time, by etching the insulating layer 30, a plurality of insulating layer structures 310 are formed, and the plurality of insulating layer structures 310 surround a plurality of connecting hole structures 40 to expose the plurality of first-layer superconducting film structures 210. Furthermore, the plurality of first-layer superconducting film structures 210 can be connected to each other through the plurality of connecting hole structures 40.

[0067] In the S60, the multiple insulating layer structures 310 are covered with the surface away from the substrate 10 by the superconducting lead film 50. And the superconducting lead film 50 is deposited in the multiple connection hole structures 40 to cover the multiple connection hole structures 40. At this time, the multiple insulating layer structures 310 and the multiple first-layer superconducting film structures 210 are covered by the superconducting lead film 50 to achieve the connection between the multiple first-layer superconducting film structures 210. The first-layer superconducting film structure 210 is a Nb film structure, including a microwave coplanar waveguide (CPW) structure, a power divider structure, a phase shifter structure, an inductor, and a bottom layer of an inductor structure.

[0068] In the S70, the surface of the superconducting lead film 50 away from the insulating layer structure 310 is etched until the insulating layer structure 310 is reached, thereby preparing the first superconducting lead film structure 511 and the second superconducting lead film structure 512. The second superconducting lead film structure 512 is located on both sides of the first superconducting lead film structure 511, and each inductor 200 is disposed on the surface of each second superconducting lead film structure 512, thereby forming an electronic device (see Figure 5 shown).

[0069] In the step S80, according to the bridge pattern (see Figure 2 ), the surface of the first superconducting lead film structure 511 away from the insulating layer structure 310 is etched to expose the insulating layer structure 310, and a plurality of the nanobridges 5111 and a plurality of first superconducting lead film substructures 5112 are formed. At this time, the plurality of nanobridges 5111 and the plurality of first superconducting lead film substructures 5112 are sequentially connected to achieve a weak connection, and the Josephson effect exists, forming a superconducting bridge junction array of a single superconducting film, and obtaining a Josephson junction array structure. At this time, the size of a single superconducting film can be regulated, thereby reducing the period size of the smallest junction in the lateral size, and a structure with a period of 100nm can be achieved.

[0070] At the same time, through the superconducting bridge array of a single superconducting film, more layers (more than 2 layers) can be stacked in sequence to increase the number of layers in the longitudinal direction as much as possible. Since a single superconducting film forms a superconducting bridge array, when multiple layers are stacked in the longitudinal direction, the heat dissipation problem will also be effectively alleviated.

[0071] Therefore, compared with the traditional sandwich-structured Josephson junction array chip, the Josephson junction array prepared by the superconducting bridge-junction-based Josephson junction array preparation method can highly integrate more Josephson junctions on the same chip size, increasing the number of junctions by an order of magnitude to meet the market demand for output voltage. Moreover, when the number of Josephson junctions is the same, the chip size can be greatly reduced.

[0072] In one embodiment, the surface of the superconducting lead film 50 away from the insulating layer structure 310 is etched until the insulating layer structure 310 is etched to prepare a first superconducting lead film structure 511 and a second superconducting lead film structure 512. After the steps, the method further includes:

[0073] A terminal resistance structure 60 is prepared near the second superconducting lead thin film structure 512 .

[0074] In this embodiment, the reverse photoresist AZ5214 is used, the coating is spread and baked, and the contact ultraviolet lithography machine is used for overlay alignment, post-baking, exposure, and development, and the third photoresist structure 90 is prepared on the surface of the superconducting lead film 50 away from the substrate 10. According to the third photoresist structure 90, a reactive ion etching method is used, and the etching pressure is set to 12mT to 20mT, the power is set to 40W to 60W, and the SF6 gas flow rate is set to 20sccm to 40sccm, and the superconducting lead film 50 is etched to the insulating layer structure 310. By setting the etching pressure range, power range, and SF6 gas flow range, the insulating layer structure 310 can be etched without etching while ensuring that the Nb lead layer is etched cleanly. Subsequently, the third photoresist structure 90 is removed, and then the next step is performed.

[0075] A contact ultraviolet lithography machine is used to prepare a fourth photoresist structure on the surface of the insulating layer structure 310 away from the substrate 10 and the surfaces of the first superconducting lead film structure 511 and the second superconducting lead film structure 512 away from the substrate 10. According to the fourth photoresist structure, a terminal resistance structure 60 is prepared at the position close to the second superconducting lead film structure 512 and the insulating layer structure 310 (the position where the fourth photoresist structure is not provided), and a PdAu film is prepared by a magnetron sputtering method or an electron beam evaporation method. Please refer to Figure 5 In Figure 5 Terminal resistance is prepared at the left side of the middle inductor coil 200 and other parts to reduce signal reflection.

[0076] In one embodiment, when a PdAu film is prepared by magnetron sputtering, a Ti film of 8 nm to 12 nm is deposited at a power of 150 W to 250 W under a pressure of 0.1 Pa to 0.5 Pa. Then, a PdAu film is prepared under a pressure of 0.8 Pa to 1.2 Pa. At this time, the adhesion of palladium to the surfaces of the insulating layer structure 310 and the second superconducting lead thin film structure 512 can be increased by the Ti metal film.

[0077] In one embodiment, when the PdAu thin film is prepared by vacuum electron beam evaporation, the vacuum is better than 4×10 - 6 Torr~5×10 -6 In a 2400-1200 Å / min (0.1-100 nm) 200 Å / min (0.1-100 nm) titanium film is first deposited in a 2400-1200 Å / min (0.1-100 nm) ... A 110 nm to 130 nm PdAu film is deposited. After the PdAu film is deposited, the terminal resistor structure 60 is stripped off by acetone soaking for 30 minutes and ultrasonic treatment for 2 minutes to form the terminal resistor palladium gold (PdAu) of the microwave transmission line.

[0078] In one embodiment, the first superconducting film 20 is prepared on the surface of the substrate 10, comprising the following steps:

[0079] The first superconducting film 20 is prepared on the surface of the substrate 10 by using a magnetron sputtering method, setting the argon sputtering pressure in the range of 4 mTorr to 10 mTorr, and setting the superconducting material sputtering power in the range of 400 W to 600 W.

[0080] In this embodiment, the background pressure of the sputtering chamber is set to be better than 3×10-8Torr through a magnetron sputtering method or an electron beam evaporation method, the sputtering gas pressure is controlled at 4mTorr to 10mTorr, including 5mTorr, and the sputtering power of the superconducting material ranges from 400W to 600W, including 500W, to prepare the first layer of superconducting film 20 on the surface of the substrate 10.

[0081] In the magnetron sputtering preparation process, the stress of the first layer of superconducting film 20 can be changed by adjusting the argon sputtering pressure, or adjusting the superconducting material sputtering power, or adjusting the argon sputtering pressure and the superconducting material sputtering power at the same time. At this time, the stress of the first layer of superconducting film 20 can be adjusted according to the argon sputtering pressure and / or the superconducting material sputtering power, so that the overall stress of the first layer of superconducting film 20 is reduced, which is beneficial to improving the film performance and can effectively improve the performance and stability of the device.

[0082] In one embodiment, etching the surface of the first superconducting film 20 away from the substrate 10 until the substrate 10 is reached to prepare the first superconducting film structure 210, including the following steps:

[0083] According to the photoresist mask pattern, a positive ultraviolet photoresist is spin-coated on the surface of the first superconducting film 20 away from the substrate 10, and a first photoresist structure 70 is prepared by using a contact ultraviolet alignment exposure technique;

[0084] According to the first photoresist structure 70, a reactive ion etching method is used, the gas pressure range is set to 10mTorr to 15mTorr, the power range is set to 40W to 100W, and the etching gas SF6 range is set to 20sccm to 40sccm, and the surface of the first superconducting film 20 away from the substrate 10 is etched;

[0085] An optical endpoint detection method is used to monitor and control the etching process, and the etching is performed until the substrate 10 is formed to prepare the first layer of superconducting thin film structure 210 .

[0086] In this embodiment, the first superconducting film structure 210 (Nb film structure) includes a microwave coplanar waveguide (CPW) structure, a power divider structure, a phase shifter structure, an inductor and a bottom layer of the inductor structure. A positive ultraviolet photoresist (AZ6112) is spin-coated on the surface of the first superconducting film 20, and the first photoresist structure 70 is prepared by contact ultraviolet alignment exposure technology.

[0087] Among them, an optical endpoint detection method is used to detect in real time, and the etching position is detected until the etching reaches the substrate 10. The optical endpoint detection method determines the etching position according to the optical path difference between visible light and reflected light. In addition, due to the different optical reflection intensities at the interfaces of different films, the dynamics of the etching position can be monitored. Thus, the etching process of the first layer of superconducting film 20 can be accurately and stably controlled to avoid etching errors, and it can be ensured that the substrate 10 will not be etched away when the unnecessary parts of the first layer of superconducting film 20 are etched cleanly. Thus, the etching process of the first layer of superconducting film 20 can be accurately and stably controlled, thereby improving the performance and stability of the prepared Josephson junction array.

[0088] The reactive ion etching method is used, the etching pressure range is set to 15mTorr, the power range is set to 50W, and the etching gas SF6 range is set to 30sccm, and the surface of the first superconducting film 20 away from the substrate 10 is etched. When the etching is completed, the first superconducting film structure 210 is formed. Then the first photoresist structure 70 is removed.

[0089] In one embodiment, according to the bridge pattern, the surface of the first superconducting lead thin film structure 511 away from the insulating layer structure 310 is etched until the insulating layer structure 310 is etched to prepare a plurality of nanobridges 5111 to form a superconducting bridge array, and obtain a Josephson junction array structure based on a superconducting bridge, including the following steps:

[0090] According to the bridge pattern, a focused ion beam etching method is used, and a voltage range of 20KV to 40kV is set to accelerate gallium ions, bombarding the first superconducting lead film structure 511 away from the surface of the insulating layer structure 310, etching to the insulating layer structure 310, preparing the multiple nanobridges 5111, and forming the superconducting bridge array.

[0091] In this embodiment, according to the bridge pattern (see Figure 3 ), by setting the voltage range in the focused ion beam etching method to 20KV to 40kV to accelerate gallium ions, the surface of the first superconducting lead film structure 511 away from the insulating layer structure 310 can be etched in a low dimension and small size, and the surface is etched to the insulating layer structure 310, and the first superconducting lead film structure 511 is refined to form the plurality of nanobridges 5111. Figure 3 and Figure 4 , by accelerating gallium ions to collide with Figure 3 and Figure 4 The region 930 is etched to prepare the plurality of nanobridges 5111. The top view of the plurality of nanobridges 5111 can be found in Figure 6Through the focused ion beam etching method, the process is controllable and stable, and the prepared array chip can meet the quantum voltage AC and DC base standard operation requirements.

[0092] The Ga ions are accelerated by 30 kV voltage to bombard the area to be removed, leaving a nanoscale structure, and preparing the plurality of nanobridges 5111 and the plurality of first superconducting lead film substructures 5112 (the nanobridges 5111 and the first superconducting lead film substructures 5112 are superconducting lead layer films, such as Nb films). The plurality of nanobridges 5111 can realize weak connection between the plurality of first superconducting lead film substructures 5112, and the Josephson effect exists.

[0093] In one embodiment, according to the bridge pattern, the surface of the first superconducting lead thin film structure 511 away from the insulating layer structure 310 is etched until the insulating layer structure 310 is etched to prepare a plurality of nanobridges 5111 to form a superconducting bridge array, and obtain a Josephson junction array structure based on a superconducting bridge, including the following steps:

[0094] According to the bridge pattern, a second photoresist structure 80 is prepared on the surface of the first superconducting wire thin film structure 511 away from the insulating layer structure 310 by using an electron beam lithography method;

[0095] According to the second photoresist structure 80, a reactive ion etching method is adopted, the etching gas pressure range is set to 10mTorr to 20mTorr, the power range is set to 40W to 100W, and the etching gas SF6 range is set to 20sccm to 40sccm, and the surface of the first superconducting lead film structure 511 away from the insulating layer structure 310 is etched until the insulating layer structure 310 is etched to prepare the multiple nanobridges 5111 to form the superconducting bridge junction array.

[0096] In this embodiment, according to the bridge pattern (see Figure 2 ), the electron beam lithography method and the reactive ion etching method are combined, the etching pressure range, power range, and etching gas SF6 range are set, and the surface of the first superconducting lead thin film structure 511 away from the insulating layer structure 310 is etched, which can avoid the occurrence of etching errors and ensure that the insulating layer structure 310 will not be etched away when the unnecessary parts are etched cleanly. Therefore, the etching process can be accurately and stably controlled, the line accuracy can be improved, and the performance of the prepared device can be improved.

[0097] Among them, ZEP520 glue is used, and after being coated, baked and exposed, it is etched with a dry etcher. The etching pressure is set to 15mT, the power of reactive ion etching is 50W, and the SF6 gas flow rate is 30sccm. The surface of the first superconducting lead film structure 511 away from the insulating layer structure 310 is etched until the insulating layer structure 310 is etched, and part of the insulating layer structure 310 is exposed to form the multiple nanobridges 5111. The multiple nanobridges 5111 can achieve weak connection between the multiple first superconducting lead film substructures 5112, and there is a Josephson effect.

[0098] In one embodiment, the insulating layer 30 is formed on the surface of the first superconducting thin film structure 210 away from the substrate 10 and the surface of the substrate 10 close to the first superconducting thin film structure 210, including the following steps:

[0099] A low-temperature plasma-assisted chemical vapor deposition method is adopted, with the deposition temperature range set to 50°C to 70°C, the pressure range to 5mTorr to 10mTorr, the oxygen flow range to 10sccm to 50sccm, and the silane flow range to 40sccm to 60sccm, to deposit a silicon dioxide film on the surface of the first superconducting film structure 210 away from the substrate 10 and on the surface of the substrate 10 close to the first superconducting film structure 210 to form the insulating layer 30.

[0100] In this embodiment, the insulating layer 30 is deposited at a temperature below 100° C. by a low temperature plasma assisted chemical vapor deposition method. The insulating layer 30 is SiO 2. When deposited at a temperature below 100° C., the plurality of first-layer superconducting thin film structures 210 will not be oxidized during the growth of the insulating layer 30, thereby ensuring the performance of the first-layer superconducting thin film structure 210.

[0101] At the same time, by adopting a low-temperature plasma-assisted chemical vapor deposition method, setting the deposition temperature range, pressure range, oxygen flow range, and silane flow range, and depositing a silicon dioxide film, the stress of the insulating layer 30 can be adjusted, so that the overall stress of the insulating layer 30 is reduced, and the superconducting properties of the first layer superconducting film structure 210 will not be affected, which can effectively improve the performance and stability of superconducting circuit devices.

[0102] In one embodiment, the surface of the insulating layer 30 away from the substrate 10 is etched to the first superconducting thin film structure 210 to form a plurality of insulating layer structures 310, wherein the plurality of insulating layer structures 310 surround a plurality of connection hole structures 40, and the steps include:

[0103] A reactive ion etching method is adopted, with the gas pressure range set to 50mTorr to 70mTorr, the RF power range to 100W to 150W, the etching power range to 30W to 50W, the oxygen flow range to 20sccm to 30sccm, and the CHF3 flow range to 20sccm to 100sccm, to etch the surface of the insulating layer 30 away from the substrate 10 until the first layer of superconducting thin film structure 210 is reached.

[0104] In this embodiment, according to the photoresist mask pattern, a positive ultraviolet photoresist is spin-coated on the surface of the insulating layer 30 away from the substrate 10, and a contact ultraviolet alignment exposure technology is used to prepare a fifth photoresist structure 920. According to the fifth photoresist structure 920, a reactive ion etching method is used to adjust the ratio of the fluorine-based gas and oxygen in the etching atmosphere through the oxygen flow range and the CHF3 flow range, so that the occurrence of etching errors can be avoided, and it can be ensured that the Josephson junction will not be etched away when the unnecessary parts of the insulating layer 30 are etched cleanly. Therefore, the etching process of the insulating layer 30 can be accurately and stably controlled, and the performance and stability of the prepared Josephson junction array are improved.

[0105] Specifically, the etching pressure is set to 60mT, the RF power is 115W, the reactive ion etching power is 30W, the O2 flow rate is 23sccm, and the CHF3 gas flow rate is 30sccm. By adjusting the ratio of the fluorine-based gas and oxygen in the etching atmosphere, the first superconducting thin film structure 210 can be prevented from being etched away while ensuring that the insulating layer is etched cleanly. Then, the fifth photoresist structure 920 is stripped and the next step is performed.

[0106] In one embodiment, a superconducting wire film 50 is prepared on the surface of the plurality of insulating layer structures 310 away from the substrate 10 and in the plurality of connecting hole structures 40, and the steps include:

[0107] The insulating layer structure 310 and the plurality of connection hole structures 40 are covered by the superconducting wire film 50. The thickness of the superconducting wire film 50 may be 100-200 nm, and the deposition conditions are the same as those in step S20.

[0108] Compared with the conventional sandwich structured Josephson junction array chip, the method for preparing the Josephson junction array based on the superconducting bridge junction is controllable and stable in process. On the same chip size, more Josephson junctions can be highly integrated, increasing the number of junctions by an order of magnitude to meet the market demand for output voltage. Moreover, with the same number of Josephson junctions, the chip size can be greatly reduced and meet the quantum voltage AC and DC base standard operation requirements.

[0109] In one embodiment, the present application provides a Josephson junction array structure based on a superconducting bridge junction. The Josephson junction array structure based on a superconducting bridge junction includes a substrate 10, a plurality of first-layer superconducting film structures 210, a plurality of insulating layer structures 310, a plurality of nanobridges 5111, and a plurality of first superconducting wire film substructures 5112. The plurality of first-layer superconducting film structures 210 are spaced apart on the surface of the substrate 10. The plurality of insulating layer structures 310 are disposed between two adjacent first-layer superconducting film structures 210. The plurality of first superconducting wire film substructures 5112 are located on the surface of the insulating layer structure 310 at the middle surface position of the substrate 10. The plurality of nanobridges 5111 are located on the surface of the insulating layer structure 310 at the middle surface position of the substrate 10. Please refer to Figure 7 The multiple nano-bridges 5111 are connected to the multiple first superconducting wire film substructures 5112 in sequence to achieve a weak connection.

[0110] In this embodiment, the plurality of first superconducting lead film substructures 5112 can be weakly connected through the plurality of nanobridges 5111, and a Josephson effect exists, thereby forming a superconducting bridge junction array of a single superconducting film, and obtaining a Josephson junction array structure. At this time, the size of a single layer of superconducting film can be regulated, thereby reducing the period size of the smallest junction in the lateral size, and a structure with a period of 100 nm can be achieved.

[0111] Therefore, compared with the traditional sandwich-structured Josephson junction array chip, the Josephson junction array structure based on superconducting bridge junctions can highly integrate more Josephson junctions on the same chip size, increasing the number of junctions by an order of magnitude to meet the market demand for output voltage. Moreover, with the same number of Josephson junctions, the chip size can be greatly reduced.

[0112] In one embodiment, the nanobridge 5111 comprises a superconducting wire thin film layer.

[0113] In this embodiment, it can be known from the above-mentioned method for preparing a Josephson junction array based on a superconducting bridge junction that the surface of the first superconducting lead thin film structure 511 away from the insulating layer structure 310 is etched until the insulating layer structure 310 is reached, and the first superconducting lead thin film structure 511 is finely trimmed to form the plurality of nanobridges 5111. At this time, the nanobridge 5111 includes a superconducting lead thin film layer, and the plurality of first superconducting lead thin film substructures 5112 can be connected.

[0114] Therefore, the plurality of first superconducting lead film substructures 5112 are weakly connected through the plurality of nanobridges 5111, forming a superconducting bridge junction array of a single layer of superconducting film, and obtaining a Josephson junction array structure. At this time, the size of the single layer of superconducting film can be adjusted, thereby reducing the period size of the smallest junction in the lateral size.

[0115] In one embodiment, the nanobridge 5111 is nanoscale in size.

[0116] In this embodiment, the nanobridge 5111 is nanometer-sized, so that the plurality of first superconducting lead thin film substructures 5112 can be weakly connected, and the Josephson effect exists, thereby avoiding the suppression of strong correlation. The nanobridge 5111 includes a superconducting lead thin film layer, and can realize the connection between the plurality of first superconducting lead thin film substructures 5112.

[0117] In one embodiment, a nanobridge junction array structure formed by sequentially stacking multiple layers of nanobridges 5111 and first superconducting wire film substructures 5112 is formed to form multiple layers of a single superconducting film. At this time, by setting multiple layers (more than 2 layers), the number of layers in the longitudinal direction is increased as much as possible to meet the quantum voltage output. Even when multiple layers are stacked in the longitudinal direction, the heat dissipation problem can be effectively alleviated.

[0118] Therefore, compared with the traditional sandwich-structured Josephson junction array chip, the Josephson junction array structure based on superconducting bridge junctions can highly integrate more Josephson junctions on the same chip size, increasing the number of junctions by an order of magnitude. Moreover, with the same number of Josephson junctions, the chip size can be greatly reduced.

[0119] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0120] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0121] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A method for preparing a Josephson junction array based on a superconducting bridge junction, characterized in that: The steps include: Providing a substrate (10); Preparing a first layer of superconducting thin film (20) on the surface of the substrate (10); Etching the surface of the first superconducting film (20) away from the substrate (10) until the surface reaches the substrate (10), thereby preparing a plurality of first superconducting film structures (210), wherein the first superconducting film structures (210) include a microwave coplanar waveguide structure, a power divider structure, a phase shifter structure, and a bottom layer of an inductor and capacitor structure; Preparing an insulating layer (30) on surfaces of the plurality of first-layer superconducting thin film structures (210) away from the substrate (10) and on a surface of the substrate (10) close to the plurality of first-layer superconducting thin film structures (210); Etching the surface of the insulating layer (30) away from the substrate (10) until the first superconducting thin film structure (210) is reached to form a plurality of insulating layer structures (310), wherein the plurality of insulating layer structures (310) surround a plurality of connection hole structures (40); Preparing a superconducting wire film (50) on surfaces of the plurality of insulating layer structures (310) away from the substrate (10) and in the plurality of connection hole structures (40); Etching the surface of the superconducting lead film (50) away from the insulating layer structure (310) until the insulating layer structure (310) is reached to prepare a first superconducting lead film structure (511) and a second superconducting lead film structure (512), wherein the second superconducting lead film structure (512) is located on both sides of the first superconducting lead film structure (511), and each second superconducting lead film structure (512) is provided with an inductor coil on its surface; According to the bridge pattern, etching the surface of the first superconducting lead thin film structure (511) away from the insulating layer structure (310) until the insulating layer structure (310) is reached, and a plurality of nanobridges (5111) and a plurality of first superconducting lead thin film substructures (5112) are prepared; the plurality of nanobridges (5111) and the plurality of first superconducting lead thin film substructures (5112) are sequentially connected to achieve a weak connection, a Josephson effect is generated, a superconducting bridge array is formed, and a Josephson junction array structure based on superconducting bridges is obtained; The surface of the first superconducting film (20) away from the substrate (10) is etched until it reaches the substrate (10), thereby preparing a plurality of first superconducting film structures (210), comprising the following steps: According to the photoresist mask pattern, spin-coating a positive ultraviolet photoresist onto a surface of the first superconducting film (20) away from the substrate (10), and using a contact ultraviolet alignment exposure technique to prepare a first photoresist structure (70); According to the first photoresist structure (70), a reactive ion etching method is used, the gas pressure range is set to 10 mTorr to 15 mTorr, the power range is set to 40 W to 100 W, and the etching gas SF6 range is set to 20 sccm to 40 sccm, to etch the surface of the first superconducting film (20) away from the substrate (10); Using an optical endpoint detection method to monitor and control the etching process, etching to the substrate (10), and preparing the plurality of first-layer superconducting thin film structures (210); According to the bridge junction pattern, a surface of the first superconducting lead thin film structure (511) away from the insulating layer structure (310) is etched until the insulating layer structure (310) is etched, a plurality of nanobridges (5111) are prepared, a superconducting bridge junction array is formed, and a Josephson junction array structure based on the superconducting bridge junction is obtained, comprising the following steps: According to the bridge pattern, using an electron beam lithography method, a second photoresist structure (80) is prepared on a surface of the first superconducting wire thin film structure (511) away from the insulating layer structure (310); According to the second photoresist structure (80), a reactive ion etching method is used, the etching pressure range is set to 10mTorr to 20mTorr, the power range is set to 40W to 100W, and the etching gas SF6 range is set to 20 sccm to 40sccm, and the surface of the first superconducting lead film structure (511) away from the insulating layer structure (310) is etched until the insulating layer structure (310) is reached, and the plurality of nanobridges (5111) are prepared to form the superconducting bridge junction array.

2. The method for preparing a Josephson junction array based on a superconducting bridge junction according to claim 1, characterized in that: The surface of the superconducting lead film (50) away from the insulating layer structure (310) is etched until the insulating layer structure (310) is reached to prepare a first superconducting lead film structure (511) and a second superconducting lead film structure (512). After the step, the method further comprises: A terminal resistance structure (60) is prepared at a position close to the second superconducting lead thin film structure (512).

3. The method for preparing a Josephson junction array based on a superconducting bridge junction according to claim 1, characterized in that: Preparing a first layer of superconducting thin film (20) on the surface of the substrate (10) comprises the following steps: The first layer of superconducting film (20) is prepared on the surface of the substrate (10) by using a magnetron sputtering method, setting the argon sputtering pressure in the range of 4 mTorr to 10 mTorr, and setting the superconducting material sputtering power in the range of 400 W to 600 W.

4. The method for preparing a Josephson junction array based on a superconducting bridge junction according to claim 1, characterized in that: An insulating layer (30) is prepared on a surface of the plurality of first-layer superconducting thin film structures (210) away from the substrate (10) and a surface of the substrate (10) close to the plurality of first-layer superconducting thin film structures (210), comprising the following steps: A low-temperature plasma-assisted chemical vapor deposition method is adopted, with the deposition temperature range set to 50°C to 70°C, the pressure range set to 5mTorr to 10mTorr, the oxygen flow range set to 10sccm to 50sccm, and the silane flow range set to 40sccm to 60sccm, to deposit a silicon dioxide film on surfaces of the plurality of first-layer superconducting film structures (210) away from the substrate (10) and on surfaces of the substrate (10) close to the plurality of first-layer superconducting film structures (210) to form the insulating layer (30).

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