Gallium nitride semiconductor device and preparation method thereof

Abstract

The present invention provides a gallium nitride semiconductor device and a preparation method thereof. The gallium nitride semiconductor device comprises a gallium nitride epitaxial wafer and a source, a gate, and a drain thereon, and also comprises a first dielectric layer, an ohmic metal layer, a second dielectric layer, a third dielectric layer, and a gate metal contact formed sequentially on the gallium nitride epitaxial wafer; the ohmic metal layer comprises a source ohmic contact and a drain ohmic contact, the source passes through the third dielectric layer and the second dielectric layer sequentially and is connected to the source ohmic contact, the drain passes through the third dielectric layer and the second dielectric layer sequentially and is connected to the drain ohmic contact, and the gate is connected to the gate metal contact; the gallium nitride epitaxial wafer comprises a barrier layer and a cap layer, the source ohmic contact and the drain ohmic contact both extend downward to the barrier layer, and the gate metal contact extends downward to the cap layer. The gallium nitride semiconductor device can obtain additional protection for the ohmic metal during the gate metal etching process, thereby reducing the difficulty of the gate metal etching process.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a gallium nitride semiconductor device and a preparation method thereof. Background Art

[0002] Gallium nitride semiconductor devices have very broad application prospects in the field of power amplification. In the manufacturing process of gallium nitride semiconductor devices, the etching of the gate metal will damage the nearby ohmic metal, especially in the process of over-etching. Over-etching is an indispensable step in dry etching, which can ensure that the etched film is fully removed. However, in certain specific cases, over-etching will damage the underlying structure. Usually, increasing the etching selectivity and reducing the over-etching amount are used to reduce the risk of damage to the underlying structure. However, high selectivity etching has certain challenges and certain limits, and reducing the over-etching amount will increase the risk of residual etched film. Summary of the invention

[0003] The first object of the present invention is to provide a gallium nitride semiconductor device in which the ohmic metal can be additionally protected during the gate metal etching process, thereby reducing the difficulty of the gate metal etching process.

[0004] A second object of the present invention is to provide a method for preparing the above-mentioned gallium nitride semiconductor device.

[0005] To achieve the above first objective, the present invention provides a gallium nitride semiconductor device, comprising a gallium nitride epitaxial wafer and a source, a gate, and a drain located on the gallium nitride epitaxial wafer; the gallium nitride semiconductor device also comprises a first dielectric layer, an ohmic metal layer, a second dielectric layer, a third dielectric layer, and a gate metal contact portion sequentially formed on the gallium nitride epitaxial wafer; the ohmic metal layer comprises a source ohmic contact portion and a drain ohmic contact portion, the source electrode sequentially passes through the third dielectric layer and the second dielectric layer and is connected to the source ohmic contact portion, the drain electrode sequentially passes through the third dielectric layer and the second dielectric layer and is connected to the drain ohmic contact portion, and the gate is connected to the gate metal contact portion; the gallium nitride epitaxial wafer comprises a barrier layer and a cap layer, the cap layer is located above the barrier layer, the source ohmic contact portion and the drain ohmic contact portion both extend downward to the barrier layer, and the gate metal contact portion extends downward to the cap layer.

[0006] A preferred solution is that the gallium nitride epitaxial wafer further includes a substrate and a transition layer and a channel layer formed in sequence on the substrate, and the barrier layer is formed above the channel layer.

[0007] A preferred solution is that the material of the first dielectric layer is one of silicon nitride, silicon oxide, aluminum nitride, and aluminum oxide, or a combination of two or more thereof.

[0008] A preferred solution is that the material of the second dielectric layer is one of silicon nitride, silicon oxide, aluminum nitride, and aluminum oxide, or a combination of two or more thereof.

[0009] A preferred solution is that the material of the third dielectric layer is one of silicon nitride, silicon oxide, aluminum nitride, and aluminum oxide, or a combination of two or more thereof.

[0010] In a preferred embodiment, the thickness of the first dielectric layer is in the range of 5 micrometers to 500 micrometers.

[0011] A preferred solution is that the material of the ohmic metal layer is Ti / Al / Ti / TiN alloy, the material of the gate metal contact is TiN / Al / TiN alloy, and the materials of the source, gate and drain are all Ti / Al / TiN alloy.

[0012] To achieve the above second objective, the present invention provides a method for preparing the above gallium nitride semiconductor device, comprising depositing a first dielectric layer on a gallium nitride epitaxial wafer; opening an ohmic contact hole on the first dielectric layer, the ohmic contact hole extending downward to the barrier layer; depositing an ohmic metal layer; depositing a second dielectric layer; etching the second dielectric layer and the ohmic metal layer to form a source ohmic contact portion and a drain ohmic contact portion; depositing a third dielectric layer; opening a gate metal through hole on the third dielectric layer, the gate metal through hole extending downward to the cap layer; depositing a gate metal layer; etching the gate metal layer to form a gate metal contact portion; manufacturing a source, a gate and a drain, the source being connected to the source ohmic contact portion, the gate being connected to the gate metal contact portion, and the drain being connected to the drain ohmic contact portion.

[0013] A preferred solution is that the steps of making the source, gate and drain include: depositing a fourth dielectric layer; opening a source contact hole, a gate contact hole and a drain contact hole on the fourth dielectric layer, the source contact hole extending downward to the source ohmic contact portion, the gate contact hole extending downward to the gate metal contact portion, and the drain contact hole extending downward to the drain ohmic contact portion; depositing an electrode metal layer; and patterning the electrode metal layer to form a source, a gate and a drain.

[0014] A further solution is that the fourth dielectric layer is one of silicon nitride, silicon oxide, aluminum nitride, and aluminum oxide, or a combination of two or more thereof.

[0015] The beneficial effect of the present invention is that by pre-depositing the second dielectric layer on the lower ohmic metal layer, the ohmic metal layer is additionally protected during the gate metal etching process, reducing the difficulty of the gate metal etching process. At the same time, the second dielectric layer and the third dielectric layer will protect the top of the ohmic metal layer together, making the selection of the thickness of the third dielectric layer more flexible. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a schematic diagram of the structure of a gallium nitride epitaxial wafer in an embodiment of a gallium nitride semiconductor device of the present invention.

[0017] Figure 2 It is a schematic diagram of a gallium nitride semiconductor device embodiment of the present invention after a first dielectric layer is deposited on a gallium nitride epitaxial wafer.

[0018] Figure 3 It is a schematic diagram of a gallium nitride semiconductor device embodiment of the present invention after an ohmic contact hole is opened.

[0019] Figure 4 It is a schematic diagram of a gallium nitride semiconductor device embodiment of the present invention after an ohmic metal layer is deposited.

[0020] Figure 5 It is a schematic diagram of the gallium nitride semiconductor device embodiment of the present invention after the second dielectric layer is deposited.

[0021] Figure 6 It is a schematic diagram of the gallium nitride semiconductor device embodiment of the present invention after etching the second dielectric layer and the ohmic metal layer.

[0022] Figure 7 It is a schematic diagram of the gallium nitride semiconductor device embodiment of the present invention after the third dielectric layer is deposited.

[0023] Figure 8 It is a schematic diagram of a gallium nitride semiconductor device embodiment of the present invention after a gate metal through hole is opened on the third dielectric layer.

[0024] Fig. 9 It is a schematic diagram of a gallium nitride semiconductor device embodiment of the present invention after a gate metal layer is deposited.

[0025] Fig.10 It is a schematic diagram of the gallium nitride semiconductor device embodiment of the present invention after etching the gate metal layer.

[0026] Fig.11 It is a schematic diagram of the gallium nitride semiconductor device embodiment of the present invention after the fourth dielectric layer is deposited.

[0027] Fig.12 It is a schematic diagram of the gallium nitride semiconductor device embodiment of the present invention after the electrode contact holes are opened.

[0028] Fig.13 It is a schematic diagram of the gallium nitride semiconductor device embodiment of the present invention after the electrode metal layer is deposited.

[0029] Fig.14 It is a schematic diagram of the gallium nitride semiconductor device embodiment of the present invention after the electrode metal layer is patterned.

[0030] The present invention is further described below in conjunction with the accompanying drawings and embodiments. DETAILED DESCRIPTION

[0031] See also Figure 1 and Fig.14The gallium nitride semiconductor device includes a gallium nitride epitaxial wafer 1 and a source 2, a gate 3, and a drain 4 located on the gallium nitride epitaxial wafer 1. In the horizontal direction, the gate 3 is located between the source 2 and the drain 4. The gallium nitride epitaxial wafer 1 includes a substrate 11 and a transition layer 12, a channel layer 13, a barrier layer 14 and a cap layer 15 formed in sequence on the substrate 11.

[0032] The gallium nitride semiconductor device further includes a first dielectric layer 5, an ohmic metal layer 6, a second dielectric layer 7, a third dielectric layer 8, a gate metal contact 31, and a fourth dielectric layer 9, which are sequentially formed on the gallium nitride epitaxial wafer 1. The ohmic metal layer 6 includes a source ohmic contact 21 and a drain ohmic contact 41. The source 2 sequentially passes through the fourth dielectric layer 9, the third dielectric layer 8, and the second dielectric layer 7 and is connected to the source ohmic contact 21. The drain 4 sequentially passes through the fourth dielectric layer 9, the third dielectric layer 8, and the second dielectric layer 7 and is connected to the drain ohmic contact 41. The gate 3 passes through the fourth dielectric layer 9 and is connected to the gate metal contact 31. The source ohmic contact 21 and the drain ohmic contact 41 both extend downward to the barrier layer 14, and the gate metal contact 31 extends downward to the cap layer 15.

[0033] The material of the substrate 11 is silicon, silicon carbide or sapphire, the material of the channel layer 13 is gallium nitride, and the material of the barrier layer 14 is aluminum gallium nitride. The materials of the first dielectric layer 5, the second dielectric layer 7, the third dielectric layer 8 and the fourth dielectric layer 9 are all one or a combination of two or more of silicon nitride, silicon oxide, aluminum nitride and aluminum oxide. The materials of the second dielectric layer 7 and the third dielectric layer 8 can be the same or different. The thickness of the first dielectric layer 5 is in the range of 5 microns to 500 microns. The ohmic metal layer 6, the gate metal contact 31, the source 2, the gate 3 and the drain 4 are all metal alloys formed by multi-layer metal deposition, the material of the ohmic metal layer 6 is Ti / Al / Ti / TiN alloy, the material of the gate metal contact 31 is TiN / Al / TiN alloy, and the materials of the source 2, the gate 3 and the drain 4 are all Ti / Al / TiN alloy.

[0034] See also Figures 1 to 14 , a method for preparing a gallium nitride semiconductor device includes the following steps.

[0035] First, prepare Figure 1 The gallium nitride epitaxial wafer 1 is shown.

[0036] Next, a chemical vapor deposition (CVD), physical vapor deposition (PVD) or atomic layer deposition (ALD) method is used to deposit a GaN epitaxial wafer 1 to form a Figure 2 The first dielectric layer 5 is shown.

[0037] Next, semiconductor photolithography and etching techniques are used to create a hole on the first dielectric layer 5. Figure 3The ohmic contact hole 51 shown in the figure extends downward to the barrier layer 14. The photolithography technology includes the steps of coating, soft baking, exposure, development, and hardening.

[0038] Then, if Figure 4 As shown, an ohmic metal layer 6 is formed above the first dielectric layer 5 and in the ohmic contact hole 51 by multi-layer metal deposition. The multi-layer metal layers are deposited in the order of Ti, Al, Ti, and TiN to form a Ti / Al / Ti / TiN alloy.

[0039] Then, if Figure 5 As shown, a second dielectric layer 7 is formed on the ohmic metal layer 6 by deposition.

[0040] Next, the second dielectric layer 7 and the ohmic metal layer 6 are etched, and the ohmic metal layer 6 that is not removed is formed as shown in FIG. Figure 6 The source ohmic contact 21 and the drain ohmic contact 41 are shown.

[0041] Then, if Figure 7 As shown, a third dielectric layer 8 is formed on the second dielectric layer 7 and on the exposed first dielectric layer 5 by deposition.

[0042] Then, if Figure 8 As shown, a gate metal through hole 81 is opened on the third dielectric layer 8 , and the gate metal through hole 81 penetrates the third dielectric layer 8 and the first dielectric layer 5 and extends downward to the cap layer 15 .

[0043] Next, multiple layers of metal are deposited to form Fig. 9 As shown in the gate metal layer 30 , multiple metal layers are deposited in the order of TiN, Al, and TiN to form a TiN / Al / TiN alloy.

[0044] Next, the gate metal layer 30 is etched, and the unremoved portion forms a Fig.10 A gate metal contact 31 is shown.

[0045] Then, if Fig.11 As shown, a fourth dielectric layer 9 is formed on the gate metal layer 30 and the third dielectric layer 8 by deposition.

[0046] Then, if Fig.12 As shown, a source contact hole 91, a gate contact hole 92 and a drain contact hole 93 are opened on the fourth dielectric layer 9. The source contact hole 91 sequentially penetrates the fourth dielectric layer 9, the third dielectric layer 8, the second dielectric layer 7 and extends downward to the source ohmic contact portion 21. The gate contact hole 92 penetrates the fourth dielectric layer 9 and extends downward to the gate metal contact portion 31. The drain contact hole 93 sequentially penetrates the fourth dielectric layer 9, the third dielectric layer 8, the second dielectric layer 7 and extends downward to the drain ohmic contact portion 41.

[0047] Then, if Fig.13 As shown, an electrode metal layer 90 is formed by multi-layer metal deposition above the fourth dielectric layer 9 and in the source contact hole 91, the gate contact hole 92 and the drain contact hole 93. The multi-layer metal is deposited in the order of Ti, Al and TiN to form a Ti / Al / TiN alloy.

[0048] Finally, the electrode metal layer 90 is patterned by using semiconductor photolithography technology and etching technology to form Fig.14 The source 2 , the gate 3 and the drain 4 are shown, the source 2 is connected to the source ohmic contact 21 , the gate 3 is connected to the gate metal contact 31 , and the drain 4 is connected to the drain ohmic contact 41 .

[0049] As can be seen from the above, the purpose of the third dielectric layer is to protect the underlying material when etching metal, especially to protect the top of the ohmic metal layer. By pre-depositing the second dielectric layer on the lower ohmic metal layer, the ohmic metal layer is additionally protected during the gate metal etching process, thereby reducing the difficulty of the gate metal etching process. At the same time, the second dielectric layer and the third dielectric layer will protect the top of the ohmic metal layer together, making the selection of the thickness of the third dielectric layer more flexible.

[0050] Finally, it should be emphasized that the above are only preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various changes and modifications. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A gallium nitride semiconductor device, characterized in that: It includes a gallium nitride epitaxial wafer and a source electrode, a gate electrode, and a drain electrode located on the gallium nitride epitaxial wafer; The gallium nitride semiconductor device further includes a first dielectric layer, an ohmic metal layer, a second dielectric layer, a third dielectric layer and a gate metal contact portion which are sequentially formed on the gallium nitride epitaxial wafer; The ohmic metal layer includes a source ohmic contact portion and a drain ohmic contact portion, the source electrode sequentially passes through the third dielectric layer and the second dielectric layer and is connected to the source ohmic contact portion, the drain electrode sequentially passes through the third dielectric layer and the second dielectric layer and is connected to the drain ohmic contact portion, and the gate electrode is connected to the gate metal contact portion; The gallium nitride epitaxial wafer comprises a barrier layer and a cap layer, wherein the cap layer is located above the barrier layer, the source ohmic contact portion and the drain ohmic contact portion both extend downward to the barrier layer, and the gate metal contact portion extends downward to the cap layer; The gallium nitride epitaxial wafer further includes a substrate, and a transition layer and a channel layer sequentially formed on the substrate, and the barrier layer is formed above the channel layer; The material of the first dielectric layer is one of silicon nitride, silicon oxide, aluminum nitride and aluminum oxide, or a combination of two or more thereof.

2. The gallium nitride semiconductor device according to claim 1, characterized in that: The material of the second dielectric layer is one of silicon nitride, silicon oxide, aluminum nitride and aluminum oxide, or a combination of two or more thereof.

3. The gallium nitride semiconductor device according to claim 1, characterized in that: The material of the third dielectric layer is one of silicon nitride, silicon oxide, aluminum nitride and aluminum oxide, or a combination of two or more thereof.

4. The gallium nitride semiconductor device according to any one of claims 1 to 3, characterized in that: The thickness of the first dielectric layer is in the range of 5 micrometers to 500 micrometers.

5. The gallium nitride semiconductor device according to any one of claims 1 to 3, characterized in that: The material of the ohmic metal layer is Ti / Al / Ti / TiN alloy, the material of the gate metal contact is TiN / Al / TiN alloy, and the materials of the source, the gate and the drain are all Ti / Al / TiN alloy.

6. A method for preparing a gallium nitride semiconductor device, characterized in that: The gallium nitride semiconductor device is a gallium nitride semiconductor device according to any one of claims 1 to 5; The preparation method comprises: Depositing a first dielectric layer on the gallium nitride epitaxial wafer; An ohmic contact hole is formed on the first dielectric layer, and the ohmic contact hole extends downward to the barrier layer; depositing an ohmic metal layer; depositing a second dielectric layer; Etching the second dielectric layer and the ohmic metal layer to form a source ohmic contact portion and a drain ohmic contact portion; depositing a third dielectric layer; A gate metal through hole is formed on the third dielectric layer, wherein the gate metal through hole extends downward to the cap layer; depositing a gate metal layer; Etching the gate metal layer to form a gate metal contact portion; A source electrode, a gate electrode and a drain electrode are manufactured, wherein the source electrode is connected to the source ohmic contact portion, the gate electrode is connected to the gate metal contact portion, and the drain electrode is connected to the drain ohmic contact portion.

7. The method for preparing a gallium nitride semiconductor device according to claim 6, characterized in that: The steps of making the source, the gate and the drain include: depositing a fourth dielectric layer; A source contact hole, a gate contact hole and a drain contact hole are formed on the fourth dielectric layer, wherein the source contact hole extends downward to the source ohmic contact portion, the gate contact hole extends downward to the gate metal contact portion, and the drain contact hole extends downward to the drain ohmic contact portion; Depositing electrode metal layers; The electrode metal layer is patterned to form the source electrode, the gate electrode and the drain electrode.

8. The method for preparing a gallium nitride semiconductor device according to claim 7, characterized in that: The fourth dielectric layer is one of silicon nitride, silicon oxide, aluminum nitride, and aluminum oxide, or a combination of two or more thereof.

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