Lead frame for chip packaging, preparation method and chip packaging structure

Abstract

The present invention discloses a lead frame for chip packaging, a preparation method and a chip packaging structure. The lead frame includes a carrier sheet, a first solder resist ink layer and a plurality of unit circuits arranged in a matrix, the unit circuit includes a plurality of electrodes, the electrodes include a top electrode and a bottom electrode; the top electrode is arranged on the top surface of the first solder resist ink layer; corresponding to each unit circuit, the first solder resist ink layer includes a bottom electrode hole corresponding to the electrode, the bottom electrode is arranged in the bottom electrode hole, and the top of the bottom electrode is fixed on the bottom surface of the top electrode; the carrier sheet is peelably attached to the first solder resist ink layer and the bottom surface of the bottom electrode. The lead frame preparation process of the present invention has few steps, a simple process and low cost.

Description

[Technical field]

[0001] The invention relates to chip packaging, and in particular to a lead frame used for chip packaging, a preparation method and a chip packaging structure. [Background Technology]

[0002] The main function of the lead frame is to provide a mechanical support carrier for the chip, and to serve as a conductive medium to connect the chip circuit inside and outside to form an electrical signal path, and to dissipate the heat generated by the chip when it is working together with the packaging shell.

[0003] The invention with application number CN202010538887.5 discloses a lead frame for chip packaging and a preparation method. The lead frame includes a substrate, a base island and a plurality of pins arranged around the periphery of the base island. The base island includes an upper base island arranged above the substrate, a lower base island arranged below the substrate, and a metal island that penetrates the substrate and connects the upper base island and the lower base island. The pins include an upper pin arranged above the substrate, a lower pin arranged below the substrate, and a metal column that penetrates the substrate and connects the upper pin and the lower pin. This invention uses electrophoretic resin filled in the groove etched in the copper foil as the substrate. The etching of the copper foil needs to be covered with a photosensitive film. It is difficult to match the etching depth of the copper foil groove and the thickness of the filled electrophoretic resin. The curing process of the electrophoretic resin will have a greater impact on the film-fading performance of the photosensitive layer. In addition, the plating cylinder of the electrophoretic process requires strict maintenance. The invention is complex and costly. [Summary of the invention]

[0004] The technical problem to be solved by the present invention is to provide a lead frame with fewer preparation steps and simpler process.

[0005] Another technical problem to be solved by the present invention is to provide a method for preparing a lead frame with fewer preparation steps and simpler process.

[0006] Another technical problem to be solved by the present invention is to provide a chip packaging structure with a lead frame having fewer process steps and a simple process.

[0007] In order to solve the above technical problems, the technical solution adopted by the present invention is a lead frame for chip packaging, comprising a carrier sheet, a first solder resist ink layer and a plurality of unit circuits arranged in a matrix, the unit circuit comprising a plurality of electrodes, the electrodes comprising a top electrode and a bottom electrode; the top electrode is arranged on the top surface of the first solder resist ink layer; corresponding to each unit circuit, the first solder resist ink layer comprises a bottom electrode hole corresponding to the electrode, the bottom electrode is arranged in the bottom electrode hole, and the top of the bottom electrode is fixed on the bottom surface of the top electrode; the carrier sheet is removably adhered to the bottom surfaces of the first solder resist ink layer and the bottom electrode.

[0008] The lead frame described above, the unit circuit includes a base island, the base island includes an upper base island and a lower base island, the upper base island is arranged on the top surface of the first solder resist ink layer; corresponding to each unit circuit, the first solder resist ink layer includes a base island hole, and the lower base island is arranged in the base island hole; the top of the lower base island is fixed on the bottom surface of the upper base island; the carrier sheet is removably adhered to the bottom surface of the lower base island.

[0009] In the lead frame described above, the lateral size of the top electrode is larger than that of the bottom electrode, and the top electrode fully covers the bottom electrode hole; the lateral size of the upper base island is larger than that of the lower base island, and the upper base island fully covers the base island hole; the height of the upper base island is the same as that of the top electrode.

[0010] The lead frame described above, the top electrode includes a copper foil layer arranged on the top surface of the first solder resist ink layer and a solderable metal layer electroplated on the top surface of the copper foil layer; the bottom electrode includes an alkali corrosion-resistant metal layer filled in the bottom electrode hole of the first solder resist ink layer and electroplated on the bottom surface of the top electrode and a solderable metal layer electroplated on the bottom surface of the alkali corrosion-resistant metal layer.

[0011] The lead frame described above, the upper base island includes a copper foil layer arranged on the top surface of the first solder resist ink layer and a solderable metal layer electroplated on the top surface of the copper foil layer; the lower base island includes an alkali corrosion-resistant metal layer filled in the base island hole of the first solder resist ink layer and plated on the bottom surface of the upper base island.

[0012] In the lead frame described above, the alkali corrosion-resistant metal layer is a nickel-plated layer, a tin-plated layer, a silver-plated layer, or a composite layer of at least two of nickel, tin and silver, and the solderable metal layer is a copper-plated layer, a nickel-plated layer, a tin-plated layer, a silver-plated layer, a gold-plated layer, or a composite layer of at least two of copper-plated layer, nickel-plated layer, tin-plated layer, silver-plated layer and gold-plated layer.

[0013] The lead frame described above comprises a second solder resist ink layer, which covers the first solder resist ink layer and the top electrode; the second solder resist ink layer comprises a window, and the pad of the top electrode is arranged in the window of the second solder resist ink layer.

[0014] A method for preparing the lead frame comprises the following steps:

[0015] 801) affixing a carrier film on the top surface of the copper foil and printing a first solder resist ink layer on the bottom surface of the copper foil;

[0016] 802) photoetching a bottom electrode hole on the first solder resist ink layer, and plating a metal layer on the bottom surface of the copper foil in the bottom electrode hole to form a bottom electrode filled in the bottom electrode hole;

[0017] 803) attaching the carrier sheet to the bottom surface of the first solder resist ink layer and the bottom electrode in a releasable manner;

[0018] 804) peeling off the carrier film on the top surface of the copper foil, and covering the top surface of the copper foil with a photosensitive layer;

[0019] 805) The photosensitive layer is photolithographically formed into a hollowed-out pattern corresponding to the top electrode, and the copper foil is etched to form a top electrode above the first solder resist ink layer.

[0020] The above-mentioned preparation method comprises the following steps:

[0021] 901) The unit circuit includes a base island, and the base island includes an upper base island and a lower base island; in step 802, a base island hole corresponding to each unit circuit is photoetched on the first solder resist ink layer, and a metal layer is plated on the bottom surface of the copper foil in the base island hole to form a lower base island filled in the base island hole;

[0022] 902) In step 803, the carrier sheet is simultaneously peelably attached to the bottom surface of the lower base island;

[0023] 903) In step 805, the pattern produced by photolithography of the photosensitive layer includes a pattern corresponding to the upper base island, and when the copper foil is etched, the upper base island is simultaneously formed above the first solder resist ink layer.

[0024] The above-mentioned preparation method comprises the following steps:

[0025] 1001) In step 805, the solid part of the hollowed-out pattern of the photosensitive layer corresponds to the shape of the top electrode;

[0026] 1002) performing acid etching on the copper foil to etch away the copper foil exposed by the hollow pattern;

[0027] 1003) The photosensitive layer is removed, and a solderable metal layer is plated on the copper foil remaining after etching to form a top electrode.

[0028] The above-mentioned preparation method comprises the following steps:

[0029] 1101) In step 805, the hollowed-out portion of the hollowed-out pattern of the photosensitive layer corresponds to the shape of the top electrode;

[0030] 1102) electroplating an alkali-resistant and solderable metal layer on the top surface of the copper foil in the hollowed-out portion of the photosensitive layer;

[0031] 1103) remove the photosensitive layer, perform alkaline etching on the copper foil, and etch away the solderable metal layer that is not coated with alkaline corrosion resistance and the exposed copper foil to form a top electrode.

[0032] In the above-described preparation method, after step 805 is completed, a second solder resist ink layer is printed above the first solder resist ink layer and the top electrode; the second solder resist ink layer includes a window, and the pad of the top electrode is arranged in the window of the second solder resist ink layer.

[0033] A chip packaging structure comprises a chip, a packaging glue layer, a plurality of electrodes and a first solder resist ink layer, wherein the electrodes comprise a top electrode and a bottom electrode, and the top electrode is arranged on the top surface of the first solder resist ink layer; the first solder resist ink layer comprises a bottom electrode hole corresponding to the electrode, and the bottom electrode hole is located directly below the top electrode; the bottom electrode is arranged in the bottom electrode hole, and the top of the bottom electrode is fixed on the bottom surface of the top electrode; the packaging glue layer covers the first solder resist ink layer and the top electrode, the chip is packaged in the packaging glue layer, and the plurality of electrodes of the chip are electrically connected to the plurality of top electrodes respectively.

[0034] The lead frame preparation process of the present invention has fewer steps, a simple process and low cost. [Drawings]

[0035] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0036] Figure 1 It is a schematic diagram of step 1 of the lead frame preparation method of embodiment 2 of the present invention.

[0037] Figure 2 It is a schematic diagram of the first step of step 2 of the lead frame preparation method of embodiment 2 of the present invention.

[0038] Figure 3 It is a schematic diagram of the second step of step 2 of the lead frame preparation method of embodiment 2 of the present invention.

[0039] Figure 4 It is a schematic diagram of step 3 of the lead frame preparation method of embodiment 2 of the present invention.

[0040] Figure 5 It is a schematic diagram of the first step of step 4 of the lead frame preparation method of embodiment 2 of the present invention.

[0041] Figure 6 It is a schematic diagram of the second step of step 4 of the lead frame preparation method of Example 2 of the present invention.

[0042] Figure 7 It is a schematic diagram of step 5 of the lead frame preparation method of embodiment 2 of the present invention.

[0043] Figure 8 It is a schematic diagram of the first step of step 6 of the lead frame preparation method of embodiment 2 of the present invention.

[0044] Fig. 9 It is a schematic diagram of the second step of step 6 of the lead frame preparation method of Example 2 of the present invention.

[0045] Fig.10 It is a schematic diagram of step 7 of the lead frame preparation method of Example 2 of the present invention.

[0046] Fig.11It is a structural diagram of the lead frame of Example 1 of the present invention.

[0047] Fig.12 The structural diagram of the flip-chip LED chip packaging structure of Example 4 of the present invention,

[0048] Fig.13 It is a schematic diagram of step 5 of the lead frame preparation method of embodiment 3 of the present invention.

[0049] Fig.14 It is a schematic diagram of step 6 of the lead frame preparation method of Example 3 of the present invention.

[0050] Fig.15 It is a schematic diagram of the first step of step 7 of the lead frame preparation method in Example 3 of the present invention.

[0051] Fig.16 It is a schematic diagram of the second step of step 7 of the lead frame preparation method of Example 3 of the present invention.

[0052] Fig.17 It is a structural diagram of another form of the lead frame of Example 1 of the present invention.

[0053] Fig.18 It is a schematic diagram of the first step of step 1 of the lead frame preparation method of embodiment 6 of the present invention.

[0054] Fig.19 It is a schematic diagram of the second step of step 1 of the lead frame preparation method of Example 6 of the present invention.

[0055] Fig. 20 It is a schematic diagram of step 2 of the lead frame preparation method of Example 6 of the present invention.

[0056] Fig.21 It is a schematic diagram of step 3 of the lead frame preparation method of Example 6 of the present invention.

[0057] Fig. 22 It is a schematic diagram of step 4 of the lead frame preparation method of Example 6 of the present invention.

[0058] Fig.23 It is a schematic diagram of step 5 of the lead frame preparation method of Example 6 of the present invention.

[0059] Fig.24 It is a structural diagram of the lead frame of Example 5 of the present invention.

[0060] Fig.25 It is a schematic diagram of step 1 of the lead frame preparation method of Example 7 of the present invention.

[0061] Fig.26 It is a schematic diagram of step 2 of the lead frame preparation method of Example 7 of the present invention.

[0062] Fig. 27It is a schematic diagram of step 3 of the lead frame preparation method of Example 7 of the present invention.

[0063] Fig.28 It is a structural diagram of another form of the lead frame of Example 5 of the present invention.

[0064] Fig.29 It is a structural diagram of the packaging structure of the upright chip according to Example 8 of the present invention. [Specific implementation method]

[0065] Embodiment 1 of the present invention is a lead frame for chip packaging. The structure of a unit circuit is as follows: Fig.11 As shown, it includes a carrier sheet 2, a solder resist ink layer 3, a second solder resist ink layer and a plurality of unit circuits arranged in a matrix, each unit circuit includes two electrodes, and the electrodes include a top electrode 11 and a bottom electrode 12. The top electrode 11 is arranged on the top surface of the solder resist ink layer 3. Corresponding to each unit circuit, the solder resist ink layer 3 includes two bottom electrode holes 31, the bottom electrode 12 is arranged in the bottom electrode hole 31, and the top of the bottom electrode 12 is fixed on the bottom surface of the top electrode 11. The carrier sheet 2 is peelably attached to the bottom surface of the solder resist ink layer 3 and the bottom electrode 12.

[0066] In this embodiment, the lateral dimension of the top electrode 11 is greater than the lateral dimension of the bottom electrode 12, and the top electrode 11 can completely cover the bottom electrode hole 31. This structural feature is mainly used to prevent the corrosion of the bottom electrode 12 by the alkaline solution during alkaline etching to protect the bottom electrode 12. When the bottom electrode 12 adopts an alkaline corrosion-resistant metal, it is not a necessary structural feature for the top electrode 11 to completely cover the bottom electrode hole 31.

[0067] The top electrode 11 includes a copper foil layer 1 arranged on the top surface of the solder resist ink layer 3 and a solderable metal layer 112 electroplated on the top surface of the copper foil layer 1. The solderable metal layer 112 on the top surface of the copper foil layer 1 can cover the entire outer surface of the top electrode 11, or the solderable metal layer 112 on the top surface of the copper foil layer 1 can only cover the outer surface of the pad portion of the top electrode 11. The bottom electrode 12 includes an alkali corrosion-resistant metal layer 121 filled in the bottom electrode hole 31 of the solder resist ink layer 3 and electroplated on the bottom surface of the top electrode 11, and a solderable metal layer 122 electroplated on the bottom surface of the alkali corrosion-resistant metal layer 121.

[0068] The alkali corrosion resistant metal layer 121 may be a nickel-plated layer, a tin-plated layer, a silver-plated layer or a composite layer of at least two of nickel, tin and silver, and the solderable metal layer 122 may be a tin-plated layer, a silver-plated layer or a gold-plated layer.

[0069] The solder resist ink layer 7 covers the solder resist ink layer 3 and the top electrode 11. The solder resist ink layer 7 has a window, and the pad portion of the top electrode 11 is arranged in the window of the second solder resist ink.

[0070] Embodiment 2 of the present invention is a method for preparing the lead frame of Embodiment 1, using acid etching, and comprising the following steps:

[0071] 1) If Figure 1 As shown, a carrier film 10 is attached to the top surface of the copper foil 1, and a photosensitive ink is printed on the bottom surface of the copper foil 1 to form a solder resist ink layer 3.

[0072] 2) If Figure 2 As shown, two bottom electrode holes 31 are photoetched on the solder resist ink layer 3 for each unit circuit. Figure 3 As shown, a metal layer is plated on the bottom surface of the copper foil 1 in the bottom electrode hole 31 to form a bottom electrode 12 filled in the bottom electrode hole 31. The metal layer plated on the bottom electrode 12 includes an alkali corrosion-resistant metal layer 121 electroplated on the bottom surface of the top electrode 11 and a solderable metal layer 122 electroplated on the bottom surface of the alkali corrosion-resistant metal layer 121. The alkali corrosion-resistant metal layer 121 can be a nickel-plated layer, a tin-plated layer, a silver-plated layer, or a composite layer of at least two of nickel, tin and silver, and the solderable metal layer 122 can be a tin-plated layer, a silver-plated layer, or a gold-plated layer.

[0073] 3) If Figure 4 As shown, the carrier sheet 2 is peelably adhered to the bottom surface of the solder resist ink layer 3 and the bottom electrode 12 .

[0074] 4) If Figure 5 As shown, the carrier film 10 on the top surface of the copper foil 1 is peeled off. Figure 6 As shown, the top surface of the copper foil 1 is covered with a photosensitive layer 6 .

[0075] 5) If Figure 7 As shown, the photosensitive layer is photolithographically manufactured into a hollowed-out pattern corresponding to the top electrode 11 of each unit circuit, and the remaining solid portion 61 of the hollowed-out pattern of the photosensitive layer corresponds to the shape of the top electrode 11 .

[0076] 6) If Figure 8 As shown, the copper foil 1 is acid-etched to etch away the copper foil 1 exposed by the hollow pattern. Fig. 9 As shown, the photosensitive layer 6 is removed to form the main part of the top electrode 11.

[0077] 7) If Fig.10 As shown, a solder resist ink layer 7 is printed on the solder resist ink layer 3 and the main part of the top electrode 11. A window 71 is opened in the solder resist ink layer 7, and the pad part 111 of the top electrode 11 is exposed in the window of the second solder resist ink.

[0078] 8) If Fig.11 As shown, the pad portion 111 of the top electrode 11 is plated with a solderable metal layer 112, which may be a tin-plated layer, a silver-plated layer or a gold-plated layer, to obtain the lead frame of Embodiment 1 of the present invention.

[0079] Embodiment 3 of the present invention is another method for preparing the lead frame of Embodiment 1, using alkaline etching. Compared with the acid etching method of Embodiment 2, steps 1 to 4 are the same, except that after step 5:

[0080] 5) If Fig.13 As shown, the photosensitive layer 6 is photolithographically processed into a hollowed-out pattern corresponding to the top electrode 11 of each unit circuit, and the hollowed-out portion 62 of the hollowed-out pattern of the photosensitive layer corresponds to the shape of the top electrode 11 portion.

[0081] 6) If Fig.14 As shown, an alkali-resistant solderable metal layer 112 is electroplated on the top surface of the copper foil 1 in the hollowed-out portion of the photosensitive layer. The alkali-resistant solderable metal layer 112 can be a tin-plated layer, a silver-plated layer or a gold-plated layer.

[0082] 7) If Fig.15 As shown, the photosensitive layer is removed, and then, as Fig.16 As shown, the copper foil 1 is etched with alkaline etching to etch away the exposed copper foil 1 which is not coated with the alkaline corrosion-resistant solderable metal layer 112 on the top surface, thereby forming a top electrode 11.

[0083] 8) If Fig.17 As shown, a solder resist ink layer 7 is printed above the solder resist ink layer 3 and the main part of the top electrode 11. A window 71 is opened in the solder resist ink layer 7, and the pad part 111 of the top electrode 11 is exposed in the window 71 of the solder resist ink layer 7, thereby obtaining another form of the lead frame of Embodiment 1 of the present invention.

[0084] The packaging structure of the flip-chip LED chip in Example 4 of the present invention is as follows Fig.12 As shown, it includes an LED chip 8A, a packaging glue layer 9, two electrodes, a solder resist ink layer 3 and a solder resist ink layer 7. The electrodes include a top electrode 11 and a bottom electrode 12, and the top electrode 11 is arranged on the top surface of the solder resist ink layer 3. The solder resist ink layer 3 includes a bottom electrode hole 31 corresponding to the electrode, and the bottom electrode hole 31 is located directly below the top electrode 11. The bottom electrode 12 is arranged in the bottom electrode hole 31, and the top of the bottom electrode 12 is fixed on the bottom surface of the top electrode 11. The solder resist ink layer 7 covers the solder resist ink layer 3 and the top electrode 11. The solder resist ink layer 7 has a window, and the pad portion 111 of the top electrode 11 is arranged in the window of the second solder resist ink. The two electrodes of the flip-chip LED chip 8A are respectively welded to the pad portions 111 of the two top electrodes 11. The packaging glue layer 9 covers the solder resist ink layer 7, the pad portion 111 of the top electrode 11 and the flip-chip LED chip 8A.

[0085] The structure of the lead frame for chip packaging in Embodiment 5 of the present invention is as follows: Fig.24As shown, the difference from Example 1 is that the unit circuit includes a base island, and the base island includes an upper base island 13 and a lower base island 14. The upper base island 13 is arranged on the top surface of the solder resist ink layer 3, and the height of the upper base island 13 is the same as the height of the top electrode 11. Corresponding to each unit circuit, the solder resist ink layer 3 has a base island hole 32, and the lower base island 14 is arranged in the base island hole 32. The top of the lower base island 14 is fixed on the bottom surface of the upper base island 13. In addition to being peelably attached to the bottom surfaces of the solder resist ink layer 3 and the bottom electrode 12, the carrier sheet 2 can also be peelably attached to the bottom surface of the lower base island 14.

[0086] The lateral dimension of the upper base island 13 is greater than that of the lower base island 14, and the upper base island 13 can fully cover the base island hole 32. Similarly, this structural feature is mainly to prevent the alkali solution from corroding the lower base island 14 during alkaline etching to protect the lower base island 14. When the lower base island 14 is made of an alkali-resistant metal, it is not a necessary structural feature for the upper base island 13 to fully cover the base island hole 32.

[0087] The upper base island 13 includes a copper foil layer arranged on the top surface of the solder resist ink layer 3 and a solderable metal layer 132 electroplated on the top surface of the copper foil layer. The lower base island 14 includes a base metal layer 141 filled in the base island hole 32 of the solder resist ink layer 3 and plated on the bottom surface of the upper base island 13, and a solderable metal layer 142 plated on the bottom surface of the base metal layer 141. When an alkaline etching process is used, the base metal layer 141 adopts an alkali-resistant metal. The alkali-resistant metal layer 141 can be a nickel-plated layer, a tin-plated layer, a silver-plated layer, or a composite coating of at least two of nickel, tin and silver, and the solderable metal layer 142 can be a copper-plated layer, a nickel-plated layer, a tin-plated layer, a silver-plated layer, a gold-plated layer, or a composite coating of at least two of copper-plated layer, nickel-plated layer, tin-plated layer, silver-plated layer and gold-plated layer.

[0088] The solder resist ink layer 7 covers the solder resist ink layer 3, the top electrode 11 and the upper base island 13. The solder resist ink layer 7 has a plurality of windows 71, and the pad portions of the top electrode 11 and the upper base island 13 are arranged in the windows 71 of the solder resist ink layer 7, respectively.

[0089] Embodiment 6 of the present invention is a method for preparing the lead frame of Embodiment 5, which has many similarities with the method for preparing the lead frame of Embodiment 2, such as using acid etching, etc., and the main differences are as follows:

[0090] 1) If Fig.18 and Fig.19 As shown, in step 2 of Example 2, in addition to photoetching a bottom electrode hole 31 on the solder resist ink layer 3, a metal layer is plated on the bottom surface of the copper foil 1 in the bottom electrode hole 31 to form a bottom electrode 12 filled in the bottom electrode hole 31, and at the same time, a base island hole 32 corresponding to each unit circuit is photoetched on the solder resist ink layer 3, and a metal layer is plated on the bottom surface of the copper foil 1 in the base island hole 32 to form a lower base island 14 filled in the base island hole 32.

[0091] 2) If Fig. 20 As shown, in step 3 of embodiment 2, the carrier sheet 2 is simultaneously releasably adhered to the bottom surface of the lower base island 14 .

[0092] 3) If Fig.21 As shown, in step 5 of Example 2, the photosensitive layer 6 is photolithographically produced into a hollowed-out pattern corresponding to the top electrode 11 and the upper base island 13, and the remaining solid part 61 of the hollowed-out pattern of the photosensitive layer corresponds to the shapes of the top electrode 11 and the upper base island 13, respectively.

[0093] 4) If Fig. 22 As shown, in step 6 of embodiment 2, the copper foil 1 is acid-etched to etch away the copper foil 1 exposed by the hollow pattern, thereby forming not only the main part of the top electrode 11 but also the main part of the upper base island 13.

[0094] 5) If Fig.23 As shown, the photosensitive layer 6 is removed, and in step 7 of embodiment 2, solderable metal layers 112 and 132 are plated simultaneously on the pad portion of the top electrode 11 and the pad portion of the upper base island 13.

[0095] 6) If Fig.24 As shown, in step 7 of Example 2, a solder resist ink layer 7 is printed above the solder resist ink layer 3, the main part of the top electrode 11 and the main part of the upper base island 13. A plurality of windows 71 are opened in the solder resist ink layer 7, and the pad part of the top electrode 11 and the pad part of the upper base island 13 are respectively exposed in the windows 71 of the solder resist ink layer 7, thereby obtaining the lead frame of Example 5 of the present invention.

[0096] Embodiment 7 of the present invention is another method for preparing the lead frame of embodiment 5, using alkaline etching. Compared with the acid etching method of embodiment 6, steps 1 and 2 are the same, but the metal layer plated on the lower base island 14 is an alkaline corrosion-resistant metal layer. The main difference is after step 3:

[0097] 1) Different from step 3 of Example 6, Fig.25 As shown, the photosensitive layer 6 is made into a hollowed-out pattern corresponding to the top electrode 11 by photolithography, and the hollowed-out portion 62 of the hollowed-out pattern of the photosensitive layer corresponds to the shape of the top electrode 11 and the upper base island 13 .

[0098] 2) If Fig.26 As shown, the top surface of the copper foil 1 is electroplated with alkali-resistant solderable metal layers 112 and 132 in the hollow portion 62 of the photosensitive layer. The alkali-resistant solderable metal layers 112 and 132 can be tin-plated layers, silver-plated layers or gold-plated layers.

[0099] 3) If Fig. 27As shown, the photosensitive layer 6 is removed, and the copper foil 1 is etched with alkaline etching to etch away the exposed copper foil 1 which is not coated with the alkali-resistant solderable metal layers 112 and 132 on the top surface, thereby forming a top electrode 11 and an upper base island 13.

[0100] 4) If Fig.28 As shown, a solder resist ink layer 7 is printed on the solder resist ink layer 3, the main body of the top electrode 11 and the main body of the upper base island 13. A plurality of windows 71 are opened in the solder resist ink layer 7, and the pad portion of the top electrode 11 and the pad portion of the upper base island 13 are respectively exposed in the windows 71 of the second solder resist ink, thereby obtaining another form of the lead frame of embodiment 5 of the present invention.

[0101] The packaging structure of the chip in Embodiment 8 of the present invention is as follows Fig.29 As shown, it includes a positive chip 8B, a packaging glue layer 9, a base island, multiple electrodes, a solder resist ink layer 3 and a solder resist ink layer 7. Multiple electrodes are arranged around the base island. The base island includes an upper base island 13 and a lower base island 14, and the electrodes include a top electrode 11 and a bottom electrode 12. The upper base island 13 and the top electrode 11 are arranged on the top surface of the solder resist ink layer 3. The solder resist ink layer 3 includes a base island hole 32 and a bottom electrode hole 31 corresponding to the electrode. The base island hole 32 is located directly below the upper base island 13, and the lower base island 14 is arranged in the base island hole 32; the top of the lower base island 14 is fixed on the bottom surface of the upper base island 13. The bottom electrode hole 31 is located directly below the top electrode 11. The bottom electrode 12 is arranged in the bottom electrode hole 31, and the top of the bottom electrode 12 is fixed on the bottom surface of the top electrode 11. The solder resist ink layer 7 covers the solder resist ink layer 3, the upper base island 13 and the top electrode 11. The solder resist ink layer 7 has a plurality of windows, and the pads of the upper base island 13 and the pads of the top electrode 11 are respectively arranged in the windows of the solder resist ink layer 7. The bottom surface of the top chip 8B is welded to the pads of the upper base island 13, and the plurality of electrodes of the top chip 8B are electrically connected to the pads of the corresponding top electrode 11 through gold wires 8C. The encapsulation glue layer 9 covers the solder resist ink layer 7, the pads of the top electrode 11 and the flip chip 8B.

[0102] The preparation method of the lead frame of the above embodiment of the present invention uses a solder resist ink layer instead of the electrophoretic resin substrate. The thickness of the printed solder resist ink layer is easy to control, and there is no need to etch the copper foil to fill the electrophoretic resin substrate. The solder resist ink layer adopts a photosensitive ink layer, and the bottom electrode hole and the base island hole are photoetched on the photosensitive ink layer without the need to cover the photosensitive film separately. Moreover, there is no need to maintain the plating tank of the electrophoretic process, and the overall process is simple and the cost is low.

Claims

1. A lead frame for chip packaging, comprising a carrier sheet and a plurality of unit circuits arranged in a matrix, wherein the unit circuits comprise a plurality of electrodes, wherein the electrodes comprise a top electrode and a bottom electrode; characterized in that: It includes a first solder resist ink layer, and the top electrode is arranged on the top surface of the first solder resist ink layer; corresponding to each unit circuit, the first solder resist ink layer includes a bottom electrode hole corresponding to the electrode, the bottom electrode is arranged in the bottom electrode hole, and the top of the bottom electrode is fixed on the bottom surface of the top electrode; the carrier sheet is peelably attached to the bottom surface of the first solder resist ink layer and the bottom electrode.

2. The lead frame according to claim 1, characterized in that: The unit circuit includes a base island, and the base island includes an upper base island and a lower base island. The upper base island is arranged on the top surface of the first solder resist ink layer; corresponding to each unit circuit, the first solder resist ink layer includes a base island hole, and the lower base island is arranged in the base island hole; the top of the lower base island is fixed on the bottom surface of the upper base island; and the carrier sheet is peelably adhered to the bottom surface of the lower base island.

3. The lead frame according to claim 1, wherein: The lateral size of the top electrode is larger than that of the bottom electrode, and the top electrode fully covers the bottom electrode hole; the lateral size of the upper base island is larger than that of the lower base island, and the upper base island fully covers the base island hole; the height of the upper base island is the same as that of the top electrode.

4. The lead frame according to claim 1, wherein: The top electrode includes a copper foil layer arranged on the top surface of the first solder resist ink layer and a solderable metal layer electroplated on the top surface of the copper foil layer; the bottom electrode includes an alkali corrosion-resistant metal layer filled in the bottom electrode hole of the first solder resist ink layer and electroplated on the bottom surface of the top electrode and a solderable metal layer electroplated on the bottom surface of the alkali corrosion-resistant metal layer.

5. The lead frame according to claim 2, characterized in that: The upper base island includes a copper foil layer arranged on the top surface of the first solder resist ink layer and a solderable metal layer electroplated on the top surface of the copper foil layer; the lower base island includes an alkali-resistant metal layer filled in the base island hole of the first solder resist ink layer and plated on the bottom surface of the upper base island.

6. The lead frame according to claim 4 or 5, characterized in that: The alkali corrosion resistant metal layer is a nickel-plated layer, a tin-plated layer, a silver-plated layer or a composite layer of at least two of nickel, tin and silver; the solderable metal layer is a copper-plated layer, a nickel-plated layer, a tin-plated layer, a silver-plated layer, a gold-plated layer or a composite layer of at least two of copper-plated layer, nickel-plated layer, tin-plated layer, silver-plated layer and gold-plated layer.

7. The lead frame according to claim 1, wherein: It comprises a second solder resist ink layer, which covers the first solder resist ink layer and the top electrode; the second solder resist ink layer comprises a window, and the pad of the top electrode is arranged in the window of the second solder resist ink layer.

8. A method for preparing a lead frame according to claim 1, characterized in that: The following steps are involved: 801) A carrier film is attached to the top surface of the copper foil, and a first solder resist ink layer is printed on the bottom surface of the copper foil; 802) photoetching a bottom electrode hole on the first solder resist ink layer, and plating a metal layer on the bottom surface of the copper foil in the bottom electrode hole to form a bottom electrode filled in the bottom electrode hole; 803) attaching the carrier sheet to the bottom surface of the first solder resist ink layer and the bottom electrode in a releasable manner; 804) peeling off the carrier film on the top surface of the copper foil, and covering the top surface of the copper foil with a photosensitive layer; 805) The photosensitive layer is photolithographically formed into a hollowed-out pattern corresponding to the top electrode, and the copper foil is etched to form a top electrode above the first solder resist ink layer.

9. The preparation method according to claim 8, characterized in that: The following steps are involved: 901) The unit circuit includes a base island, and the base island includes an upper base island and a lower base island; in step 802, a base island hole corresponding to each unit circuit is photoetched on the first solder resist ink layer, and a metal layer is plated on the bottom surface of the copper foil in the base island hole to form a lower base island filled in the base island hole; 902) In step 803, the carrier sheet is simultaneously releasably adhered to the bottom surface of the lower base island; 903) In step 805, the pattern produced by photolithography of the photosensitive layer includes a pattern corresponding to the upper base island, and when etching the copper foil, the upper base island is simultaneously formed above the first solder resist ink layer.

10. The preparation method according to claim 8, characterized in that: The following steps are involved: 1001) In step 805, the solid part of the hollowed-out pattern of the photosensitive layer corresponds to the shape of the top electrode; 1002) Acid etching is performed on the copper foil to etch away the copper foil exposed by the hollow pattern; 1003) The photosensitive layer is removed and a solderable metal layer is plated on the copper foil remaining after etching to form a top electrode.

11. The preparation method according to claim 8, characterized in that: The following steps are involved: 1101) In step 805, the hollowed-out portion of the hollowed-out pattern of the photosensitive layer corresponds to the shape of the top electrode; 1102) electroplating an alkali-resistant and solderable metal layer on the top surface of the copper foil in the hollowed-out portion of the photosensitive layer; 1103) removing the photosensitive layer, performing alkaline etching on the copper foil, etching away the solderable metal layer that is not coated with alkaline corrosion resistance and the exposed copper foil to form a top electrode.

12. The preparation method according to claim 8, characterized in that: After step 805 is completed, a second solder resist ink layer is printed above the first solder resist ink layer and the top electrode; the second solder resist ink layer includes a window, and the pad of the top electrode is arranged in the window of the second solder resist ink layer.

13. A chip packaging structure, comprising a chip, a packaging adhesive layer and a plurality of electrodes, characterized in that: It includes a first solder resist ink layer, the electrode includes a top electrode and a bottom electrode, the top electrode is arranged on the top surface of the first solder resist ink layer; the first solder resist ink layer includes a bottom electrode hole corresponding to the electrode, and the bottom electrode hole is located directly below the top electrode; The bottom electrode is arranged in the bottom electrode hole, and the top of the bottom electrode is fixed on the bottom surface of the top electrode; the packaging glue layer covers the first solder resist ink layer and the top electrode, the chip is packaged in the packaging glue layer, and the plurality of electrodes of the chip are electrically connected to the plurality of top electrodes respectively.

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