Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same include: providing a substrate; the substrate having an initial semiconductor structure; forming a dielectric layer on the surface of the substrate, the dielectric layer having a first opening exposing the surface of the initial semiconductor structure; etching the initial semiconductor structure exposed at the bottom of the first opening to form a second opening in the initial semiconductor structure; forming a contact layer in the second opening, the contact layer having a third opening; and forming a conductive structure in the first opening and the third opening. By forming the third opening in the contact surface, it is possible to ensure that the contact interface formed between the conductive structure and the contact layer is a concave curved surface structure, and the contact area of ​​the concave curved surface structure is effectively increased compared with the horizontal surface structure, thereby reducing the contact resistance.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a forming method thereof. Background Art

[0002] With the continuous advancement of semiconductor technology, the characteristic size of semiconductor devices is gradually getting smaller. The reduction of critical size means that more transistors can be arranged on the chip, and at the same time, higher requirements are placed on the semiconductor process. As the size of semiconductor devices decreases, the contact resistance of MOS transistors has an increasingly greater impact on the performance of MOS transistors and the entire semiconductor chip. In order to improve the performance of semiconductor chips, it is necessary to reduce the contact resistance of MOS transistors.

[0003] Currently, the contact resistance is reduced and the performance of the semiconductor structure is improved mainly by increasing the contact surface area between the metal contact layer and the conductive structure or the source-drain doped region.

[0004] However, the semiconductor structure formed by the prior art has the problem of large contact resistance between the metal silicide and the conductive structure. Summary of the invention

[0005] The problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, which can effectively increase the contact surface between the conductive structure and the contact layer by forming a third opening in the contact surface, thereby reducing the contact resistance.

[0006] To solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, wherein the substrate has an initial semiconductor structure; forming a dielectric layer on the surface of the substrate, wherein the dielectric layer has a first opening exposing the surface of the initial semiconductor structure; etching the initial semiconductor structure exposed at the bottom of the first opening to form a second opening in the initial semiconductor structure; forming a contact layer in the second opening, wherein the contact layer has a third opening; and forming a conductive structure in the first opening and the third opening.

[0007] Optionally, the substrate is a single-layer structure or a multi-layer structure.

[0008] Optionally, when the substrate is a single-layer structure, the substrate includes an initial substrate and an epitaxial layer located in the initial substrate, and the initial semiconductor structure is the epitaxial layer.

[0009] Optionally, when the substrate is a multi-layer structure, the substrate includes a base and a device layer located on the base, the device layer includes a device structure and a device dielectric layer surrounding the device structure, and the initial semiconductor structure is the device structure.

[0010] Optionally, the initial semiconductor structure is doped with first type ions.

[0011] Optionally, the process of doping the first type of ions in the initial semiconductor structure is an in-situ doping process.

[0012] Optionally, the first type of ions are P-type ions or N-type ions; the P-type ions include boron ions or indium ions; the N-type ions include phosphorus ions or arsenic ions.

[0013] Optionally, the method for forming the contact layer and the third opening includes: forming an initial contact layer in the second opening; performing a sputtering process on the initial contact layer to form an initial third opening in the initial contact layer; and performing an annealing process on the initial contact layer to form the contact layer and the third opening located in the contact layer.

[0014] Optionally, the initial contact layer is formed by a physical vapor deposition process.

[0015] Optionally, the parameters of the annealing treatment include: annealing temperature of 750° C. to 850° C., and annealing time of 170s to 190s.

[0016] Optionally, the material of the initial contact layer includes single metal or alloy of titanium, nickel or platinum.

[0017] Optionally, the ions used in the sputtering process include titanium ions or argon ions.

[0018] Optionally, the parameters of the sputtering process include: sputtering time 15s to 25s, sputtering voltage 1800W to 2200W.

[0019] Optionally, the conductive structure includes a barrier layer and a conductive plug located on a surface of the barrier layer.

[0020] Optionally, the conductive structure is formed before forming the contact layer; or, the conductive structure is formed after forming the contact layer.

[0021] Optionally, the material of the barrier layer includes titanium nitride.

[0022] Optionally, the barrier layer formation process includes an atomic layer deposition process.

[0023] Optionally, the material of the conductive plug includes tungsten, cobalt, copper or aluminum.

[0024] Optionally, the bottom surface of the initial third opening is a concave curved structure.

[0025] Correspondingly, the present invention also provides a semiconductor structure formed by any of the above methods, comprising: a substrate, wherein the substrate has an initial semiconductor structure; a dielectric layer located on the substrate, wherein the dielectric layer has a first opening exposing the surface of the initial semiconductor structure; a second opening located in the initial semiconductor structure, wherein the first opening exposes the second opening; a contact layer located in the second opening, wherein the contact layer has a third opening; and a conductive structure located in the first opening and the third opening.

[0026] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0027] In the technical solution of the present invention, a third opening is formed in the contact layer, and a conductive plug is formed in the third opening. Since the surface of the third opening is a concave curved surface structure, it can be ensured that the contact interface formed between the conductive structure formed in the third opening and the contact layer is also a concave curved surface structure. Compared with the horizontal surface structure, the contact area of ​​the concave curved surface structure is effectively increased. Since the contact area is increased in the direction of the electrical path of the conductive structure, it is equivalent to connecting a resistor in parallel, and the total resistance will be smaller than any one of the resistors. Based on this principle, the effect of reducing the contact resistance between the conductive structure and the contact layer is achieved.

[0028] Furthermore, in the technical solution of the present invention, the ions used in the sputtering process and the metal used in the deposition process to form the initial contact layer are both titanium. Since the materials used are the same, the process of replacing equipment is omitted, effectively improving production efficiency.

[0029] Furthermore, in the technical solution of the present invention, the barrier layer is formed by an atomic layer deposition process. Since the atomic layer deposition process is a method that can deposit a substance on the surface of a substrate layer by layer in the form of a single atomic film, the method has good conformality. Therefore, the barrier layer formed by the atomic layer deposition process can well maintain the concave surface structure of the third opening, thereby ensuring that the contact interface between the barrier layer and the conductive plug is also a concave surface structure. Under the same width, the surface area of ​​the concave surface structure is greater than the surface area of ​​the horizontal surface structure, so the contact area between the conductive plug and the barrier layer is effectively increased. Since the contact area is increased in the direction of the electrical path of the conductive structure, it is equivalent to connecting a resistor in parallel, and the total resistance will be smaller than any one of the resistors. Based on this principle, the contact resistance between the conductive structure and the contact layer is further reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figures 1 to 3 It is a structural schematic diagram of the process of semiconductor structure formation;

[0031] Figures 4 to 9It is a schematic structural diagram of each step of a method for forming a semiconductor structure in one embodiment of the present invention.

[0032] Fig.10 and Fig.11 It is a schematic structural diagram of each step of a method for forming a semiconductor structure in another embodiment of the present invention. DETAILED DESCRIPTION

[0033] As described in the background art, the semiconductor structure formed by the prior art has a problem of large contact resistance between the metal silicide and the conductive structure. Figures 1 to 3 To explain, Figures 1 to 3 It is a structural schematic diagram of the formation process of a semiconductor structure.

[0034] refer to Figure 1 , providing a substrate 100, wherein the substrate 100 has a first opening (not shown); forming an epitaxial layer 101 in the first opening; forming a dielectric layer 102 on the substrate 100, wherein the dielectric layer 102 has a second opening 103 exposing the surface of the epitaxial layer; etching the epitaxial layer 101 exposed at the bottom of the second opening 103, and forming a third opening 104 in the epitaxial layer 101.

[0035] Please refer to Figure 2 A contact layer 105 is formed on the sidewall surface and the bottom surface of the third opening 104 by using a semiconductor metallization process.

[0036] Please refer to Figure 3 A conductive structure 106 is formed on the surface of the contact layer 105 , and the conductive structure 106 is located in the second opening 103 .

[0037] In the above embodiment, since the process of forming the contact layer 105 adopts physical vapor deposition, the top surface of the contact layer 105 formed by this process is horizontal, so the contact interface between the conductive structure 106 and the contact layer 105 is also a horizontal plane structure. The area of ​​the horizontal plane structure is small, so the contact resistance between the conductive structure 106 and the contact layer 105 is large.

[0038] On this basis, the present invention provides a semiconductor structure and a method for forming the same. By forming a third opening in the contact surface, it can ensure that the contact interface formed between the conductive structure and the contact layer is a concave surface structure. Compared with the horizontal surface structure, the contact area of ​​the concave surface structure is effectively increased, thereby reducing the contact resistance.

[0039] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0040] Figures 4 to 9 It is a schematic structural diagram of each step of the method for forming a semiconductor structure in an embodiment of the present invention.

[0041] Please refer to Figure 4 , providing a substrate 201, wherein the substrate 201 has an initial semiconductor structure 202 therein.

[0042] In this embodiment, the substrate 201 is a single-layer structure. The substrate 201 includes an initial substrate and an epitaxial layer located in the initial substrate. The initial semiconductor structure 202 is the epitaxial layer.

[0043] The material of the initial substrate is silicon; in other embodiments, the material of the initial substrate may also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium; in other embodiments, the initial substrate may also be a silicon substrate on an insulator or a germanium substrate on an insulator.

[0044] In this embodiment, the method for forming the substrate 201 includes: forming a substrate opening in the initial substrate, and forming the initial semiconductor structure 202 in the substrate opening.

[0045] In this embodiment, the method for forming the substrate opening includes: forming a first mask structure on the initial substrate; forming a first patterned layer on the first mask structure, the first patterned layer having an opening exposing a portion of the first mask structure; etching a portion of the first mask structure and the initial substrate using the first patterned layer as a mask to form the substrate opening; after the substrate opening is formed, removing the first patterned layer and the first mask structure (not shown).

[0046] In this embodiment, the first mask structure includes a first mask layer located on the initial substrate, and a second mask layer located on the surface of the first mask layer; in other embodiments, the first mask structure may also be a single-layer structure.

[0047] In this embodiment, the material of the first mask layer is nitrogen-doped silicon carbide; the first mask layer formed by the nitrogen-doped silicon carbide has good bonding ability with the initial substrate, and when the initial substrate is subsequently etched using the etched first mask layer as a mask, the first mask layer is not prone to peeling or warping, so the first mask layer has a good ability to maintain the etching pattern, which is beneficial to making the substrate opening morphology formed in the initial substrate good, and effectively improving the accuracy of the pattern after etching.

[0048] In this embodiment, the material of the second mask layer is titanium nitride, and the second mask layer has good bonding ability with the first mask layer. The second mask layer can protect the surface of the first mask layer when the initial substrate is subsequently etched, so that the first mask layer will not be thinned. Moreover, the physical strength of the second mask layer is relatively large. When the initial substrate is subsequently etched, the patterns of the second mask layer and the first mask layer can remain stable, which is conducive to forming a substrate opening with a good morphology.

[0049] In other embodiments, the material of the second mask layer may also be silicon carbide, silicon carbonitride, silicon carbonitride oxide, silicon nitride oxide, boron nitride or boron carbonitride.

[0050] In this embodiment, the first mask layer and the second mask layer are formed by an atomic layer deposition process; in other embodiments, the first mask layer and the second mask layer may also be formed by a chemical vapor deposition process, a physical vapor deposition process, or a spin coating process.

[0051] In this embodiment, the material of the first patterned layer includes photoresist, and the formation process of the first patterned layer includes a photolithography patterning process; the process of removing the first patterned layer includes a wet stripping process or an ashing process, and the gas of the ashing process is an oxygen-containing gas, such as oxygen or ozone.

[0052] In this embodiment, the process used to remove the first mask structure is a wet etching process; in other embodiments, the process used to remove the first mask structure may also be a dry etching process.

[0053] In this embodiment, the initial semiconductor structure 202 is formed by an epitaxial deposition process.

[0054] The material of the initial semiconductor structure 202 is a semiconductor material doped with the first type of ions. In this embodiment, the semiconductor material includes silicon. In other embodiments, the semiconductor material may also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium.

[0055] In this embodiment, the process of doping the first type of ions in the initial semiconductor structure 202 is an in-situ doping process.

[0056] In this embodiment, the first type of ions are P-type ions, which are boron ions; in other embodiments, the P-type ions may be indium ions; in other embodiments, the first type of ions may also be N-type ions, which may be phosphorus ions or arsenic ions.

[0057] Please refer to Figure 5A dielectric layer 203 is formed on the surface of the substrate 201 , and a first opening 204 is provided in the dielectric layer 203 to expose the surface of the initial semiconductor structure 202 .

[0058] In this embodiment, the method for forming the dielectric layer 203 and the first opening 204 includes: forming an initial dielectric layer on the substrate 201; forming a second mask structure on the initial dielectric layer; forming a second patterned layer (not shown) on the second mask structure, the second patterned layer having an opening that exposes a portion of the initial dielectric layer; etching a portion of the second mask structure and the initial dielectric layer using the second patterned layer as a mask until the surface of the initial semiconductor structure 202 is exposed to form the dielectric layer 203 and the first opening 204; after forming the dielectric layer 203 and the first opening 204, removing the second patterned layer and the second mask structure.

[0059] The material of the initial dielectric layer includes silicon dioxide, low-k dielectric material (low-k dielectric material refers to dielectric material with a relative dielectric constant lower than 3.9) or ultra-low-k dielectric material (ultra-low-k dielectric material refers to dielectric material with a relative dielectric constant lower than 2.5).

[0060] When the material of the initial dielectric layer is a low-k dielectric material or an ultra-low-k dielectric material, the material of the initial dielectric layer is carbon silicon oxyhydride (SiCOH), fluorine-doped silicon dioxide (FSG), boron-doped silicon dioxide (BSG), phosphorus-doped silicon dioxide (PSG), boron-phosphorus-doped silicon dioxide (BPSG), hydrogenated silsesquioxane or methyl silsesquioxane.

[0061] In this embodiment, the material of the initial dielectric layer is an ultra-low-k dielectric material (dielectric constant is less than 2.5), and the ultra-low-k dielectric material is silicon carbon oxyhydride (SiCOH).

[0062] The process of forming the initial dielectric layer includes atomic layer deposition, chemical vapor deposition, physical vapor deposition or spin coating. In this embodiment, the process of forming the initial dielectric layer adopts chemical vapor deposition.

[0063] In this embodiment, the second mask structure adopts the first mask layer and the second mask layer mentioned above, which will not be described in detail here; in other embodiments, the second mask structure may also adopt a single-layer structure.

[0064] In this embodiment, the material of the second patterned layer includes photoresist, and the formation process of the second patterned layer includes a photolithography patterning process.

[0065] The process of removing the second patterned layer includes a wet stripping process or an ashing process, and the gas of the ashing process is an oxygen-containing gas, such as oxygen or ozone.

[0066] In this embodiment, the process used to remove the first mask structure is a wet etching process; in other embodiments, the process used to remove the first mask structure may also be a dry etching process.

[0067] Please refer to Figure 6 , the initial semiconductor structure 202 exposed at the bottom of the first opening 204 is etched to form a second opening 205 in the initial semiconductor structure 202 .

[0068] In this embodiment, the initial semiconductor structure 202 is etched by dry etching.

[0069] After forming the second opening 205, a contact layer is subsequently formed in the second opening 205, wherein the contact layer has a third opening. Figures 7 to 9 .

[0070] In this embodiment, please refer to Figure 7 The method for forming the contact layer and the third opening includes: forming an initial contact layer 206 in the second opening 205 ; performing a sputtering process on the initial contact layer 206 to form an initial third opening 207 in the initial contact layer 206 .

[0071] Please refer to Figure 8 , the initial contact layer 206 is annealed to form the contact layer 208 and the third opening 209 located in the contact layer 208 .

[0072] In this embodiment, the initial contact layer 206 is formed by a physical vapor deposition process. Since the initial contact layer 206 only needs to be formed in the second opening 205 and does not need to be formed on the side wall surface of the first opening 204, the physical vapor deposition process can meet the process requirements.

[0073] The material of the initial contact layer 206 includes a single metal or an alloy of titanium, nickel or platinum. In this embodiment, the material of the initial contact layer 206 is titanium.

[0074] The initial third opening 207 is formed by processing the initial contact layer using a sputtering process, and the ions used in the sputtering process include titanium ions or argon ions; in this embodiment, the ions used in the sputtering process are titanium ions. The advantage of using titanium ion sputtering is that titanium ion sputtering and titanium deposition use the same equipment, eliminating the process of changing equipment and effectively improving production efficiency.

[0075] The titanium ion sputtering time is 15s to 25s, and the titanium ion sputtering voltage is 1800W to 2200W. In this embodiment, the sputtering time is 20s, and the sputtering voltage is 2000W.

[0076] The parameters of the annealing process include: annealing temperature of 750° C. to 850° C., and annealing time of 170s to 190s. In this embodiment, the annealing temperature is 800° C., and the annealing time is 180s.

[0077] In this embodiment, the bottom surface of the initial third opening 207 is a concave curved structure.

[0078] Please refer to Fig. 9 , a conductive structure 210 is formed in the first opening 204 and the third opening 209 .

[0079] In this embodiment, the conductive structure 210 includes a barrier layer 211 and a conductive plug 212 located on a surface of the barrier layer 211 . The barrier layer 211 is located on a surface of the third opening 209 and a sidewall surface of the first opening 204 .

[0080] Under the condition of the same width, the concave surface area of ​​the third opening 209 is larger than the surface area of ​​the horizontal surface, thereby effectively increasing the contact surface between the contact layer 208 and the barrier layer 211. Since the contact area is increased in the electrical path direction of the conductive structure 210, it is equivalent to connecting a resistor in parallel, and the total resistance will be smaller than any one of the resistors. Based on this principle, the effect of reducing the contact resistance between the conductive structure 210 and the contact layer 208 is achieved.

[0081] In this embodiment, the conductive structure 210 is formed after the contact layer 206 is formed; in other embodiments, the conductive structure may also be formed before the contact layer is formed.

[0082] In this embodiment, the material of the barrier layer 211 is titanium nitride. The barrier layer 211 serves to adhere the conductive plug 212 on the one hand, and prevents the metal of the conductive plug 212 from penetrating outwards, which may cause metal contamination on the other hand.

[0083] In this embodiment, the barrier layer 211 is formed by an atomic layer deposition process. Since the atomic layer deposition process is a method of coating a material on the surface of a substrate layer by layer in the form of a single atomic film, the method has good conformality. Therefore, the barrier layer 211 formed by the atomic layer deposition process can well maintain the concave surface structure of the third opening 209, and thus can ensure that the contact interface between the barrier layer 211 and the conductive plug 212 is also a concave surface structure. Under the condition of the same width, the surface area of ​​the concave surface structure is greater than the surface area of ​​the horizontal surface structure, so the contact area between the conductive plug 212 and the barrier layer 211 is effectively increased. Since the contact area is increased in the direction of the electrical path of the conductive structure 210, it is equivalent to connecting a resistor in parallel, and the total resistance will be smaller than any one of the resistors. Based on this principle, the contact resistance between the conductive structure 210 and the contact layer 206 is further reduced.

[0084] In this embodiment, the conductive plug 212 is made of cobalt; in other embodiments, the conductive plug may be made of tungsten, copper or aluminum.

[0085] Please continue to refer to Fig. 9 Accordingly, the present invention also provides a semiconductor structure formed by the above method, comprising: a substrate 201, wherein the substrate 201 has an initial semiconductor structure 202; a dielectric layer 203 located on the substrate 201, wherein the dielectric layer 203 has a first opening exposing the surface of the initial semiconductor structure 202; a second opening located in the initial semiconductor structure 202, wherein the first opening exposes the second opening; a contact layer 208 located in the second opening, wherein the contact layer 208 has a third opening; and a conductive structure 210 located in the first opening and the third opening.

[0086] Fig.10 and Fig.11 A schematic structural diagram of each step of a method for forming a semiconductor structure in another embodiment of the present invention.

[0087] Please refer to Fig.10 , providing a substrate 301, wherein the substrate 301 has an initial semiconductor structure 302 therein.

[0088] In this embodiment, the substrate 301 is a multi-layer structure, which includes a base 303 and a device layer 304 located on the base 303. The device layer 304 includes a device structure and a device dielectric layer surrounding the device structure. The initial semiconductor structure 302 is the device structure.

[0089] The material of the initial semiconductor structure 302 includes semiconductor material; the semiconductor material includes silicon, germanium, silicon germanium or silicon carbide.

[0090] In this embodiment, the device structure is a gate structure. In other embodiments, the device structure can also be a resistor structure, a capacitor structure, an inductor structure or a storage gate structure.

[0091] Please refer to Fig.11 A dielectric layer 305 is formed on the surface of the substrate 301 , and a first opening is provided in the dielectric layer 305 to expose the surface of the initial semiconductor structure 302 .

[0092] In this embodiment, the dielectric layer 305 is formed on the surface of the device dielectric and the initial semiconductor structure 302 .

[0093] Please continue to refer to Fig.11 , etching the initial semiconductor structure 302 exposed at the bottom of the first opening, forming a second opening in the initial semiconductor structure 302; forming a contact layer 306 in the second opening, and the contact layer 306 has a third opening; forming a conductive structure 307 in the first opening and the third opening. The specific formation process can be referred to Figures 6 to 9 And related instructions have been described, which will not be repeated here.

[0094] Accordingly, the embodiment of the present invention also provides a Fig.11 The semiconductor structure shown.

[0095] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: providing a substrate having an initial semiconductor structure therein; Forming a dielectric layer on the surface of the substrate, wherein the dielectric layer has a first opening exposing the surface of the initial semiconductor structure; Etching the initial semiconductor structure exposed at the bottom of the first opening to form a second opening in the initial semiconductor structure; forming a contact layer in the second opening, wherein the contact layer has a third opening; forming a conductive structure in the first opening and the third opening; in The method for forming the contact layer and the third opening includes: forming an initial contact layer in the second opening; performing a sputtering process on the initial contact layer to form an initial third opening in the initial contact layer; and performing an annealing process on the initial contact layer to form the contact layer and the third opening located in the contact layer.

2. The method for forming a semiconductor structure according to claim 1, wherein: The substrate is a single-layer structure or a multi-layer structure.

3. The method for forming a semiconductor structure according to claim 2, wherein: When the substrate is a single-layer structure, the substrate includes an initial substrate and an epitaxial layer located in the initial substrate, and the initial semiconductor structure is the epitaxial layer.

4. The method for forming a semiconductor structure according to claim 2, wherein: When the substrate is a multi-layer structure, the substrate includes a base and a device layer located on the base, the device layer includes a device structure and a device dielectric layer surrounding the device structure, and the initial semiconductor structure is the device structure.

5. The method for forming a semiconductor structure according to claim 3, wherein: The initial semiconductor structure is doped with first type ions.

6. The method for forming a semiconductor structure according to claim 5, wherein: The process of doping the first type of ions in the initial semiconductor structure is an in-situ doping process.

7. The method for forming a semiconductor structure according to claim 5, wherein: The first type of ions are P-type ions or N-type ions; the P-type ions include boron ions or indium ions; the N-type ions include phosphorus ions or arsenic ions.

8. The method for forming a semiconductor structure according to claim 1, wherein: The initial contact layer is formed by a physical vapor deposition process.

9. The method for forming a semiconductor structure according to claim 1, wherein: The parameters of the annealing treatment include: annealing temperature of 750° C. to 850° C., and annealing time of 170s to 190s.

10. The method for forming a semiconductor structure according to claim 1, wherein: The material of the initial contact layer includes single metal or alloy of titanium, nickel or platinum.

11. The method for forming a semiconductor structure according to claim 1, wherein: The ions used in the sputtering process include titanium ions or argon ions.

12. The method for forming a semiconductor structure according to claim 1, wherein: The parameters of the sputtering process include: sputtering time 15s-25s, sputtering voltage 1800W-2200W.

13. The method for forming a semiconductor structure according to claim 1, wherein: The conductive structure includes a barrier layer and a conductive plug located on the surface of the barrier layer.

14. The method for forming a semiconductor structure according to claim 13, wherein: The conductive structure is formed before forming the contact layer; or, the conductive structure is formed after forming the contact layer.

15. The method for forming a semiconductor structure according to claim 13, wherein: The material of the barrier layer includes titanium nitride.

16. The method for forming a semiconductor structure according to claim 13, wherein: The barrier layer formation process includes an atomic layer deposition process.

17. The method for forming a semiconductor structure according to claim 13, wherein: The conductive plug is made of tungsten, cobalt, copper or aluminum.

18. The method for forming a semiconductor structure according to claim 1, wherein: The bottom surface of the initial third opening is a concave curved structure.

19. A semiconductor structure formed by the method according to any one of claims 1 to 18, characterized in that: include: a substrate having an initial semiconductor structure therein; A dielectric layer located on the substrate, wherein the dielectric layer has a first opening exposing a surface of the initial semiconductor structure; a second opening in the initial semiconductor structure, the first opening exposing the second opening; a contact layer located in the second opening, wherein the contact layer has a third opening; A conductive structure is located in the first opening and the third opening.

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