Analog-to-digital converter

Abstract

The present invention discloses an analog-to-digital converter, which is used to receive an analog input signal and generate a digital code. The analog-to-digital converter includes a delta-sigma modulator, a frequency reduction filter and a detection circuit. The delta-sigma modulator includes a loop filter, a quantizer and a digital-to-analog converter. The loop filter is used to receive the analog input signal. The quantizer is coupled to the loop filter and is used to quantize an output of the loop filter to generate a digital output signal. The digital-to-analog converter is coupled to the quantizer and the loop filter. The frequency reduction filter is coupled to the delta-sigma modulator and is used to convert the digital output signal into the digital code. The detection circuit is coupled to the delta-sigma modulator and is used to detect a node voltage of the delta-sigma modulator and generate a control signal. The control signal is used to control the loop filter, the quantizer, a feedback path of the delta-sigma modulator and / or a feedforward path of the delta-sigma modulator.

Description

Technical Field

[0001] The present invention relates to an analog-to-digital converter (ADC), and in particular to an ADC based on a delta-sigma modulator. Background Art

[0002] Sigma-delta modulator (SDM) is a common method to realize ADC. However, the signal applied to sigma-delta modulator usually has the following characteristics: outside the signal bandwidth of the in-band signal, there are other out-of-band signals with a larger amplitude than the in-band signal. This out-of-band signal that interferes with the sigma-delta modulator can be called an image or blocker. Therefore, detecting and suppressing these unnecessary out-of-band signals has become an important issue in this field. Summary of the invention

[0003] In view of the shortcomings of the prior art, an object of the present invention is to provide an ADC to improve the stability of the ADC.

[0004] The present invention discloses an analog-to-digital converter, which is used to receive an analog input signal and generate a digital code. The analog-to-digital converter includes a delta-sigma modulator, a frequency reduction filter and a detection circuit. The delta-sigma modulator includes a loop filter, a quantizer and a digital-to-analog converter. The loop filter is used to receive the analog input signal. The quantizer is coupled to the loop filter and is used to quantize an output of the loop filter to generate a digital output signal. The digital-to-analog converter is coupled to the quantizer and the loop filter. The frequency reduction filter is coupled to the delta-sigma modulator and is used to convert the digital output signal into the digital code. The detection circuit is coupled to the delta-sigma modulator and is used to detect a node voltage of the delta-sigma modulator and generate a control signal. The control signal is used to control the loop filter, the quantizer, a feedback path of the delta-sigma modulator and / or a feedforward path of the delta-sigma modulator.

[0005] The present invention also discloses an analog-to-digital converter for receiving an analog input signal and generating a digital code. The analog-to-digital converter includes a delta-sigma modulator, a frequency reduction filter, a detection circuit, and a control circuit. The delta-sigma modulator includes a loop filter, a quantizer, and a digital-to-analog converter. The loop filter is used to receive the analog input signal. The quantizer is coupled to the loop filter and is used to quantize an output of the loop filter to generate a digital output signal. The digital-to-analog converter is coupled to the quantizer and the loop filter. The frequency reduction filter is coupled to the delta-sigma modulator and is used to convert the digital output signal into the digital code. The detection circuit is coupled to the delta-sigma modulator and is used to detect a node voltage of the delta-sigma modulator and generate a detection result. The control circuit is coupled to the detection circuit and is used to generate a control signal according to the detection result. The control signal is used to control the loop filter, the quantizer, a feedback path of the delta-sigma modulator, and / or a feedforward path of the delta-sigma modulator.

[0006] The ADC of the present invention uses a detection circuit to detect the node voltage of the delta-sigma modulator, and adaptively adjusts the ADC according to the detection result to improve the stability of the ADC and reduce power consumption. Compared with the traditional technology, the ADC of the present invention can detect and suppress these unnecessary out-of-band signals, making the operation of the ADC more stable.

[0007] The features, implementation and technical effects of the present invention are described in detail below with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 A circuit diagram of an ADC according to an embodiment of the present invention;

[0009] Figure 2 is a circuit diagram of a resonator according to an embodiment of the present invention;

[0010] Figure 3 is a circuit diagram of a clamping circuit according to an embodiment of the present invention;

[0011] Figure 4 A circuit diagram of an ADC according to another embodiment of the present invention;

[0012] Figure 5 is a functional block diagram of a detection circuit according to an embodiment of the present invention; and

[0013] Figure 6 FIG. 4 is a functional block diagram of a detection circuit according to another embodiment of the present invention.

[0014] Explanation of symbols

[0015] 10.15 Analog-to-digital converter

[0016] 100 Low pass filter

[0017] 200 Delta-Sigma Modulator

[0018] 210 loop filter

[0019] 212a, 212b, 500 resonator

[0020] 214, 240 switch

[0021] 220 Quantizer

[0022] 230 Digital to Analog Converter

[0023] 245 Feedback Path

[0024] 250 Impedance Circuit

[0025] 255 Feedforward path

[0026] 300a, 300b, 300c, 300d detection circuit

[0027] 400a, 400b, 400c, 400d Clamping Circuits

[0028] 900 Down-Band Filter

[0029] Cd1~Cd4、Cdx control signal

[0030] S1~S10, S control signal

[0031] Vin Analog input signal

[0032] Dout digital output signal

[0033] D Digital Code

[0034] 510, 520 Integrator

[0035] 512, 522 operational amplifiers

[0036] 530 Impedance

[0037] 532 variable resistor

[0038] 412, 414, 416, 418 transistors

[0039] N1 and N2 nodes

[0040] 610a, 610b Integrator or operational amplifier

[0041] 700 Control Circuit

[0042] 800 Memory

[0043] DR1~DR4、DRx、DR test results

[0044] 310 Low Resolution Analog-to-Digital Converter

[0045] 320 Area Control Circuit

[0046] 330 Comparator

[0047] Vn node voltage DETAILED DESCRIPTION

[0048] The technical terms used in the following descriptions refer to the customary terms in the technical field. If some terms are explained or defined in this specification, the interpretation of these terms shall be based on the explanation or definition in this specification.

[0049] The disclosure of the present invention includes an ADC based on a delta-sigma modulator. Since some components of the ADC of the present invention may be known components individually, the details of the known components will be omitted in the following description without affecting the full disclosure and feasibility of the device invention.

[0050] Figure 1 1 is a circuit diagram of an ADC according to an embodiment of the present invention. ADC 10 is an ADC based on a delta-sigma modulator, comprising a low-pass filter (LPF) 100, an SDM 200, a decimation filter 900, and a plurality of detection circuits 300 ( Figure 1 The example includes a detection circuit 300a, a detection circuit 300b, a detection circuit 300c and a detection circuit 300d) and a plurality of clamping circuits 400 ( Figure 1 The example includes clamp circuit 400a, clamp circuit 400b, clamp circuit 400c and clamp circuit 400d). The low-pass filter 100 low-pass filters the analog input signal Vin, and the SDM 200 converts the low-pass filtered analog input signal Vin into a digital output signal Dout, and the digital output signal Dout is processed by the down-conversion filter 900 to generate a digital code D. The digital code D is the output of the ADC 10. The operation of the down-conversion filter 900 is well known to those skilled in the art, so it is not described in detail.

[0051] The SDM 200 includes a loop filter 210, a quantizer 220, a digital-to-analog converter (DAC) 230, a switch 240, and an impedance circuit 250. The loop filter 210 receives and filters the low-pass filtered analog input signal Vin, and includes a resonator 212a, a resonator 212b, and a switch 214. The quantizer 220 is coupled to the loop filter to quantize the output of the loop filter 210 to generate a digital output signal Dout. The switch 240 is coupled between the DAC 230 and the loop filter 210. The operating principle of the SDM 200 is well known to those skilled in the art, so it is not described in detail. Figure 1 The order of the loop filter 210 is only an example and is not intended to limit the present invention.

[0052] Resonator 212a is controlled by control signal S1; resonator 212b is controlled by control signal S2; switch 214 is controlled by control signal S3; quantizer 220 is controlled by control signal S4; switch 240 is controlled by control signal S5; impedance circuit 250 is controlled by control signal S6; and clamp circuits 400a to 400d are controlled by control signals S7 to S10, respectively.

[0053] The detection circuit 300 detects the voltages of several nodes of the SDM 200 and generates a control signal Cdx (at Figure 1 In the example of , x is an integer and 1≤x≤4). More specifically, the detection circuit 300a detects the voltage at the input end of the SDM 200 (i.e., the output end of the low-pass filter 100, the input end of the resonator 212a), and generates a control signal Cd1; the detection circuit 300b detects the voltage at the internal node of the resonator 212a, and generates a control signal Cd2; the detection circuit 300c detects the output voltage of the resonator 212a (i.e., the input voltage of the resonator 212b), and generates a control signal Cd3; the detection circuit 300d detects the output voltage of the resonator 212b (i.e., the input voltage of the quantizer 220), and generates a control signal Cd4. The control signal Cdx can be used to control: (1) the loop filter 210; (2) the quantizer 220; (3) the feedback path 245 of the SDM 200; (4) the feedforward path 255 of the SDM 200; and (5) the clamp circuit 400. The following discusses each of the above control scenarios.

[0054] Scenario (1): The control signal Cdx controls the loop filter 210. Figure 2 , Figure 2 FIG. 5 is a circuit diagram of a resonator 500 according to an embodiment of the present invention. The resonator 500 includes an integrator 510 , an integrator 520 , and an impedance 530 . Figure 1 The resonator 212a and the resonator 212b can be implemented by the resonator 500. The integrator 510 and the integrator 520 each include a resistor R, a capacitor C and an operational amplifier 512 or 522. The connection method of the components is as follows: Figure 2 As shown, the operation principle of the integrator 510 and the integrator 520 is well known to those skilled in the art, so it will not be repeated. Impedance 530 is located on the feedback path of the resonator 500, one end of which is coupled to the output end of the operational amplifier 522 of the integrator 520, and the other end is coupled to one of the input ends of the operational amplifier 512 of the integrator 510. Impedance 530 includes a variable resistor 532. Under the control of the control signal S1, the integrator 510 and / or the integrator 520 can operate in a passive mode. More specifically, the control signal S1 can turn off the operational amplifier 512 and / or the operational amplifier 522, so that the integrator 510 and the integrator 520 only have passive components (i.e., resistor R and capacitor C). When the image or blocking in the SDM 200 is too large, turning off the operational amplifier 512 and / or the operational amplifier 522 helps to stabilize the circuit. In addition, turning off the operational amplifier 512 and / or the operational amplifier 522 also has the technical effect of saving power.

[0055] Back to Figure 1 , the control signal Cdx can also reduce the order of the loop filter 210. More specifically, when the switch 214 is turned on by the control signal S3, the resonator 212a is bypassed, which is equivalent to reducing the order of the loop filter 210 by two orders. Bypassing the resonator 212a is equivalent to controlling the resonator 212a to be inactive. When the image or blocking in the SDM 200 is too large, reducing the order of the loop filter 210 helps stabilize the circuit. In addition, reducing the order of the loop filter 210 also has the technical effect of saving power.

[0056] Scenario (2): The control signal Cdx controls the input operating range of the quantizer 220. More specifically, the detection circuit 300c can measure the output swing of the resonator 212a, and then turn on / off the comparator in the quantizer 220, or adjust the binary search cycle of the quantizer 220. For example, when the detection circuit 300c detects that the output swing of the resonator 212a is less than the first preset value (indicating that the most significant bit of the digital output signal Dout may be logic 0) or greater than the second preset value (indicating that the most significant bit of the digital output signal Dout may be logic 1) (the second preset value is greater than the first preset value), the control signal S4 turns off the comparator corresponding to the higher bit in the quantizer 220, or controls the quantizer 220 to skip the first few cycles corresponding to the higher bit in the binary search. In other words, the input operating range of the quantizer 220 can be the number of active comparators, or the number of cycles of the binary search actually performed.

[0057] Scenario (3): The control signal Cdx controls the switch 240 to couple the output of the DAC 230 to the input of the resonator 212a or the input of the resonator 212b. When the resonator 212a is bypassed, the control signal Cdx can compliantly control the switch 240 to couple the output of the DAC 230 to the input of the resonator 212b. When the resonator 212a is not bypassed, the control signal Cdx can control the switch 240 to couple the output of the DAC 230 to the input of the resonator 212a or the input of the resonator 212b.

[0058] Scenario (4): The control signal Cdx controls the impedance circuit 250. The feedforward path 255 connects the input end of the loop filter 210 and the output end of the loop filter 210, and includes the impedance circuit 250. The impedance of the impedance circuit 250 is adjustable (for example, the impedance circuit 250 includes a variable resistor and / or a variable capacitor), and the control signal S6 adjusts the feedforward of the SDM 200 by adjusting the equivalent impedance of the impedance circuit 250.

[0059] Scenario (5): The control signal Cdx adjusts the magnitude of the clamping voltage of the clamping circuit 400 to limit the voltage value of the corresponding node, thereby suppressing mirroring or blocking, and making the circuit more stable.

[0060] See also Figure 2, the detection circuit 300b is coupled to the output end of the integrator 510 and the input end of the integrator 520, and is used to detect the voltage of the internal node of the resonator 500 to generate the control signal Cd2. The clamping circuit 400b is coupled to the output end of the integrator 510 and the input end of the integrator 520, and is used to limit the node voltage of the output end of the integrator 510 and the input end of the integrator 520. Please note that for the sake of simplicity, Figure 1 The detection circuit 300 and the clamping circuit 400 electrically connected to the internal nodes of the resonator 212b are not shown, however, those skilled in the art can Figure 1 and Figure 2 The detection circuit 300 and the clamping circuit 400 are implemented in accordance with the disclosure.

[0061] In some embodiments, the aforementioned control signal Cdx is used to control the components electrically connected to the detection circuit 300 that generates the control signal Cdx. More specifically, the control signal S1 can be the control signal Cd1, the control signal Cd2, or the control signal Cd3; the control signal S2 can be the control signal Cd3 or the control signal Cd4; the control signal S3 can be the control signal Cd1 or the control signal Cd2; the control signal S4 can be the control signal Cd4; the control signal S7 can be the control signal Cd1; the control signal S8 can be the control signal Cd2; the control signal S9 can be the control signal Cd3; and the control signal S10 can be the control signal Cd4. In addition, the control signal S5 can be equal to the control signal S3; and the control signal S6 can be any of the control signals Cdx.

[0062] In other embodiments, any one of the control signals S1 to S10 may be equal to any one of the control signals Cd1 to Cd4 .

[0063] Figure 3 4 is a circuit diagram of a clamping circuit 400 according to an embodiment of the present invention. The clamping circuit 400 mainly includes a transistor 412, a transistor 414, a transistor 416, a transistor 418, and a plurality of switches. The clamping voltage (i.e., the voltage difference between the node N1 and the node N2) of the clamping circuit 400 can be adjusted by switching the plurality of switches. The node N1 and the node N2 are electrically connected to the output ends of the integrator or operational amplifier 610a and the integrator or operational amplifier 610b, so that the output voltage of the integrator or operational amplifier 610a and the integrator or operational amplifier 610b is limited to the clamping voltage of the clamping circuit 400. The number of transistors and the number of switches of the clamping circuit 400 are not limited to Figure 3 The illustration is limited, and the operation principle of the clamp circuit 400 is well known to those skilled in the art, so it is not described in detail. Similar to the integrators 510 and 520, the integrators or operational amplifiers 610a and 610b can be adjusted to operate in a passive mode.

[0064] Figure 4 FIG. 4 is a circuit diagram of an ADC according to another embodiment of the present invention. Figure 4 Examples and Figure 1 The embodiment is similar to Figure 4 The ADC 15 further includes a control circuit 700 and a memory 800. Figure 4 In the embodiment of the present invention, the control signal S (including S1 to S10) is generated by the control circuit 700 according to the detection result DR (including DR1 to DR4) of the detection circuit 300, rather than being directly generated by the detection circuit 300. More specifically, the control circuit 700 can be a circuit or electronic component with program execution capability, such as a central processing unit, a microprocessor, a microprocessing unit or a digital signal processor, which performs control by executing program codes or program instructions stored in the memory 800. In some embodiments, the memory 800 stores a lookup table, and the control circuit 700 uses the detection result DR to find the corresponding control mode in the lookup table to suppress the mirror or blocking in the SDM 200 and achieve the technical effect of power saving.

[0065] Compared to Figure 1 ADC 10, Figure 4 The ADC 15 can simultaneously consider the voltages of multiple nodes of the SDM 200 to make a comprehensive control for the aforementioned scenarios, thereby achieving a preferred combination of the following multiple circuit characteristics: the order of the loop filter 210; the coefficients of the signal transfer function (STF) and / or the noise transfer function (NTF); the swing; the clamping voltage of the clamping circuit 400; the maximum signal-to-noise ratio (SNR); the maximum dynamic range, the maximum error vector magnitude (EVM); the maximum swing stability; the maximum blocker (co-existence) ability; and the lowest power consumption. Figure 1 The embodiment has a faster response time, in other words, the circuit can be adjusted faster; Figure 4 The embodiment of has a more comprehensive and diverse adjustment strategy. Please note that Figure 4 The control circuit 700 can also be individually adjusted for the above-mentioned multiple scenarios; in other words, at least one of the control signals S1 to S10 is not dependent on the other control signals.

[0066] Figure 5FIG. 3 is a functional block diagram of an embodiment of a detection circuit 300. The detection circuit 300 includes a low-resolution ADC 310 and a region control circuit 320. The low-resolution ADC 310 converts the node voltage Vn into a detection result DRx (in Figure 4 In the example, x is an integer and 1≤x≤4), the regional control circuit 320 generates a control signal Cdx according to the detection result DRx. The number of bits of the low-resolution ADC 310 is less than the number of bits of ADC 10 and ADC 15. For example, the low-resolution ADC 310 can be implemented as a 2-bit ADC to quickly obtain the detection result DRx. The regional control circuit 320 can be a logic circuit composed of multiple transistors. Those skilled in the art can implement the regional control circuit 320 according to the above content. Figure 5 The detection circuit 300 is applied to Figure 4 In the embodiment of the present invention, the detection circuit 300 includes the low-resolution ADC 310 but does not include the regional control circuit 320. When the node voltage Vn is large (for example, the swing of the node is large due to the presence of mirror or blocking), the detection result DRx is also large.

[0067] Figure 6 FIG. 3 is a functional block diagram of another embodiment of the detection circuit 300. The detection circuit 300 includes a comparator 330 and a regional control circuit 320. The comparator 330 compares the node voltage Vn with a preset voltage to generate a detection result DRx, and the regional control circuit 320 generates a control signal Cdx according to the detection result DRx. The comparator 330 can be regarded as a low-resolution ADC 310 with one bit. Figure 6 The detection circuit 300 is applied to Figure 4 In the embodiment of the present invention, the detection circuit 300 includes the comparator 330 but does not include the region control circuit 320.

[0068] In summary, the ADC of the present invention utilizes a detection circuit to detect the node voltage of the delta-sigma modulator, and adaptively adjusts the ADC according to the detection result to improve the stability of the ADC and reduce power consumption.

[0069] Please note that in the above-mentioned figures, the shapes, sizes and proportions of the components are only for illustration purposes, and are provided for those skilled in the art to understand the present invention, and are not intended to limit the present invention.

[0070] Although the embodiments of the present invention are described above, the embodiments are not intended to limit the present invention. Those skilled in the art may make changes to the technical features of the present invention based on the explicit or implicit contents of the present invention. All these changes may fall within the scope of patent protection sought by the present invention. In other words, the scope of patent protection of the present invention shall be subject to that defined in the claims of this specification.

Claims

1. An analog-to-digital converter, for receiving an analog input signal and generating a digital code, comprising: A delta-sigma modulator, comprising: A loop filter, used for receiving the analog input signal; a quantizer, coupled to the loop filter, for quantizing an output of the loop filter to generate a digital output signal; and a digital-to-analog converter, coupled to the quantizer and the loop filter; a down-conversion filter, coupled to the delta-sigma modulator, for converting the digital output signal into the digital code; and a detection circuit coupled to the delta-sigma modulator, for detecting a node voltage of the delta-sigma modulator and generating a control signal; in, The control signal is used to control the loop filter and / or the quantizer.

2. The analog-to-digital converter of claim 1, wherein the loop filter comprises a resonator, the resonator comprises an operational amplifier, and the control signal is used to shut down the operational amplifier.

3. The analog-to-digital converter as claimed in claim 1, wherein the loop filter comprises a resonator, and the control signal is used to control the resonator to be inactive.

4. The analog-to-digital converter of claim 3, wherein the resonator is a first resonator, the loop filter further comprises a second resonator, an input end of the second resonator is coupled to an output end of the first resonator, the delta-sigma modulator further comprises a switch coupled between the loop filter and the digital-to-analog converter, and the control signal is used to control the switch so that when the first resonator is inoperative, an output end of the digital-to-analog converter is coupled to the input end of the second resonator.

5. The analog-to-digital converter as claimed in claim 1 , wherein the loop filter comprises a first resonator and a second resonator, an input end of the second resonator is coupled to an output end of the first resonator, the delta-sigma modulator further comprises a switch coupled between the loop filter and the digital-to-analog converter, and the control signal is used to control the switch to control an output end of the digital-to-analog converter to couple to an input end of the first resonator or the input end of the second resonator. 6 . The analog-to-digital converter as claimed in claim 1 , wherein the control signal is used to control an input operating range of the quantizer. 7 . The analog-to-digital converter as claimed in claim 1 , wherein the analog-to-digital converter further comprises a clamp circuit coupled to the delta-sigma modulator, and the control signal is used to control a clamp voltage of the clamp circuit. 8 . The analog-to-digital converter of claim 1 , wherein the detection circuit comprises a low-resolution analog-to-digital converter, and the bit number of the low-resolution analog-to-digital converter is smaller than the bit number of the analog-to-digital converter.

9. An analog-to-digital converter, for receiving an analog input signal and generating a digital code, comprising: A delta-sigma modulator, comprising: A loop filter, used for receiving the analog input signal; a quantizer, coupled to the loop filter, for quantizing an output of the loop filter to generate a digital output signal; and a digital-to-analog converter, coupled to the quantizer and the loop filter; a down-conversion filter, coupled to the delta-sigma modulator, for converting the digital output signal into the digital code; a detection circuit coupled to the delta-sigma modulator, for detecting a node voltage of the delta-sigma modulator and generating a detection result; as well as a control circuit, coupled to the detection circuit, for generating a control signal according to the detection result; The control signal is used to control the loop filter and / or the quantizer.

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