Display device

Abstract

A display device according to an exemplary embodiment of the present disclosure includes: a substrate in which a plurality of sub-pixels are defined, each of the plurality of sub-pixels including an emission region and a circuit region; a driving transistor disposed in the circuit region and including a first gate electrode and a first source electrode disposed on the same layer; a storage capacitor disposed in the circuit region and including a first capacitor electrode electrically connected to the first gate electrode and disposed below the first gate electrode; an insulating layer that flattens the upper portions of the driving transistor and the storage capacitor; and a light-emitting element disposed on the insulating layer. Therefore, by disposing the first capacitor electrode electrically connected to the first gate electrode below the first gate electrode, the parasitic capacitance between the first capacitor electrode and the light-emitting element can be minimized.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of priority from Korean Patent Application No. 10-2019-0115279 filed in the Korean Intellectual Property Office on September 19, 2019, the disclosure of which is incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a display device, and more particularly, to a display device for minimizing parasitic capacitance between a storage capacitor and a cathode. Background Art

[0004] Display devices used for computer monitors, TVs, and mobile phones include organic light emitting display devices (OLEDs) that emit light by themselves, liquid crystal display (LCD) devices that require a separate light source, and the like.

[0005] Such display devices are being applied to more and more various fields including not only computer monitors and TVs but also personal mobile devices, and thus, display devices having reduced volume and weight while having a wide display area are being studied.

[0006] Meanwhile, a display device includes a plurality of sub-pixels and a dam disposed between the plurality of sub-pixels to reduce color mixing between the plurality of sub-pixels. However, an additional process is required to form the dam, and there is a problem that moisture penetrates into the display device through the dam formed of an organic material. Therefore, in order to simplify the process and minimize moisture penetration, a display device in which such a dam is removed is being studied. Summary of the invention

[0007] An object to be achieved by the present disclosure is to provide a display device in which a reduction in light emitting efficiency due to removal of a bank is minimized.

[0008] Another object to be achieved by the present disclosure is to provide a display device in which a parasitic capacitance between a storage capacitor and a cathode is minimized.

[0009] Another object to be achieved by the present disclosure is to provide a display device in which leakage of light emitted from each of a plurality of sub-pixels is minimized.

[0010] The objects of the present disclosure are not limited to the above objects, and other objects not mentioned above can be clearly understood by those skilled in the art from the following description.

[0011] According to one aspect of the present disclosure, a display device includes: a substrate in which a plurality of sub-pixels are defined, each of the plurality of sub-pixels including an emission region and a circuit region; a driving transistor disposed in the circuit region and including a first gate electrode and a first source electrode disposed on the same layer; a storage capacitor disposed in the circuit region and including a first capacitor electrode electrically connected to the first gate electrode and disposed below the first gate electrode; an insulating layer that flattens the upper portions of the driving transistor and the storage capacitor; and a light-emitting element disposed on the insulating layer. Therefore, by disposing the first capacitor electrode electrically connected to the first gate electrode below the first gate electrode, the parasitic capacitance between the first capacitor electrode and the light-emitting element can be minimized.

[0012] According to another aspect of the present disclosure, a display device includes: a substrate in which a plurality of sub-pixels including a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel are defined; a first capacitor electrode disposed in each of the plurality of sub-pixels; a driving transistor disposed in each of the plurality of sub-pixels and including a first gate electrode electrically connected to the first capacitor electrode and a first source electrode disposed on the first capacitor electrode; and a light emitting element including a plurality of anodes disposed on the driving transistor in each of the plurality of sub-pixels, and a cathode disposed on the entire plurality of sub-pixels to cover the plurality of anodes and a light emitting layer, wherein a portion of a lower surface of the light emitting layer is disposed on the same plane as the corresponding lower surfaces of the plurality of anodes. Therefore, it is feasible to minimize the distortion of a data signal due to the parasitic capacitance between the cathode and the storage capacitor while simplifying the process by removing the dam.

[0013] Additional details of exemplary embodiments are included in the detailed description and accompanying drawings.

[0014] According to the present disclosure, by minimizing the anode electrode provided in the circuit region, the occurrence of light leakage through the circuit region and color coordinate distortion may be minimized.

[0015] According to the present disclosure, by reducing the arrangement area of ​​the anode in the circuit region, power consumption can be reduced and color coordinate distortion can be minimized.

[0016] According to the present disclosure, by disposing a first capacitor electrode connected to a first gate electrode of a first transistor among electrodes of a storage capacitor under the first gate electrode, a parasitic capacitance between the first capacitor electrode and a cathode may be reduced.

[0017] According to the present disclosure, by disposing a plurality of color filters between a storage capacitor and a cathode, distortion of a data signal due to parasitic capacitance between the storage capacitor and the cathode may be minimized.

[0018] The effects according to the present disclosure are not limited to the contents of the above-mentioned examples, and more various effects are included in the present specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The above and other aspects, features and other advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0020] Figure 1 is a plan view of a display device according to an exemplary embodiment of the present disclosure;

[0021] Figure 2 is a circuit diagram of a sub-pixel of a display device according to an exemplary embodiment of the present disclosure;

[0022] Figure 3 yes Figure 1 An enlarged plan view of area A;

[0023] Figure 4 is along Figure 3 A cross-sectional view taken along line IV-IV';

[0024] Figure 5 is an enlarged plan view of a display device according to another exemplary embodiment of the present disclosure; and

[0025] Figure 6 is along Figure 5 A cross-sectional view taken along line VI-VI'. DETAILED DESCRIPTION

[0026] By referring to the exemplary embodiments described in detail below and the accompanying drawings, the advantages and features of the present disclosure and the methods for achieving these advantages and features will be clear. However, the present disclosure is not limited to the exemplary embodiments disclosed herein, but will be implemented in various forms. Exemplary embodiments are provided only by way of example so that those skilled in the art can fully understand the disclosure of the present disclosure and the scope of the present disclosure. Therefore, the present disclosure will only be limited by the scope of the appended claims.

[0027] The shapes, sizes, ratios, angles, quantities, etc. shown in the drawings for describing exemplary embodiments of the present disclosure are merely examples, and the present disclosure is not limited thereto. Throughout the specification, the same reference numerals generally represent the same elements. In addition, in the following description of the present disclosure, a detailed explanation of known related art may be omitted to avoid unnecessarily obscuring the subject matter of the present disclosure. Terms such as "including", "having" and "consisting of..." used herein are generally intended to allow the addition of other components unless these terms are used together with the term "only". Unless otherwise expressly stated, any reference to the singular may include the plural.

[0028] Even if not expressly stated, parts are interpreted as including ordinary margins of error.

[0029] When terms such as “on,” “over,” “below,” and “next” are used to describe the positional relationship between two components, one or more components may be located between the two components unless these terms are used with the term “immediately” or “directly.”

[0030] When an element or a layer is referred to as being “on” another element or layer, the other layer or element can be directly on the other element or interposed therebetween.

[0031] Although the terms "first", "second", etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from other components. Therefore, in the technical concept of the present disclosure, the first component to be mentioned below can be the second component.

[0032] Throughout the specification, like reference numerals generally refer to like elements.

[0033] The size and thickness of each component shown in the drawings are illustrated for convenience of description, and the present disclosure is not limited to the size and thickness of the components shown.

[0034] The features of the various embodiments of the present disclosure may be partially or completely adhered to or combined with each other, and may be interlocked and operated in various technical ways, and the embodiments may be performed independently or in association with each other.

[0035] Hereinafter, a display device according to exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0036] Figure 1 is a plan view of a display device according to an exemplary embodiment of the present disclosure. For ease of description, Figure 1 Only a plurality of sub-pixels SP and the substrate 110 are shown among various components of the display device 100 .

[0037] The substrate 110 is a supporting member for supporting other components of the display device 100, and may be formed of an insulating material. For example, the substrate 110 may be formed of glass or resin. In addition, the substrate 110 may be formed of a polymer or plastic such as polyimide (PI), or may be formed of a material having flexibility.

[0038] The substrate 110 includes a display area AA and a non-display area NA.

[0039] The display area AA is an area for displaying an image. In the display area AA, a plurality of sub-pixels SP for displaying an image and a driving circuit for driving the plurality of sub-pixels SP may be provided. The driving circuit may include various thin film transistors, storage capacitors, and lines for driving the sub-pixels SP. For example, the circuit may be formed of various components such as a driving transistor, a switching transistor, a sensing transistor, a storage capacitor, a gate line, a data line, etc., but is not limited thereto.

[0040] The non-display area NA is an area where no image is displayed. In the non-display area NA, various lines, driver ICs, etc. for driving the sub-pixels SP disposed in the display area AA are disposed. For example, various driver ICs such as a gate driver IC and a data driver IC may be disposed in the non-display area NA.

[0041] At the same time, although Figure 1 It is illustrated that the non-display area NA surrounds the display area AA, but the non-display area NA may be an area extending from one side of the display area AA, and is not limited thereto.

[0042] A plurality of sub-pixels SP are disposed in the display area AA of the substrate 110. Each of the plurality of sub-pixels SP is an independent unit that emits light, and each of the plurality of sub-pixels SP is provided with a light-emitting element and a driving circuit. For example, the plurality of sub-pixels SP may include a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel, but is not limited thereto.

[0043] In the following, reference will be made to Figure 2 A driving circuit of the plurality of sub-pixels SP is described in detail.

[0044] Figure 2 is a circuit diagram of a sub-pixel of a display device according to an exemplary embodiment of the present disclosure. Figure 2 The driving circuit for driving the light emitting element 160 of the plurality of sub-pixels SP includes a first transistor 120, a second transistor 130, a third transistor 140, a storage capacitor 150, a gate line GL, a data line DL, a high potential power line VDD, a sensing line SL, and a reference line RL.

[0045] Reference Figure 2, each of the first transistor 120, the second transistor 130, and the third transistor 140 included in the driving circuit of the sub-pixel SP includes a gate electrode, a source electrode, and a drain electrode. The first transistor 120, the second transistor 130, and the third transistor 140 may be a P-type thin film transistor or an N-type thin film transistor. For example, in a P-type thin film transistor, since holes flow from the source electrode to the drain electrode, current may flow from the source electrode to the drain electrode. In an N-type thin film transistor, since electrons flow from the source electrode to the drain electrode, current may flow from the drain electrode to the source electrode. In the following, it is assumed that the first transistor 120, the second transistor 130, and the third transistor 140 are N-type thin film transistors, in which current flows from the drain electrode to the source electrode, but the present disclosure is not limited thereto.

[0046] The first transistor 120 includes a first active layer, a first gate electrode, a first source electrode, and a first drain electrode. The first gate electrode is connected to the first node N1, the first source electrode is connected to the first electrode of the light emitting element 160, and the first drain electrode is connected to the high potential power line VDD. When the voltage of the first node N1 is higher than the threshold voltage, the first transistor 120 is turned on, and when the voltage of the first node N1 is lower than the threshold voltage, the first transistor 120 is turned off. In addition, when the first transistor 120 is turned on, the first transistor 120 can transmit a power signal from the high potential power line VDD to the light emitting element 160. The first transistor 120 can also be called a driving transistor.

[0047] The second transistor 130 includes a second active layer, a second gate electrode, a second source electrode, and a second drain electrode. The second gate electrode is connected to the gate line GL, the second source electrode is connected to the first node N1, and the second drain electrode is connected to the data line DL. The second transistor 130 can be turned on or off based on a gate signal from the gate line GL. When the second transistor 130 is turned on, the data signal from the data line DL can be charged to the first node N1. The second transistor 130 can also be called a switching transistor.

[0048] The third transistor 140 includes a third active layer, a third gate electrode, a third source electrode, and a third drain electrode. The third gate electrode is connected to the sensing line SL, the third source electrode is connected to the second node N2, and the third drain electrode is connected to the reference line RL. The third transistor 140 can be turned on or off based on the sensing signal from the sensing line SL. When the third transistor 140 is turned on, the reference voltage from the reference line RL can be transmitted to the storage capacitor 150. The third transistor 140 can also be referred to as a sensing transistor. At the same time, Figure 2 , the gate line GL and the sensing line SL are illustrated as separate lines, but the gate line GL and the sensing line SL may be implemented as a single line.

[0049] The storage capacitor 150 includes a first capacitor electrode and a second capacitor electrode. The first capacitor electrode is connected to the first node N1, and the second capacitor electrode is connected to the second node N2. When the light emitting element 160 emits light, the storage capacitor 150 maintains the potential difference between the first gate electrode and the first source electrode of the first transistor 120, thereby allowing a constant current to be supplied to the light emitting element 160.

[0050] The first electrode of the light emitting element 160 is connected to the second node N2, and the second electrode is connected to the low potential power line VSS. The light emitting element 160 may receive current from the first transistor 120 to emit light. At this time, the low potential power signal from the low potential power line may be a ground voltage.

[0051] At the same time, Figure 2 , the driving circuit of the subpixel SP of the display device 100 according to the exemplary embodiment of the present disclosure is described as having a 3T1C structure including three transistors and one storage capacitor. However, the number and connection relationship of the transistors and the storage capacitor may be variously changed according to the design and are not limited thereto.

[0052] In the following, reference will be made to Figure 3 and Figure 4 The plurality of sub-pixels SP are described in more detail.

[0053] Figure 3 yes Figure 1 An enlarged plan view of area A. Figure 4 is along Figure 3 A cross-sectional view taken along line IV-IV'. Figure 3 is a plan view showing four sub-pixels SP. Figure 3 and Figure 4 The display device 100 according to the exemplary embodiment of the present disclosure includes a substrate 110, a gate line GL, a data line DL, a high potential power line VDD, a sensing line SL, a reference line RL, a light emitting element 160, a first transistor 120, a second transistor 130, a third transistor 140, a storage capacitor 150, a buffer layer 111, a gate insulating layer 112, a passivation layer 113, and a planarization layer 114. Figure 3 In FIG. 1 , for the sake of convenience of explanation, multiple color filters are not shown. Figure 4 , only the first color filter 171 among the plurality of color filters is shown.

[0054] First, refer to Figure 3 The plurality of sub-pixels SP include a red sub-pixel SPR, a green sub-pixel SPG, a blue sub-pixel SPB, and a white sub-pixel SPW. Each of the plurality of sub-pixels SP includes an emission area and a circuit area CA.

[0055] The emission area EA is an area that can independently emit light of one color. The light emitting element 160 can be disposed in the emission area EA. The emission area EA of the red sub-pixel SPR is a red emission area that emits red light, the emission area EA of the green sub-pixel SPG is a green emission area that emits green light, the emission area EA of the blue sub-pixel SPB is a blue emission area that emits blue light, and the emission area EA of the white sub-pixel SPW can be a white emission area that emits white light.

[0056] The circuit region CA is a region where a driving circuit for driving the plurality of light emitting elements 160 is disposed. In the circuit region CA, a first transistor 120, a second transistor 130, a third transistor 140, and a storage capacitor 150 may be disposed.

[0057] Reference Figure 3 and Figure 4 , a plurality of high potential power lines VDD, a plurality of data lines DL, and a reference line extending in a column direction between a plurality of sub-pixels SP are provided on the substrate 110. The plurality of high potential power lines VDD, the plurality of data lines DL, and the reference line RL may be provided on the same layer on the substrate 110, and may be formed of the same conductive material. For example, the plurality of high potential power lines VDD, the plurality of data lines DL, and the reference line RL may be formed of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

[0058] The plurality of high potential power lines VDD are lines for transmitting a power signal to each of the plurality of sub-pixels SP, and include a first high potential power line VDD1 and a second high potential power line VDD2. Two sub-pixels SP adjacent to each other in the row direction may share one high potential power line VDD among the plurality of high potential power lines VDD. For example, the first high potential power line VDD1 is disposed on the left side of the red sub-pixel SPR, and transmits a power signal to the first transistor 120 of the red sub-pixel SPR and the white sub-pixel SPW. The second high potential power line VDD2 is disposed on the right side of the green sub-pixel SPG, and transmits a power signal to the first transistor 120 of the blue sub-pixel SPB and the green sub-pixel SPG.

[0059] The plurality of data lines DL are lines for transmitting data signals to each of the plurality of sub-pixels SP, and include a first data line DL1, a second data line DL2, a third data line DL3, and a fourth data line DL4. The first data line DL1 is disposed between the red sub-pixel SPR and the white sub-pixel SPW, that is, located on the right side of the red sub-pixel SPR, and transmits the data signal to the second transistor 130 of the red sub-pixel SPR. The second data line DL2 is disposed between the first data line DL1 and the white sub-pixel SPW, that is, located on the left side of the white sub-pixel SPW, and transmits the data signal to the second transistor 130 of the white sub-pixel SPW. The third data line DL3 is disposed between the blue sub-pixel SPB and the green sub-pixel SPG, that is, located on the right side of the blue sub-pixel SPB, and transmits the data signal to the second transistor 130 of the blue sub-pixel SPB. The fourth data line DL4 is disposed between the third data line DL3 and the green sub-pixel SPG, that is, located on the left side of the green sub-pixel SPG, and transmits the data signal to the second transistor 130 of the green sub-pixel SPG.

[0060] The reference line RL is a line for transmitting a reference signal to each of the plurality of sub-pixels SP, and may be disposed between the white sub-pixel SPW and the blue sub-pixel SPB. The plurality of sub-pixels SP constituting one pixel may share one reference line RL. The reference line RL may transmit a reference signal to the third transistor 140 of the red sub-pixel SPR, the white sub-pixel SPW, the blue sub-pixel SPB, and the green sub-pixel SPG.

[0061] The buffer layer 111 is disposed on the plurality of high potential power lines VDD, the plurality of data lines DL, and the reference line RL. The buffer layer 111 can reduce the penetration of moisture or impurities through the substrate 110. The buffer layer 111 can be made of, for example, silicon oxide (SiO x ) or silicon nitride (SiN x ) is formed of a single layer or multiple layers, but is not limited thereto. The buffer layer 111 may be omitted according to the type of the substrate 110 or the type of the thin film transistor, but is not limited thereto.

[0062] The first transistor 120 is disposed in the circuit area CA of each of the sub-pixels SP. The first transistor 120 includes a first gate electrode 121, a first source electrode 122, a first drain electrode 123, and a first active layer 124. The first transistor 120 electrically connected to the first electrode 161 of the light emitting element 160 and the high potential power line VDD may be a driving transistor.

[0063] First, the first drain electrode 123 is disposed on the buffer layer 111. The first drain electrode 123 is electrically connected to a plurality of high potential power lines VDD. Specifically, the first drain electrode 123 of the red sub-pixel SPR and the white sub-pixel SPW may be electrically connected to the first high potential power line VDD1 through a contact hole formed in the buffer layer 111. The first drain electrode 123 of the blue sub-pixel SPB and the green sub-pixel SPG may be electrically connected to the second high potential power line VDD2 through a contact hole formed in the buffer layer 111.

[0064] The first active layer 124 is disposed on the buffer layer 111. The first active layer 124 may be formed of a semiconductor material such as an oxide semiconductor, amorphous silicon, or polycrystalline silicon, but is not limited thereto. For example, when the first active layer 124 is formed of an oxide semiconductor, the first active layer 124 may be formed of a channel region, a source region, and a drain region, and the source region and the drain region may be a conductor region. However, the present disclosure is not limited thereto.

[0065] At the same time, the first drain electrode 123 of the red sub-pixel SPR and the white sub-pixel SPW may be formed integrally, and the first drain electrode 123 of the blue sub-pixel SPB and the green sub-pixel SPG may be formed integrally. Specifically, the first drain electrode 123 of the red sub-pixel SPR and the first drain electrode 123 of the white sub-pixel SPW may be formed integrally to share a first high potential power line VDD1. For example, a power signal from the first high potential power line VDD1 may be transmitted to the first drain electrode 123 of the white sub-pixel SPW through the first drain electrode 123 of the red sub-pixel SPR. The power signal from the second high potential power line VDD2 may be transmitted to the first drain electrode 123 of the blue sub-pixel SPB through the first drain electrode 123 of the green sub-pixel SPG. However, the present disclosure is not limited thereto. The first drain electrode 123 of the red sub-pixel SPR and the first drain electrode 123 of the white sub-pixel SPW may be formed separately, and the first drain electrode 123 of the blue sub-pixel SPB and the first drain electrode 123 of the green sub-pixel SPG may be formed separately.

[0066] The first active layer 124 and the first drain electrode 123 of each of the plurality of sub-pixels SP may be integrally formed. For example, when a voltage is applied to the first gate electrode 121 in the red sub-pixel SPR, the first drain electrode 123 integrally formed with the first active layer 124 and being a conductor region transmits a power signal from the first high potential power line VDD1 to the first active layer 124 and the first source electrode 122. The first drain electrode 123 may be defined as being integrated with the first high potential power line VDD1, but is not limited thereto.

[0067] The gate insulating layer 112 is disposed on the first active layer 124 and the first drain electrode 123. The gate insulating layer 112 is a layer for insulating the first gate electrode 121 and the first active layer 124 from each other, and may be formed of an insulating material. For example, the gate insulating layer 112 may be made of silicon oxide (SiO x ) or silicon nitride (SiN x ) is formed by a single layer or multiple layers, but is not limited to this.

[0068] In each of the plurality of sub-pixels SP, a first gate electrode 121 is disposed on the gate insulating layer 112 to overlap the first active layer 124. The first gate electrode 121 may be formed of a conductive material, for example, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

[0069] In each of the plurality of sub-pixels SP, a first source electrode 122 is disposed on the gate insulating layer 112 to be spaced apart from the first gate electrode 121. The first source electrode 122 may be electrically connected to the first active layer 124 through a contact hole formed in the gate insulating layer 112. The first source electrode 122 and the first gate electrode 121 may be disposed on the same layer and may be formed of the same conductive material. However, the present disclosure is not limited thereto. The first source electrode 122 may be formed of a conductive material, for example, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr) or an alloy thereof, but is not limited thereto.

[0070] The second transistor 130 is disposed in the circuit area CA of each of the plurality of sub-pixels SP. The second transistor 130 includes a second gate electrode 131, a second source electrode 132, a second drain electrode 133, and a second active layer 134. The second transistor 130 electrically connected to the gate line GL, the data line DL, and the first gate electrode 121 of the first transistor 120 may be a switching transistor.

[0071] First, in each of the plurality of sub-pixels SP, a second drain electrode 133 is disposed between the substrate 110 and the buffer layer 111. The second drain electrode 133 is electrically connected to one of the plurality of data lines DL. The second drain electrode 133 may be formed integrally with the plurality of data lines DL, and may be formed of the same conductive material as the plurality of data lines DL. For example, the second drain electrode 133 of the red sub-pixel SPR may be formed integrally with the first data line DL1, the second drain electrode 133 of the white sub-pixel SPW may be formed integrally with the second data line DL2, the second drain electrode 133 of the blue sub-pixel SPB may be formed integrally with the third data line DL3, and the second drain electrode 133 of the green sub-pixel SPG may be formed integrally with the fourth data line DL4. The second drain electrode 133 may be formed of a conductive material, such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr) or an alloy thereof, but is not limited thereto.

[0072] In each of the plurality of sub-pixels SP, the second source electrode 132 is disposed to be spaced apart from the second drain electrode 133 between the substrate 110 and the buffer layer 111. The second source electrode 132 and the second drain electrode 133 may be disposed on the same layer and may be formed of the same conductive material. However, the present disclosure is not limited thereto. The second source electrode 132 may be formed of a conductive material, for example, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr) or an alloy thereof, but is not limited thereto.

[0073] In each of the plurality of sub-pixels SP, the second active layer 134 is disposed between the buffer layer 111 and the gate insulating layer 112. The second active layer 134 may be electrically connected to the second source electrode 132 and the second drain electrode 133 through a contact hole formed in the buffer layer 111. The second active layer 134 may be formed of a semiconductor material such as an oxide semiconductor, amorphous silicon, or polycrystalline silicon, but is not limited thereto.

[0074] In each of the plurality of sub-pixels SP, the second gate electrode 131 is disposed on the gate insulating layer 112 to overlap the second active layer 134. The second gate electrode 131 may be formed of a conductive material, for example, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

[0075] The second gate electrode 131 extends from the gate line GL. Therefore, the second gate electrode 131 and the gate line GL may be formed of the same conductive material. The gate line GL may be formed of a conductive material, for example, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

[0076] The gate line GL is a line that transmits a gate signal to each of the plurality of sub-pixels SP. The gate line GL crosses the plurality of sub-pixels SP and extends in the row direction. For example, the gate line GL is arranged to extend in the row direction between the circuit area CA and the emission area EA of each of the plurality of sub-pixels SP, and crosses a plurality of high potential power lines VDD extending in the column direction, a plurality of data lines DL, and a reference line RL.

[0077] The third transistor 140 is disposed in the circuit area CA of each of the sub-pixels SP. The third transistor 140 includes a third gate electrode 141, a third source electrode 142, a third drain electrode 143, and a third active layer 144. The third transistor 140 electrically connected to the reference line RL, the sensing line SL, and the second capacitor electrode 152 of the storage capacitor 150 may be a sensing transistor.

[0078] First, in each of the plurality of sub-pixels SP, a third source electrode 142 is disposed between the substrate 110 and the buffer layer 111. The third source electrode 142 is disposed on the same layer as the plurality of high potential power lines VDD, the plurality of data lines DL, and the reference line RL, and is formed of the same conductive material as the plurality of high potential power lines VDD, the plurality of data lines DL, and the reference line RL. The third source electrode 142 may be formed of a conductive material, for example, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

[0079] The third source electrode 142 may be electrically connected to the first source electrode 122. Specifically, the third source electrode 142 extends toward the first source electrode 122 to contact a portion of the first active layer 124 overlapping the first source electrode 122, thereby being electrically connected to the first source electrode 122. In addition, the third source electrode 142 may also be electrically connected to a second capacitor electrode 152 constituting a storage capacitor 150, which will be described later.

[0080] Meanwhile, the third source electrode 142 may function as a light blocking layer that blocks light incident on the first active layer 124 of the first transistor 120. For example, when light is irradiated on the first active layer 124, leakage current may occur, and thus, the reliability of the first transistor 120 may be reduced. In this case, the third source electrode 142 formed of a non-transparent conductive material is disposed under the first active layer 124 and the first gate electrode 121, thereby blocking light incident on the first active layer 124 from the bottom of the substrate. Therefore, the reliability of the first transistor 120 may be improved.

[0081] In each of the plurality of sub-pixels SP, a third active layer 144 is disposed between the buffer layer 111 and the gate insulating layer 112. The third active layer 144 may be electrically connected to the third source electrode 142 through a contact hole formed in the buffer layer 111, and may be electrically connected to the third drain electrode 143 through a contact hole formed in the gate insulating layer 112. The third active layer 144 may be formed of a semiconductor material such as an oxide semiconductor, amorphous silicon, or polycrystalline silicon, but is not limited thereto.

[0082] In each of the plurality of sub-pixels SP, a third gate electrode 141 is disposed on the gate insulating layer 112 to overlap the third active layer 144. The third gate electrode 141 is electrically connected to the sensing line SL. The third gate electrode 141 may be formed integrally with the sensing line SL and may be formed of the same conductive material as the sensing line SL. The third gate electrode 141 may be formed of a conductive material, for example, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

[0083] The sensing line SL is a line that transmits a sensing signal to each of the plurality of sub-pixels SP, and extends in a row direction between the plurality of sub-pixels SP. For example, the sensing line SL may be disposed to extend in a row direction at a boundary between the plurality of sub-pixels SP, and to cross a plurality of high potential power lines VDD extending in a column direction, a plurality of data lines DL, and a reference line RL.

[0084] In each of the plurality of sub-pixels SP, a third drain electrode 143 is disposed on the gate insulating layer 112. The third drain electrode 143 may be electrically connected to the third active layer 144 through a contact hole formed in the gate insulating layer 112. The third drain electrode 143 may be formed of a conductive material, for example, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

[0085] The third drain electrode 143 is electrically connected to the reference line RL through the auxiliary reference line SRL. A plurality of sub-pixels SP constituting one pixel may share one reference line RL. In this case, in order to transmit a reference signal from the reference line RL to each of the plurality of sub-pixels SP, an auxiliary reference line SRL electrically connected to the reference line RL and extending in the row direction may be provided. The auxiliary reference line SRL may be electrically connected to the reference line RL extending in the column direction between the white sub-pixel SPW and the blue sub-pixel SPB through a contact hole formed in the buffer layer 111 and the gate insulating layer 112. In addition, the auxiliary reference line SRL may extend from the reference line RL in the row direction and be electrically connected to the third drain electrode 143 of each of the plurality of sub-pixels SP. The auxiliary reference line SRL is integrally formed with the third drain electrode 143 and may be formed of the same conductive material. The auxiliary reference line SRL may be formed of a conductive material, for example, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr) or an alloy thereof, but is not limited thereto.

[0086] The storage capacitor 150 is disposed in the circuit area CA of each sub-pixel SP. The storage capacitor 150 can store the voltage between the first gate electrode 121 and the first source electrode 122 of the first transistor 120 so that the light emitting element 160 continuously maintains the same state during one frame period. The storage capacitor 150 includes a first capacitor electrode 151 and a second capacitor electrode 152.

[0087] In each of the plurality of sub-pixels SP, the first capacitor electrode 151 is disposed between the substrate 110 and the buffer layer 111. Among the conductive components disposed on the substrate 110, the first capacitor electrode 151 may be disposed closest to the substrate 110. The first capacitor electrode 151 may be integrally formed with the second source electrode 132 and electrically connected to the second source electrode 132. In addition, the first capacitor electrode 151 may be electrically connected to the first gate electrode 121 through a contact hole formed in the buffer layer 111. That is, the second source electrode 132 of the second transistor 130 and the first gate electrode 121 of the first transistor 120 may be electrically connected to each other through the first capacitor electrode 151. The first capacitor electrode 151 integrally formed with the second source electrode 132 may be formed of the same material as the second source electrode 132. The first capacitor electrode 151 may be formed of a conductive material, such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

[0088] In this case, the first capacitor electrode 151 is disposed under the first gate electrode 121 and the first source electrode 122. The first capacitor electrode 151 is disposed to overlap with the first source electrode 122.

[0089] In each of the plurality of sub-pixels SP, a second capacitor electrode 152 is disposed on the gate insulating layer 112. The second capacitor electrode 152 may be disposed on the first capacitor electrode 151 to overlap with the first capacitor electrode 151. The second capacitor electrode 152 may be integrally formed with the first source electrode 122 and electrically connected to the first source electrode 122. A portion of the first source electrode 122 that overlaps with the first capacitor electrode 151 may be defined as the second capacitor electrode 152. The second capacitor electrode 152 integrally formed with the first source electrode 122 may be formed of the same material as the first source electrode 122. The second capacitor electrode 152 may be formed of a conductive material, such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

[0090] In summary, the first capacitor electrode 151 of the storage capacitor 150 may be integrally formed with the second source electrode 132 and may be electrically connected to the first gate electrode 121 of the first transistor 120 and the second source electrode 132 of the second transistor 130. In addition, the second capacitor electrode 152 may be integrally formed with the first source electrode 122 and may be electrically connected to the first source electrode 122 of the first transistor 120 and the third source electrode 142 of the third transistor 140.

[0091] Next, a passivation layer 113 is disposed on the first transistor 120, the second transistor 130, the third transistor 140, the storage capacitor 150, a plurality of high potential power lines VDD, a plurality of data lines DL, a reference line RL, a gate line GL, and a sensing line SL. The passivation layer 113 is an insulating layer for protecting components under the passivation layer 113. For example, the passivation layer 113 may be made of silicon oxide (SiO x ) or silicon nitride (SiN x ) is formed of a single layer or multiple layers, but is not limited thereto. In addition, according to an embodiment, the passivation layer 113 may be omitted.

[0092] A plurality of color filters are disposed on the passivation layer 113. Specifically, the plurality of color filters may be disposed between the planarization layer 114 and the passivation layer 113. The plurality of color filters include a first color filter 171, a second color filter, and a third color filter. For example, the first color filter 571 may be a red color filter, the second color filter may be a blue color filter, and the third color filter may be a green color filter.

[0093] The first color filter 171 is disposed between the planarization layer 114 in the emission area EA of one sub-pixel SP among the plurality of sub-pixels SP and the substrate 110. For example, the first color filter 171 is a red color filter, and the first color filter 171 may be disposed between the planarization layer 114 in the emission area EA of the red sub-pixel SPR and the substrate 110.

[0094] Despite Figure 3 and Figure 4 Although not shown in the figure, the second color filter may be disposed between the planarization layer 114 in the emission area EA of another sub-pixel SP among the plurality of sub-pixels SP and the substrate 110. For example, the second color filter is a blue color filter, and the second color filter may be disposed between the planarization layer 114 in the emission area EA of the blue sub-pixel SPB and the substrate 110.

[0095] In addition, despite Figure 3 and Figure 4 Although not shown in the figure, the third color filter may be disposed between the planarization layer 114 in the emission area EA of another sub-pixel SP among the plurality of sub-pixels SP and the substrate 110. For example, the third color filter is a green color filter, and the third color filter may be disposed between the planarization layer 114 in the emission area EA of the green sub-pixel SPG and the substrate 110.

[0096] The planarization layer 114 is disposed on the passivation layer 113 and the plurality of color filters. The planarization layer 114 is an insulating layer for planarizing the upper portion of the substrate 110, on which the first transistor 120, the second transistor 130, the third transistor 140, the storage capacitor 150, the plurality of high potential power lines VDD, the plurality of data lines DL, the reference line RL, the gate line GL, and the sensing line SL are disposed. The planarization layer 114 may be formed of an organic material, and may be formed of a single layer or multiple layers of, for example, polyimide or photoacrylic. However, the present disclosure is not limited thereto.

[0097] The light emitting element 160 is disposed in each of the plurality of sub-pixels SP. In each of the plurality of sub-pixels SP, the light emitting element 160 is disposed on the planarization layer 114. The light emitting element 160 includes a first electrode 161, a light emitting layer 164, and a second electrode 165.

[0098] The first electrode 161 is disposed on the planarization layer 114 in the emission area EA. Since the first electrode 161 supplies holes to the light emitting layer 164, the first electrode 161 may be formed of a conductive material having a high work function and may be referred to as an anode. The first electrode 161 may be formed of, for example, a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), but is not limited thereto.

[0099] Meanwhile, when the display device 100 according to an exemplary embodiment of the present disclosure is a top emission type, a reflective layer formed of a metal material having excellent reflection efficiency (e.g., aluminum (Al) or silver (Ag)) may be added to the lower portion of the first electrode 161, so that light emitted from the light emitting layer 164 is reflected on the first electrode 161 to be guided in an upward direction, that is, to the second surface 165. In contrast, when the display device 100 is a bottom emission type, the first electrode 161 may be formed of only a transparent conductive material. Hereinafter, the display device 100 according to an exemplary embodiment of the present disclosure will be described under the assumption that the display device 100 is a bottom emission type.

[0100] The light emitting layer 164 is disposed on the first electrode 161 in the emission area EA and the circuit area CA. The light emitting layer 164 may be formed as a single layer throughout the plurality of sub-pixels SP. That is, the respective light emitting layers 164 of the plurality of sub-pixels SP may be connected to each other and formed integrally. The light emitting layer 164 may be configured as a single light emitting layer 164, or may have a structure in which a plurality of light emitting layers 164 emitting light of different colors are stacked. The light emitting layer 164 may also include an organic layer such as a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer.

[0101] The second electrode 165 is disposed on the light emitting layer 164 in the emission area EA and the circuit area CA. Since the second electrode 165 supplies electrons to the light emitting layer 164, the second electrode 165 may be formed of a conductive material having a low work function and may be referred to as a cathode. The second electrode 165 may be formed as a single layer throughout the plurality of sub-pixels SP. That is, the corresponding second electrodes 165 of the plurality of sub-pixels SP may be connected to each other and formed integrally. The second electrode 165 may be formed of a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), or the like, or an alloy of ytterbium (Yb), and may also include a layer doped with a metal. However, the present disclosure is not limited thereto. Meanwhile, although in Figure 3 and Figure 4 Although not shown in the figure, the second electrode 165 of the light emitting element 160 may be electrically connected to the low potential power line VSS so as to be supplied with a low potential power signal.

[0102] The light emitting element 160 includes an extension portion 162 extending from the first electrode 161 toward the circuit area CA. The extension portion 162 extends from the first electrode 161 of the emission area EA toward the first source electrode 122 of the circuit area CA, and may be electrically connected to the first source electrode 122 through a contact hole formed in the planarization layer 114 and the passivation layer 113. Therefore, the first electrode 161 of the light emitting element 160 may be electrically connected to the first source electrode 122 of the first transistor 120 and the second capacitor electrode 152 of the storage capacitor 150 through the extension portion 162.

[0103] The light emitting element 160 further includes a repair portion 163, which extends from a first electrode 161 disposed in one sub-pixel SP of the plurality of sub-pixels SP toward a circuit area CA of another sub-pixel SP adjacent to the one sub-pixel SP. The repair portion 163 extends toward a circuit area CA of another sub-pixel SP in a sub-pixel SP adjacent to the one sub-pixel SP that emits light of the same color as the one sub-pixel SP. For example, the repair portion 163 of a red sub-pixel SPR may extend in a vertical direction toward a circuit area CA of another red sub-pixel SPR adjacent to the one red sub-pixel SPR. The repair portion 163 may extend toward the third source electrode 142 of the third transistor 140 in the circuit area CA of the adjacent sub-pixel SP. The repair portion 163 may overlap with the third source electrode 142, and the planarization layer 114 and the passivation layer 113 are inserted between them.

[0104] If a defect occurs in the plurality of transistors and the storage capacitor 150 in the circuit area CA, a laser may be irradiated to the repair portion 163 extending toward the third source electrode 142 of the adjacent sub-pixel SP, so that the repair portion 163 and the third source electrode 142 of the adjacent sub-pixel SP may be electrically connected to each other. In this case, the third source electrode 142 may be electrically connected between the first source electrode 122 of the first transistor 120 and the first electrode 161 of the light-emitting element 160, that is, at a point where the current supplied from the first transistor 120 to the light-emitting element 160 flows. Therefore, even if a defect occurs in the driving circuit, the first transistor 120 and the repair portion 163 may be electrically connected to each other through the third source electrode 142 of the adjacent sub-pixel SP, and the two light-emitting elements 160 may be driven by one driving circuit. Meanwhile, in the accompanying drawings, the repair portion 163 is shown as overlapping with the third source electrode 142. However, the repair portion 163 may overlap with the first transistor 120, but is not limited thereto.

[0105] The repair pattern RP is disposed between the repair portion 163 and the third source electrode 142. The repair pattern RP is formed on the same layer as the first drain electrode 123, the first gate electrode 121, and the gate line GL, and is formed of the same material as the first drain electrode 123, the first gate electrode 121, and the gate line GL. The island-shaped repair pattern RP is disposed to overlap the third source electrode 142 and the repair portion 163. If a defect occurs in the driving circuit, a laser may be irradiated to the repair portion 163 so that the repair portion 163, the repair pattern RP, and the third source electrode 142 may be electrically connected to each other. In this case, a plurality of insulating layers such as a buffer layer 111, a gate insulating layer 112, a passivation layer 113, and a planarization layer 114 are disposed between the third source electrode 142 and the repair portion 163. Furthermore, the repair pattern RP may also be disposed between the third source electrode 142 and the repair portion 163, so that the third source electrode 142 and the repair portion 163 are easily connected to each other. However, the repair portion 163 and the repair pattern RP may be omitted according to design and are not limited thereto.

[0106] At the same time, a dummy pattern DP formed of the same material as the gate line GL is disposed on some of the plurality of contact holes, the high potential power line VDD, and the reference line RL. The island-shaped dummy pattern DP may be disposed to overlap the high potential power line VDD, the reference line RL, or the contact hole. The dummy pattern DP is a pattern formed in a mask design, and the arrangement of the dummy pattern DP may be changed according to the mask design, but is not limited thereto.

[0107] In the display device 100 according to an exemplary embodiment of the present disclosure, by providing the extension portion 162, the power consumption of the light-emitting element 160 can be reduced, and the color coordinate distortion can be minimized. First, the light-emitting layer 164 and the second electrode 165 are provided in the entire emission area and the circuit area CA. The light-emitting layer 164 is provided in the entire emission area EA and the circuit area CA. However, light may not be emitted from the entire light-emitting layer 164, but may be emitted only from the portion of the light-emitting layer 164 overlapping the second electrode 165 and the first electrode 161. In this case, when the first electrode 161 is provided in the entire circuit area CA, light is also emitted from the circuit area CA, and therefore, the power consumption and light amount of the light-emitting element 160 will increase. However, since the display device 100 according to the exemplary embodiment of the present disclosure is a bottom emission type, even when light is emitted from the circuit area CA, the light is blocked by the plurality of transistors and the storage capacitor 150 provided in the circuit area CA. Therefore, the light extraction efficiency is reduced. In addition, when an image is realized using light emitted from the emission area EA, undesired light is emitted from the circuit area CA, that is, light leakage may occur, resulting in color coordinate distortion. Therefore, the extension portion 162 electrically connected only to the first electrode 161 is minimally provided in the circuit area CA, thereby minimizing light emission in the circuit area CA, and reducing power consumption and color coordinate distortion of the light emitting element 160.

[0108] According to an exemplary embodiment of the present disclosure, a repair portion 163 is further provided in the display device 100, whereby when one driving circuit is defective, two light emitting elements 160 can be driven by another driving circuit. The repair portion 163 extends from the first electrode 161 provided in one sub-pixel SP among the plurality of sub-pixels SP toward the circuit area CA of another sub-pixel SP in the sub-pixel SP adjacent to the one sub-pixel SP, which emits light of the same color as the one sub-pixel SP. The repair portion 163 may extend toward the third source electrode 142 of the third transistor 140 in the circuit area CA of the adjacent sub-pixel SP and overlap with the third source electrode 142. If a defect occurs in the plurality of transistors and the storage capacitor 150 in the circuit area CA, laser light is irradiated to the repair portion 163 extending toward the third source electrode 142 of the adjacent sub-pixel SP, so that the repair portion 163 and the third source electrode 142 of the adjacent sub-pixel SP may be electrically connected to each other. In this case, since the third source electrode 142 is electrically connected to a point where the current supplied from the first transistor 120 to the light emitting element 160 flows, even if a defect occurs in the driving circuit, the repair portion 163 and the third source electrode 142 of the adjacent sub-pixel SP are electrically connected to each other, thereby driving two light emitting elements 160 with one driving circuit. Therefore, in the display device 100 according to the exemplary embodiment of the present disclosure, even if a defect occurs in the driving circuit, the corresponding light emitting elements 160 of the plurality of sub-pixels SP can be driven, thereby minimizing the reduction in light efficiency.

[0109] At the same time, the storage capacitor 150 maintains a potential difference between the first gate electrode 121 and the first source electrode 122 of the first transistor 120, thereby allowing a constant current to be supplied to the light emitting element 160. In addition, in order to supply a constant current to the light emitting element 160, it is important to maintain a voltage in the first capacitor electrode 151 connected to the first gate electrode 121 of the storage capacitor 150. However, when the first capacitor electrode 151 is disposed adjacent to the second electrode 165 of the light emitting element 160 connected to the low potential power line VSS, a parasitic capacitance between the first capacitor electrode 151 and the second electrode 165 increases, so that a data signal from the data line DL may be distorted.

[0110] In the prior art, after forming a bank at the boundary between the entire circuit region and the emission region, a second electrode is formed on the bank so that the second electrode and the first capacitor electrode can be arranged to be spaced apart from each other by a distance sufficient to reduce parasitic capacitance. Meanwhile, the display device 100 according to an exemplary embodiment of the present disclosure is a display device 100 that allows a simplified process by removing the bank. Therefore, in the display device 100, since the bank is removed, the distance between the first capacitor electrode 151 and the second electrode 165 may be shortened, thereby causing a parasitic capacitance problem.

[0111] Therefore, in the display device 100 according to the exemplary embodiment of the present disclosure, the first capacitor electrode 151 is disposed closest to the substrate 110 among the conductive components disposed on the substrate 110, thereby minimizing the parasitic capacitance between the first capacitor electrode 151 and the second electrode 165. Specifically, the distance between the first capacitor electrode 151 and the second electrode 165 can be increased by disposing the first capacitor electrode 151 closest to the substrate 110. First, on the substrate 110, the first capacitor electrode 151 is disposed together with the high potential power line VDD, the plurality of data lines DL, and the reference line RL. In addition, the buffer layer 111 and the gate insulating layer 112 are disposed on the first capacitor electrode 151, and the first source electrode 122 serving as the second capacitor electrode 152 is disposed on the gate insulating layer 112. In addition, after the passivation layer 113 and the planarization layer 114 are disposed on the first source electrode 122, the second electrode 165 can be disposed on the planarization layer 114. That is, since the plurality of insulating layers and the second capacitor electrode 152 are disposed between the first capacitor electrode 151 and the second electrode 165, the distance between the first capacitor electrode 151 and the second electrode 165 can be increased. Therefore, in the display device 100 according to the exemplary embodiment of the present disclosure, by disposing the first capacitor electrode 151 closest to the substrate 110, the parasitic capacitance between the first capacitor electrode 151 and the second electrode 165 can be minimized, and the current flowing to the light emitting element 160 can be stably maintained.

[0112] Figure 5 is an enlarged plan view of a display device according to another exemplary embodiment of the present disclosure. Figure 6 is along Figure 5 A cross-sectional view taken along line VI-VI'. Figure 5 and Figure 6 The display device 500 and Figures 1 to 4 The display device 100 is different from the display device 100 in that it further includes a plurality of color filters 570, and its other configurations are the same as those of Figures 1 to 4 The configuration of the display device 100 is substantially the same. Therefore, repeated description will be omitted.

[0113] Reference Figure 5 and Figure 6 , a plurality of color filters 570 are disposed under the planarization layer 114 and the light emitting element 160. Specifically, the plurality of color filters 570 may be disposed between the planarization layer 114 and the passivation layer 113. The plurality of color filters 570 include a first color filter 571, a second color filter 572, and a third color filter 573. For example, the first color filter 571 may be a red color filter, the second color filter 572 may be a blue color filter, and the third color filter 573 may be a green color filter.

[0114] The first color filter 571 is disposed between the planarization layer 114 and the substrate 110 in the emission area EA of one sub-pixel SP among the plurality of sub-pixels SP, and is disposed between the planarization layer 114 and the first transistor 120 in the circuit area CA of the one sub-pixel SP. For example, the first color filter 571 is a red color filter, and the first color filter 571 may be disposed between the planarization layer 114 and the substrate 110 in the emission area EA of the red sub-pixel SPR, and may be disposed between the first transistor 120 and the planarization layer 114 in the circuit area CA of the red sub-pixel SPR. In addition to the red sub-pixel SPR, the first color filter 571 may be disposed between the planarization layer 114 and the substrate 110 in the circuit area CA of each of the white sub-pixel SPW, the blue sub-pixel SPB, and the green sub-pixel SPG. Therefore, the first color filter 571 disposed in the emission area of ​​the red sub-pixel SPR of the plurality of sub-pixels SP and the circuit area CA of each of the plurality of sub-pixels SP may be formed to have a grid shape.

[0115] The second color filter 572 is disposed between the planarization layer 114 and the substrate 110 in the emission area EA of another sub-pixel SP among the plurality of sub-pixels SP, between the planarization layer 114 and the first transistor 120 in the circuit area CA of the other sub-pixel SP, and between the planarization layer 114 and the first color filter 571 in the circuit area CA of the one sub-pixel SP. For example, the second color filter 572 is a blue color filter. The second color filter 572 is disposed between the planarization layer 114 and the substrate 110 in the emission area EA of the blue sub-pixel SPB, between the first transistor 120 and the planarization layer 114 in the circuit area CA of the blue sub-pixel SPB, and between the planarization layer 114 and the first color filter 571 in the circuit area CA of the red sub-pixel SPR. In addition, except for the circuit area CA of the blue sub-pixel SPB and the red sub-pixel SPR, the second color filter 572 may be disposed between the planarization layer 114 and the substrate 110 in the circuit area CA of each of the white sub-pixel SPW and the green sub-pixel SPG. Therefore, the second color filter 572 disposed in the emission area of ​​the blue sub-pixel SPB among the plurality of sub-pixels SP and the circuit area CA of each of the plurality of sub-pixels SP may be formed to have a grid shape.

[0116] In addition, the first color filter 571 and the second color filter 572 disposed in the circuit area CA of each of the plurality of sub-pixels SP may partially overlap each other. In the respective circuit areas CA of the plurality of sub-pixels SP, the first color filter 571 may be disposed between the substrate 110 and the planarization layer 114, and the second color filter 572 may be disposed between the first color filter 571 and the planarization layer 114. Therefore, the first color filter 571 and the second color filter 572 may be disposed to overlap each other in the respective circuit areas CA of the plurality of sub-pixels SP.

[0117] Meanwhile, the first color filter 571 and the second color filter 572 are shown to be arranged to overlap each other in the corresponding circuit area CA of the plurality of sub-pixels SP, but this is merely an arrangement according to the process sequence. The types of the plurality of color filters 570 stacked on the circuit area CA are not limited thereto. For example, in the case where the third color filter 573 and the first color filter 571 are sequentially formed on the passivation layer 113, the third color filter 573 and the first color filter 571 may also be arranged and stacked in the entire corresponding circuit area CA of the plurality of sub-pixels SP.

[0118] The third color filter 573 is disposed in the emission area EA of another sub-pixel SP among the plurality of sub-pixels SP. For example, the third color filter 573 is a green color filter, and the third color filter 573 is disposed between the planarization layer 114 and the substrate 110 in the emission area EA of the green sub-pixel SPG. In this case, instead of the third color filter 573, the first color filter 571 and the second color filter 572 may be disposed in the circuit area CA of the green sub-pixel SPG. Therefore, since the third color filter 573 is disposed only in the emission area EA of the green sub-pixel SPG, the third color filter 573 may be formed to have an island shape.

[0119] In the display device 500 according to another embodiment of the present disclosure, at least a portion of the plurality of color filters 570 may be stacked in the circuit area CA, thereby minimizing the parasitic capacitance between the first capacitor electrode 151 and the second electrode 165. First, since the display device 500 according to another exemplary embodiment of the present disclosure is a bottom emission type, the light emitted from the light emitting element 160 is emitted to the bottom of the substrate 110. Therefore, the plurality of color filters 570 may be disposed between the light emitting element 160 and the substrate 110 to convert the color of the light emitted from the light emitting element 160 into various colors. In this case, each of the plurality of color filters 570 is not only disposed in the emission area EA, but also arranged in the circuit area CA, so that the separation distance between the first capacitor electrode 151 and the second electrode 165 can be increased. For example, the first color filter 571 of the plurality of color filters 570 may be disposed between the substrate 110 and the planarization layer 114, that is, between the light emitting element 160 and the storage capacitor 150, in the emission area of ​​the red sub-pixel SPR and the entire circuit area CA of the plurality of sub-pixels SP. In addition, the second color filter 572 among the plurality of color filters 570 may be disposed between the planarization layer 114 and the substrate 110 in the emission area EA of the blue sub-pixel SPB, and may be disposed between the storage capacitor 150 and the light emitting element 160 in the entire circuit area CA of the plurality of sub-pixels SP. Therefore, the first color filter 571 and the second color filter 572 are also disposed between the second electrode 165 and the storage capacitor 150 in the circuit area CA, so that the distance between the first capacitor electrode 151 and the second electrode 165 can be increased, and the parasitic capacitance between the first capacitor electrode 151 and the second electrode 165 can also be minimized. Therefore, in the display device 500 according to another exemplary embodiment of the present disclosure, at least one color filter 570 is also disposed between the second electrode 165 and the storage capacitor 150 in the circuit area CA, so that the distortion of the data signal due to the parasitic capacitance between the first capacitor electrode 151 and the second electrode 165 can be minimized.

[0120] Exemplary embodiments of the present disclosure may also be described as follows:

[0121] According to one aspect of the present disclosure, a display device includes: a substrate in which a plurality of sub-pixels are defined, each of the plurality of sub-pixels including an emission region and a circuit region; a driving transistor, which is disposed in the circuit region and includes a first gate electrode and a first source electrode disposed on the same layer; a storage capacitor, which is disposed in the circuit region and includes a first capacitor electrode electrically connected to the first gate electrode and disposed below the first gate electrode; an insulating layer, which flattens the upper portions of the driving transistor and the storage capacitor; and a light-emitting element, which is disposed on the insulating layer.

[0122] The first capacitor electrode may overlap the first source electrode, and the storage capacitor may further include a second capacitor electrode integrally formed with the first source electrode.

[0123] The second capacitor electrode may be disposed on the first capacitor electrode.

[0124] The light-emitting element may include: a first electrode, which is arranged in the emission region and on the insulating layer; a light-emitting layer, which is arranged in the entire emission region and the circuit region and on the first electrode; and a second electrode, which is arranged in the entire emission region and the circuit region and on the light-emitting layer, wherein, in the upper surface of the insulating layer, the remaining part except the part contacting the first electrode can be in contact with the light-emitting element.

[0125] The first electrodes disposed in the plurality of corresponding sub-pixels may be disposed to be spaced apart from each other, and the light emitting layer may be disposed between the first electrodes spaced apart from each other.

[0126] The light emitting element may further include an extending portion extending from the first electrode of the emission region toward the first source electrode of the circuit region.

[0127] The light emitting element may further include a repair portion extending from the first electrode provided in one of the plurality of sub-pixels toward a circuit region of another sub-pixel adjacent to the one sub-pixel.

[0128] The display device may further include a light blocking layer disposed between the substrate and the first active layer of the driving transistor, and the first capacitor electrode may be disposed on the same layer as the light blocking layer.

[0129] The display device may further include: a switching transistor, which is arranged in the circuit area and includes a second source electrode electrically connected to the first gate electrode and the first capacitor electrode; a sensing transistor, which is arranged in the circuit area and includes a third source electrode electrically connected to the driving transistor, the storage capacitor and the light-emitting element; a gate line, which is electrically connected to the second gate electrode of the switching transistor; a data line, which is electrically connected to the second drain electrode of the switching transistor; a high potential power line, which is electrically connected to the first drain electrode of the driving transistor; a sensing line, which is electrically connected to the third gate electrode of the sensing transistor; and a reference line, which is electrically connected to the third drain electrode of the sensing transistor, wherein the data line, the high potential power line and the sensing line can be arranged to extend along the column line on the same layer as the light blocking layer, wherein the gate line and the reference line can be arranged to extend in the row direction on the same layer as the first gate electrode.

[0130] The display device may also include: a first color filter, which is arranged between the insulating layer and the substrate in the emission area of ​​one sub-pixel among the multiple sub-pixels, and is arranged between the insulating layer and the driving transistor in the circuit area of ​​the one sub-pixel; and a second color filter, which is arranged between the insulating layer and the substrate in the emission area of ​​another sub-pixel among the multiple sub-pixels, and is arranged between the insulating layer and the first color filter in the circuit area of ​​the one sub-pixel.

[0131] The first capacitor electrode, the first color filter, and the second color filter may overlap each other in a circuit region of one sub-pixel.

[0132] According to another aspect of the present disclosure, a display device includes: a substrate in which a plurality of sub-pixels including red sub-pixels, green sub-pixels, blue sub-pixels and white sub-pixels are defined; a first capacitor electrode, which is arranged in each of the plurality of sub-pixels; a driving transistor, which is arranged in each of the plurality of sub-pixels and includes a first gate electrode electrically connected to the first capacitor electrode and a first source electrode arranged on the first capacitor electrode; and a light-emitting element, which includes a plurality of anodes arranged on the driving transistor in each of the plurality of sub-pixels, and a cathode and a light-emitting layer arranged on the entire plurality of sub-pixels to cover the plurality of anodes, wherein a portion of a lower surface of the light-emitting layer can be arranged on the same plane as the corresponding lower surfaces of the plurality of anodes.

[0133] Each of the multiple sub-pixels may also include: an emission area in which multiple anodes are arranged; and a circuit area in which a driving transistor and a first capacitor electrode are arranged, wherein the light-emitting element may also include an extension portion extending from each of the multiple anodes toward the driving transistor.

[0134] The light emitting element may further include a repair portion extending from an anode disposed in the red sub-pixel among the plurality of anodes toward another red sub-pixel adjacent to the red sub-pixel.

[0135] The display device may also include: a red filter, which is arranged in the emission area of ​​the red sub-pixel in the emission area and in the circuit area of ​​each of the multiple sub-pixels; a blue filter, which is arranged in the emission area of ​​the blue sub-pixel in the emission area and in the circuit area of ​​each of the multiple sub-pixels; and a green filter, which is arranged in the emission area of ​​the green sub-pixel in the emission area, wherein the red filter and the blue filter may overlap each other in the circuit area of ​​each of the multiple sub-pixels.

[0136] The red color filter and the blue color filter may be formed to have a mesh shape, wherein the green color filter may be formed to have an island shape.

[0137] The first capacitor electrode and the first source electrode may constitute a storage capacitor, and the first source electrode, a red color filter, and a blue color filter may be disposed between the first capacitor electrode and the cathode.

[0138] The first capacitor electrode may be disposed closest to the substrate among conductive members disposed on the substrate.

[0139] Although the exemplary embodiments of the present disclosure have been described in detail with reference to the accompanying drawings, the present disclosure is not limited thereto, and the present disclosure can be implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, the exemplary embodiments of the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above exemplary embodiments are illustrative in all aspects and do not limit the present disclosure. The scope of protection of the present disclosure should be interpreted based on the attached claims, and all technical concepts in their equivalent scope should be interpreted as falling within the scope of the present disclosure.

Claims

1. A display device, comprising: a substrate in which a plurality of sub-pixels are defined, and each sub-pixel includes an emission region and a circuit region; a driving transistor disposed in the circuit region and including a first gate electrode and a first source electrode disposed on the same layer; a storage capacitor disposed in the circuit region and comprising a first capacitor electrode electrically connected to the first gate electrode and disposed below the first gate electrode; an insulating layer that planarizes upper portions of the driving transistor and the storage capacitor; as well as a light emitting element, wherein the light emitting element is disposed on the insulating layer, Wherein, the light emitting element comprises: A first electrode is disposed in the emission region and on the insulating layer; a light-emitting layer, covering the entire emission region and the circuit region and disposed on the first electrode; and A second electrode covers the entire emission area and the circuit area and is disposed on the light-emitting layer, The portion of the upper surface of the insulating layer that is not in contact with the first electrode is in contact with the light emitting element.

2. The display device according to claim 1, wherein: The first capacitor electrode overlaps the first source electrode, and The storage capacitor also includes a second capacitor electrode formed integrally with the first source electrode.

3. The display device according to claim 2, wherein: The second capacitor electrode is disposed on the first capacitor electrode.

4. The display device according to claim 1, wherein: The first electrodes disposed in the plurality of sub-pixels are spaced apart from each other, and The light emitting layer is disposed between the first electrodes that are spaced apart from each other.

5. The display device according to claim 1, wherein: The light emitting element further includes an extension portion extending from the first electrode of the emission region toward the first source electrode of the circuit region.

6. The display device according to claim 1, wherein: The light emitting element further includes a repair portion extending from the first electrode provided in one of the plurality of sub-pixels toward the circuit region of another sub-pixel adjacent to the one sub-pixel.

7. The display device according to claim 1, further comprising: a light blocking layer disposed between the substrate and the first active layer of the driving transistor, and A first capacitor electrode is provided on the same layer as the light blocking layer.

8. The display device according to claim 7, further comprising: a switching transistor disposed in the circuit region and including a second source electrode electrically connected to the first gate electrode and the first capacitor electrode; a sensing transistor disposed in the circuit region and including a third source electrode electrically connected to the driving transistor, the storage capacitor, and the light emitting element; a gate line electrically connected to a second gate electrode of the switching transistor; a data line electrically connected to the second drain electrode of the switch transistor; a high potential power line electrically connected to the first drain electrode of the driving transistor; a sensing line electrically connected to a third gate electrode of the sensing transistor; as well as a reference line electrically connected to a third drain electrode of the sensing transistor, wherein the data line, the high potential power line and the sensing line are arranged to extend along the column line on the same layer as the light blocking layer, and The gate line and the reference line are arranged to extend along a row direction on the same layer as the first gate electrode.

9. The display device according to claim 1, further comprising: a first color filter disposed between the insulating layer and the substrate in the emission region of one of the plurality of sub-pixels, and disposed between the insulating layer and the driving transistor in the circuit region of the one sub-pixel; as well as A second color filter is disposed between the insulating layer and the substrate in the emission region of another sub-pixel among the plurality of sub-pixels, and between the insulating layer and the first color filter in the circuit region of the one sub-pixel.

10. The display device according to claim 9, wherein: The first capacitor electrode, the first color filter, and the second color filter overlap each other in the circuit region of the one sub-pixel.

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