A wide input and output range amplifier circuit

Abstract

The present invention discloses a wide input and output range amplifier circuit. The circuit is powered by a 1.5V power supply. When working, the input voltage range is 0.2V-1.2V, and it has a high load driving capability. The circuit of the present invention includes a differential amplifier, an output stage, and a discharge circuit; the differential amplifier is composed of two groups of input pairs of tubes with a zero threshold and a normal threshold. According to different input voltages, the input pair of tubes of the amplifier is selected to ensure the gain within the input voltage range, and the output voltage OUTP is connected to the differential amplifier input terminal IN_N, and the difference between IN_P and OUP is amplified so that the OUTP voltage output reaches the target potential. The output stage is a common source amplifier circuit, the purpose of which is to enhance the driving capability of the output signal of the differential amplifier, and it can drive a capacitive load of the order of 1 nanofarad, and it has a strong voltage pull-up capability and output range. The discharge circuit can quickly discharge the circuit load and quickly establish the output voltage OUTP.

Description

Technical Field

[0001] The present invention relates to the field of low supply voltage operational amplifiers, and in particular to an amplifier circuit with wide input range and output range. Background Art

[0002] Operational amplifiers are frequently used modules in integrated circuit design and are the cornerstone of analog integrated circuits. Various analog modules such as bandgap references, current sources, and charge pumps are inseparable from operational amplifiers. As the system's requirements for chip power consumption become increasingly stringent, the chip power supply voltage is gradually reduced, and 1.5V power supply and 1.2V power supply have become the mainstream of chip power supply. Under 1.5V power supply, operational amplifiers using traditional NMOS or PMOS input pairs perform well at ground level or near the power supply, but when the input voltage is near half of the power supply voltage, the input pair of the operational amplifier can easily enter the linear region, greatly reducing the performance of the amplifier. At the same time, if the output stage is too complex, it will limit the swing of the output voltage. For these reasons, how to design an amplifier circuit with a wide input range and output range becomes a problem. It not only needs to provide a large input range and output range, but also requires sufficient dynamic response capability and relatively strong pull-up capability when driving the load. Summary of the invention

[0003] In order to realize the amplifier required above, the present invention provides an amplifier circuit with a wide input range and output range, which uses zero-threshold transistors and ordinary threshold transistors to form two groups of input pairs of tubes. According to the input range of voltage, the input pairs of tubes for the operational amplifier are selected, so that the amplifier circuit can work normally within a larger input voltage. At the same time, the two groups of differential input pairs of tubes share the current source, output stage and discharge circuit, which reduces the power consumption of the amplifier circuit and saves chip area. The amplifier circuit contains a high-speed discharge path. When the output stage drives a large load, the amplifier circuit can discharge quickly and establish quickly, so that the response speed of the entire amplifier circuit is guaranteed.

[0004] Reference Figure 1 And attached Figure 2 The circuit of the present invention is composed of a differential amplifier, an output stage and a discharge circuit.

[0005] The differential amplifier circuit is composed of two groups of input pairs of tubes with different thresholds. The two groups of tubes work independently and do not interfere with each other. According to different input voltages, different input pairs of tubes are selected to make the amplifier circuit have a wider input range and output range. At the same time, the difference between the external input reference voltage IN_P and the output voltage OUTP is amplified, so as to adjust the output voltage OUTP of the circuit to reach the target value.

[0006] The output stage circuit is a common source amplifier circuit, which ensures the overall gain of the amplifier circuit and has a high transient response speed and driving capability. The common source stage, as an output stage, has a large voltage output range and can cooperate with the input stage of the differential amplifier.

[0007] The discharge circuit has a fast discharge function. When the amplifier circuit is not working, the output OUTP is clamped at VDD12. When the amplifier circuit is working and the PST signal is low, the output load is first slowly discharged through the current source I2; after the PST signal is valid, the output OUTP is quickly discharged through the transistor, which enables the output voltage of the amplifier circuit to quickly establish the target potential.

[0008] As can be seen from the above, the advantages of the present invention are that while meeting the requirements of high-precision voltage conversion, the dual input structure with different threshold voltages and common source output are adopted, which increases the input range and output range of the amplifier circuit and has a good transient response speed. The two sets of input pairs use the same common source drive, discharge circuit and compensation circuit, which reduces the power consumption of the amplifier, saves the layout area, and improves the integration of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 This is a block diagram of a wide input range amplifier;

[0010] Figure 2 The circuit schematic diagram of the wide input range amplifier of the present invention; DETAILED DESCRIPTION

[0011] The technical solution of the present invention is further described below in conjunction with the accompanying drawings.

[0012] Figure 1 The structure block diagram of the wide input range and output range amplifier of the present invention shows the basic structure of the circuit, which is composed of a differential amplifier, an output stage, and a discharge circuit. In the non-working state, the output voltage OUTP is clamped to VDD12; in the initial stage of normal operation, the operational amplifier and the discharge circuit work normally, the output stage does not work, and OUTP is quickly pulled down; in normal operation, the operational amplifier and the output stage work normally, the discharge circuit does not work, and the input reference voltage IN_P and the output voltage OUTP pass through the error amplifier to amplify and adjust the difference between the two, and finally complete the control of the output voltage. Since the differential amplifier uses two groups of input pairs of tubes with different electrical characteristics, which group of tubes works can be determined according to the input voltage value, so that the operational amplifier has a wider input voltage range, and the output stage and the discharge circuit are shared at the same time, which effectively saves the layout area and reduces the chip power consumption.

[0013] Further explanation: Figure 2As shown, the error amplifier is composed of a current source I1, transistors NM1, NM2, NM3, NM4, NM5, NM6, NM7, NM8, PM1, PM2, and PM3. The source terminals of transistors NM1, NM2, NM3, and NM4 are connected to the current source I1 to form a selection of two sets of differential input structures. According to different input voltages, the left differential input or the right differential input is selected to work. The source terminals of transistors NM5, NM6, NM7, and NM8 are respectively connected to the drain terminals of NM1, NM2, NM3, and NM4 to form two sets of differential input structures. NM5 and NM6 are zero threshold transistors, and NM7 and NM8 are normal threshold transistors. When the input voltage is less than 0.6V, NM1 and NM2 are turned on, NM3 and NM4 are turned off, the left differential input works, and the right differential input is turned off. Since NM5 and NM6 are zero-threshold transistors, they can work in the saturation region when the input voltage is 0.2V and 0.6V, and the differential amplifier can provide a higher gain, but when the input voltage is 0.8V, NM5 and NM6 will have the risk of entering the linear region under some conditions; when the input voltage is higher than 0.6V, NM1 and NM2 are turned off, NM3 and NM4 are turned on, and the right differential input works. The differential inputs on both sides work independently and do not interfere with each other. The drains of NM5 and NM7 are connected to the drains of PM1 and PM2; the drains of NM6 and NM8 are connected to the drain of PM3, forming a dual-input single-output differential amplifier. The output of the differential amplifier is connected to the output stage circuit. The error amplifier circuit has a large input voltage range and provides sufficient gain while providing a low offset voltage, thereby ensuring the conversion accuracy of the entire voltage regulator.

[0014] The output stage circuit is composed of a transistor PM4 and a current source I2. The source of the transistor PM4 is connected to the power supply; the drain of the transistor PM4 is connected to the current source I2; and the gate of the transistor PM4 is connected to the output end of the differential amplifier. This part of the circuit forms a common source amplifier, which ensures the overall gain of the amplifier circuit, so that the amplifier has a higher transient response speed and driving capability. At the same time, the output of the output stage is connected to the discharge circuit.

[0015] refer to Figure 2, the discharge circuit is composed of transistors PM4, PM6, NM9, NM10 and digital logic I10, I11, I12. The source terminal of PM5 is connected to the power supply VDD12; the drain terminal is connected to the amplifier output stage; the gate terminal is connected to the enable signal EN1. When the EN1 signal is equal to zero, the amplifier stops working and the output voltage of the output stage is clamped to VDD12V. The source terminal of NM10 is connected to VSS, the gate terminal is connected to the discharge control signal PST, and the drain terminal is connected to the source terminal of transistor NM9; the drain terminal and the gate terminal of transistor NM9 are diode-connected and then connected to the output of the output stage; the source terminal of transistor PM3 is connected to the power supply, the gate terminal is connected to the combination logic output EN2 of EN1 and PST signals, and the drain terminal is connected to the output of the output stage. After the enable signal EN1 is high, when the PST signal is low, the output stage load is slowly discharged through the current source I2; when the PST signal is high, NM10 is turned on, the output stage load is quickly discharged, and at the same time, the EN2 signal turns on PM3 and turns off transistor PM4 to prevent the generation of through current.

[0016] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the design principles and technical solutions of the present invention are included in the protection scope of the present invention.

Claims

1. A wide input and output range amplifier circuit, characterized in that, It includes a differential amplifier, an output stage and a discharge circuit, wherein: The differential amplifier: the input reference voltage is connected to the IN_P terminal of the differential amplifier, the output voltage OUTP is connected to the IN_N terminal of the differential amplifier, and its output signal is connected to the output stage. The differential amplifier is composed of a current source I1, transistors NM1, NM2, NM3, NM4, NM5, NM6, NM7, NM8, PM1, PM2, and PM3. The source terminals of the transistors NM1, NM2, NM3, and NM4 are connected to the current source I1 to form a selection of two groups of differential input structures. According to different input voltages, the left differential input or the right differential input is selected to work; the source terminals of the transistors NM5, NM6, NM7, and NM8 are connected to the drain terminals of NM1, NM2, NM3, and NM4 respectively. The two ends are connected together to form two sets of differential input structures; NM5 and NM6 are zero threshold transistors, and NM7 and NM8 are normal threshold transistors; when the input voltage is less than 0.6V, NM1 and NM2 are turned on, NM3 and NM4 are turned off, the left differential input works, and the right differential input is turned off; when the input voltage is higher than 0.6V, NM1 and NM2 are turned off, NM3 and NM4 are turned on, and the right differential input works, and the differential inputs on both sides work independently without interfering with each other; the drains of NM5 and NM7 are connected together with the drains of PM1 and PM2; the drains of NM6 and NM8 are connected together with the drain of PM3 to form a dual-input single-output differential amplifier, and the output of the differential amplifier is connected to the output stage circuit; The output stage: one end receives the output signal of the differential amplifier, and the other end is connected to the discharge circuit; the output stage adopts a common source structure, and the output stage is composed of a transistor PM4 and a current source I2, wherein the source of the transistor PM4 is connected to the power supply; the drain of the transistor PM4 is connected to the current source I2, forming a common source structure; the gate of the transistor PM4 is connected to the output end of the differential amplifier, and the output of the output stage is connected to the discharge circuit; The discharge circuit: the discharge circuit is connected to the output stage. When the differential amplifier is not working, the output voltage OUTP is clamped to the power supply VDD12. When the differential amplifier is working, it is first slowly discharged through the tail current of the output stage; when the discharge circuit is working, the output voltage OUTP is quickly discharged and then quickly stabilized at the target value. The source end of the discharge circuit PM5 is connected to the power supply VDD12; the drain end is connected to the output stage of the differential amplifier; the gate end is connected to the enable signal EN1; when the EN1 signal is equal to zero, the differential amplifier stops working, and the output voltage of the output stage is clamped to VDD12. The source end of NM9 is connected to VSS, and the gate end is connected to The discharge control signal PST is received, and the drain end is connected to the source end of the transistor NM10; the drain end and the gate end of the transistor NM10 are diode-connected, and then connected to the output of the output stage; the source end of the transistor PM3 is connected to the power supply VDD15, the gate end is connected to the combination logic output EN2 of the EN1 and PST signals, and the drain end is connected to the output of the output stage. After the enable signal EN1 is high, when the PST signal is low, the output stage connection is slowly discharged through the current source I2; when the PST signal is high, NM9 is turned on, and the output stage load is quickly discharged. At the same time, the EN2 signal turns on PM3 and turns off the transistor PM4 to prevent the generation of a through current.

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