Semiconductor structure and method for forming the same

Abstract

The present invention relates to a semiconductor structure and a method for forming the same, the method comprising: providing a substrate; forming a patterned sacrificial layer on the surface of the substrate; forming a first sidewall on the sidewall surface of the sacrificial layer; removing the sacrificial layer; filling a second sidewall between adjacent first sidewalls, the top of the second sidewall being lower than the top of the first sidewall; etching the first sidewall to the surface of the substrate to form a plurality of discrete second sidewalls; etching the substrate using the second sidewall as a mask. The above-mentioned method can improve the accuracy of the etching pattern formed after etching the substrate.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] As the size of semiconductor devices continues to decrease, in order to improve the integration of devices, a double patterning process has been proposed. Double patterning technology only requires a small change to the existing lithography infrastructure to effectively fill the gap in lithography technology for smaller nodes and improve the minimum pitch between adjacent semiconductor patterns, thereby obtaining patterns with smaller feature sizes and higher density. The principle of double patterning technology is to decompose a set of high-density patterns into two sets of discrete, lower-density patterns, and then prepare them on the wafer. The double patterning technologies in the prior art mainly include: self-aligned double patterning (SADP: Self-Aligned Double-Patterning) and secondary lithography and etching process (LELE: Litho-Eth-Litho-Eth). Since the self-aligned double patterning process (SADP) is simpler and less expensive, the self-aligned double patterning process is often used in the formation process of semiconductor devices.

[0003] In the prior art double patterning method, please refer to Figure 1a , a patterned sacrificial layer 102 is formed on the target layer 101 on the surface of the substrate 100, and a sidewall 103 is formed on the sidewall surface of the sacrificial layer 102; please refer to Figure 1b , remove the sacrificial layer 102, and obtain multiple patterns. Subsequently, the sidewall 103 is used as a mask to continue etching downward to transfer the pattern to the substrate 100. In the process of multiple pattern support, the sidewall is usually formed by deposition and etching processes, and an arc morphology is formed at the corner of the sidewall on one side of the top of the sidewall, so that the sidewall morphology on both sides of the sidewall is different. In the subsequent pattern transfer process, the pattern 104a and the pattern 104b on both sides of the sidewall layer have different morphological sizes, and have different effects on the etching ions, which will produce different etching load effects, resulting in distortion of the pattern transfer, causing critical dimension misalignment and even pattern bridging problems.

[0004] How to improve the quality of graphics in double patterning process is a problem that needs to be solved urgently. Summary of the invention

[0005] The technical problem to be solved by the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the pattern quality of the double patterning process.

[0006] In order to solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate; forming a patterned sacrificial layer on the surface of the substrate; forming a first side wall on the side wall surface of the sacrificial layer; removing the sacrificial layer; filling a second side wall between adjacent first side walls, wherein the top of the second side wall is lower than the top of the first side wall; etching the first side wall to the surface of the substrate to form a plurality of discrete second side walls; and etching the substrate using the second side wall as a mask.

[0007] Optionally, the top of the second side wall is flat.

[0008] Optionally, the first sidewall spacer is etched by a selective etching process or an anisotropic etching process.

[0009] Optionally, when etching the first side wall, an etching selectivity ratio between the first side wall and the second side wall is greater than 5:1.

[0010] Optionally, the first sidewall spacer includes a first sub-sidewall spacer and a second sub-sidewall spacer located on top of the first sub-sidewall spacer, and the width uniformity of the first sub-sidewall spacer is greater than the width uniformity of the second sub-sidewall spacer.

[0011] Optionally, a side wall of the first side wall away from the sacrificial layer is arc-shaped; and a curvature of the arc-shaped side wall of the second sub-side wall is greater than a curvature of the arc-shaped side wall of the first sub-side wall.

[0012] Optionally, the height of the second side wall is equal to or less than the height of the first sub-side wall.

[0013] Optionally, the intervals between adjacent second side walls are the same.

[0014] Optionally, the substrate includes: a substrate and a target layer located on the surface of the substrate; the method of etching the substrate using the second side wall as a mask includes: etching the target layer using the second side wall as a mask to form a patterned target layer; removing the second side wall, etching the substrate using the patterned target layer as a mask, and forming an etched pattern in the substrate.

[0015] Optionally, the method for forming the first side wall includes: forming a first side wall material layer covering the sacrificial layer and the surface of the substrate; etching and removing the first side wall material layer covering the top of the sacrificial layer and the surface of the substrate along a direction perpendicular to the surface of the substrate to form a first side wall covering the side wall of the sacrificial layer.

[0016] Optionally, the method for forming the second side wall includes: forming a second side wall material layer, wherein the second side wall material layer fills the gap between adjacent first side walls and has a surface higher than the top of the first side wall; flattening the surface of the second side wall material layer; etching the second side wall material layer so that the height of the second side wall material layer decreases to form a second side wall whose top is lower than the top of the first side wall.

[0017] Optionally, a selective etching process is used to remove the sacrificial layer.

[0018] In order to solve the above problems, the technical solution of the present invention further provides a semiconductor structure, comprising: a substrate; and a plurality of discrete sidewalls located on the surface of the substrate, wherein the tops of the sidewalls are flat and the openings between adjacent sidewalls have the same shape and size.

[0019] Optionally, the side walls have the same width at different heights.

[0020] Optionally, in a direction perpendicular to the length of the side wall, a cross-sectional shape of the side wall is a rectangle.

[0021] Optionally, the side wall includes an independent side wall and a composite side wall, the independent side wall and the composite side wall are spaced apart, and the composite side wall includes a second side wall whose side wall is recessed inwardly, and a first side wall filling the recessed side wall of the second side wall.

[0022] The semiconductor structure and the method for forming the same of the present invention adopt a multiple patterning method to obtain a pattern formed by a first sidewall on the surface of a substrate, and then fill a second sidewall between the first sidewalls, with the top of the second sidewall being located next to the top of the first sidewall. By removing the first sidewall and the pattern between the second sidewalls, the etching load effect in the subsequent pattern transfer process can be reduced due to the consistent morphology on both sides of the second sidewall, thereby forming an etched pattern with uniform morphology and accurate size in the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1a to Figure 1b , is a schematic structural diagram of a semiconductor structure formed by a double patterning process of the prior art of the present invention;

[0024] Figures 2 to 9 A schematic diagram of a semiconductor structure formed by a double patterning process according to a specific embodiment of the present invention;

[0025] Figure 10 to Figure 11 It is a schematic structural diagram of a semiconductor structure formed by a double patterning process according to another specific embodiment of the present invention. DETAILED DESCRIPTION

[0026] The specific implementation manner of the semiconductor structure and the method for forming the same provided by the present invention will be described in detail below with reference to the accompanying drawings.

[0027] Please refer to Figure 2 , providing a substrate 200, and forming a patterned sacrificial layer 210 on the surface of the substrate 200.

[0028] In this specific embodiment, the base 200 includes a substrate 201 and a target layer 202 located on the surface of the substrate 201 .

[0029] The substrate 201 is made of semiconductor materials such as silicon, germanium, silicon germanium, silicon carbide or indium gallium; the substrate 201 may also be a silicon on insulator substrate, a germanium on insulator substrate or a silicon germanium on insulator substrate. In this specific embodiment, the substrate 201 is a single crystal silicon substrate.

[0030] Semiconductor devices such as MOS transistors, resistors, capacitors or inductors may also be formed in the substrate 201 .

[0031] The target layer 202 may be a mask layer, a device layer, a dielectric layer, or any other material layer that needs to be patterned.

[0032] In other specific implementations, the substrate 201 may also be a multi-layer stacked structure, including at least two material layers of a semiconductor layer, a device layer, a dielectric layer, and a metal layer stacked in sequence.

[0033] In other specific implementations, the base 200 may also be a single-layer structure, including only a substrate 201 , and the sacrificial layer 210 is directly located on the surface of the substrate 201 .

[0034] The sacrificial layer 210 is a material that is easy to remove. The material of the sacrificial layer 210 includes silicon oxide, silicon nitride, silicon oxynitride, amorphous carbon, organic dielectric material, organic anti-reflective material, etc.

[0035] In this specific embodiment, the material of the sacrificial layer 210 is amorphous carbon, and the method for forming the patterned sacrificial layer 210 includes: using a spin coating process to form a sacrificial material layer covering the surface of the target layer 202; patterning the sacrificial material layer, and setting the spacing between the sacrificial layers 210 according to the size of the pattern that needs to be finally formed in the substrate. In this specific embodiment, the spacing between adjacent sacrificial layers 210 is the same.

[0036] Please refer to Figure 3 , forming a first spacer material layer 300 covering the sacrificial layer 210 and the surface of the substrate 200 .

[0037] The material of the first side wall material layer 300 is different from the material of the sacrificial layer 20, and the material of the first side wall material layer 300 is different from the surface material of the substrate 200. In this specific embodiment, it is different from the material of the target layer 202, so that the subsequent removal of the sacrificial layer 210 will not have an adverse effect on the first side wall formed by the first side wall material layer 300, and the subsequent removal of the first side wall will not cause damage to the substrate 200.

[0038] The material of the first spacer material layer 300 includes at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, silicon carbonitride, silicon carbon oxynitride or boron nitride. In this specific embodiment, the material of the first spacer material layer 300 is silicon nitride. The first spacer material layer 300 can be formed by a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process. In this specific embodiment, the first spacer material layer 300 is formed by an atomic layer deposition process, so that the first spacer material layer 300 has a high step coverage and the deposition thickness of the first spacer material layer 300 can be strictly controlled, so that the thickness of the first spacer material layer 300 is uniform.

[0039] Please refer to Figure 4 , along a direction perpendicular to the surface of the substrate 200, the first spacer material layer 300 covering the top of the sacrificial layer 210 and the surface of the substrate 200 is etched away (please refer to Figure 3 ), forming a first sidewall spacer 400 covering the sidewall of the sacrificial layer 210.

[0040] The first spacer material layer 300 is etched by an anisotropic etching process. The anisotropic etching process may be a plasma etching process, which has high etching selectivity and anisotropy. The anisotropic etching process is an etching process in a direction perpendicular to the surface of the substrate 200, and the first spacer material layer located on the side wall of the sacrificial layer 210 is substantially not laterally etched. Therefore, the first spacer material layer covering the side wall of the sacrificial layer 210 is finally retained as the first spacer 400.

[0041] Since the surface of the first spacer material layer 300 covering the top of the sacrificial layer 210 and the top corner of the side wall is arc-shaped, due to the transfer of the pattern, the top of the first spacer 400 formed by etching the first spacer material layer 300 will also have an arc-shaped side wall.

[0042] The first sidewall spacer 400 includes a first sub-sidewall spacer 401 located on the surface of the substrate 200 and a second sub-sidewall spacer 402 located on the top of the first sub-sidewall spacer 401. The width uniformity of the first sub-sidewall spacer 401 is greater than the width uniformity of the second sub-sidewall spacer 402. The width of the sidewall spacer is the thickness of the sidewall spacer covering the sidewall of the sacrificial layer.

[0043] In this specific implementation, the second sub-sidewall 402 is a section of the top of the first sidewall 400 with an arc-shaped sidewall; and the cross-sectional shape of the first sub-sidewall 401 along the direction perpendicular to the length of the first sidewall 400 is a rectangle with the same width at different heights.

[0044] In other specific embodiments, the first sub-sidewall 401 and the second sub-sidewall 402 may both have curved sidewalls, and the curvature of the curved sidewall of the first sub-sidewall 401 is smaller than the curvature of the curved sidewall of the second sub-sidewall 402. Therefore, the width uniformity of the first sub-sidewall 401 is greater than the width uniformity of the second sub-sidewall 402.

[0045] Please refer to Figure 5 , remove the sacrificial layer 210 (please refer to Figure 4 ).

[0046] The sacrificial layer 210 is removed by a selective etching process. Since the material of the sacrificial layer 210 is different from that of the first sidewall 400, the first sidewall 400 is substantially not damaged during the process of removing the sacrificial layer 210. The selective etching process may be a wet etching process, an ashing process, or a dry etching process. In this specific embodiment, the material of the sacrificial layer 210 is amorphous carbon, and the sacrificial layer 210 may be removed by an ashing process to minimize the impact on the substrate 200 and the first sidewall 400.

[0047] After removing the sacrificial layer 210 , an additional cleaning process may be performed to remove material residues from etching the first spacer material layer 300 and the sacrificial layer 210 , thereby forming a complete and clean multi-pattern composed of the first spacer 400 .

[0048] Please refer to Figure 6 , a second sidewall 600 is filled between adjacent first sidewalls 400 , and a top of the second sidewall 600 is lower than a top of the first sidewall 400 .

[0049] The material of the second sidewall 600 is different from that of the first sidewall 400, so that the second sidewall 600 will not be affected when the first sidewall 400 is removed later. The material of the second sidewall 600 includes at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, silicon carbonitride, silicon carbon oxynitride or boron nitride. In this specific embodiment, the material of the second sidewall 600 is silicon oxide.

[0050] The top of the second sidewall 600 is lower than the top of the first sidewall 400. As the first sidewall 400 is closer to the top, the curvature of the sidewall is greater, and the gap between the arc-shaped sidewalls of two adjacent first sidewalls 400 and the gap between the vertical sidewalls are greater. The top of the second sidewall 600 is lower than the top of the first sidewall 400, so that the width of the gap between adjacent second sidewalls 600 varies less with height, and the difference between the graphic morphologies on both sides of the second sidewall 600 is reduced after the first sidewall 400 is removed, thereby reducing the subsequent etching load effect.

[0051] In this specific embodiment, the top of the second sidewall 600 is flat. Preferably, the height of the second sidewall 600 is less than the height of the first sub-sidewall 401, so that the top of the second sidewall 600 is lower than the top of the first sub-sidewall 401. Since the width of the first sub-sidewall 401 is uniform and the cross-section is rectangular, the cross-section of the second sidewall 600 along the vertical length direction is also rectangular. And since the widths of the first sub-sidewalls 401 are the same, after removing the first sub-sidewall 401, the spacing between adjacent second sidewalls 600 is the same.

[0052] The method for forming the second side wall 600 includes: forming a second side wall material layer, wherein the second side wall material layer fills the gap between adjacent first side walls 400 and has a surface higher than the top of the first side wall 400; planarizing the surface of the second side wall material layer; and etching the second side wall material layer so that the height of the second side wall material layer decreases to form a second side wall whose top is lower than the top of the first side wall 400.

[0053] In other specific implementations, spin coating or other deposition processes may be used to directly form the second sidewall 600 lower than the first sidewall 400 on the surface of the substrate 200 .

[0054] Please refer to Figure 7 , etching the first sidewall 400 (please refer to Figure 6 ) to the surface of the substrate 200 to form a plurality of discrete second sidewalls 600.

[0055] When the first sidewall 400 is etched by a selective etching process, the etching selectivity ratio of the first sidewall 400 to the second sidewall 600 is greater than 5:1, thereby substantially not affecting the second sidewall 600 and ensuring that the morphology of the retained second sidewall 600 does not change.

[0056] The selective etching process used to remove the first sidewall 400 may be a wet etching process. In this specific embodiment, the material of the first sidewall 400 is silicon nitride, and a phosphoric acid solution, which is a wet etching solution with a high etching selectivity to the silicon nitride, may be used to wet-etch the first sidewall 400 to remove the first sidewall 400. In other specific embodiments, a dry etching process with a high etching selectivity to the first sidewall 400 may also be used for anisotropic etching. Those skilled in the art may select a suitable etching process to etch the first sidewall 400 without substantially affecting the second sidewall 600 and the substrate 200, which is not limited here.

[0057] In this specific embodiment, the spacing between the openings 701 between adjacent second side walls 600 is the same. When the substrate 200 is subsequently etched using the second side walls 600 as a mask to transfer the pattern, there will be no etching load effect due to the different spacing. Therefore, the accuracy of the pattern transfer can be ensured and the size uniformity of the formed pattern can be improved.

[0058] Please refer to Figure 8 , using the second sidewall 600 as a mask, etching the target layer 202 .

[0059] In this specific embodiment, the base 200 includes a substrate 201 and a target layer 202 located on the surface of the substrate 201 (see Figure 7 ). The target layer 202 is etched using the second sidewall 600 as a mask to form a patterned target layer 202a.

[0060] The target layer 202 may be etched by an anisotropic etching process, and the preferred dry etching process is a plasma etching process. The material of the target layer 202 is amorphous carbon, and an oxygen-containing gas may be used as a plasma source to generate oxygen plasma to etch the target layer 202. In other specific embodiments, those skilled in the art may select a suitable etching process according to the material of the target layer 202.

[0061] Since the sizes of the patterns on both sides of the second sidewall 600 are consistent, the etching load effect can be effectively reduced, thereby ensuring the accuracy of the etching pattern formed in the patterned target layer 202a.

[0062] In this specific implementation, the target layer 202 is a mask layer for forming a mask pattern for etching the substrate 201 .

[0063] Please refer to Fig. 9 , remove the second side wall 600 (please refer to Figure 8 ), using the patterned target layer 202a as a mask, etching the substrate 201 to form an etched pattern 901 in the substrate 201.

[0064] Since the second sidewall 600 as a mask will be bombarded by plasma during the process of etching to form the patterned target layer 202a, there will be a certain degree of damage and consumption. In order to improve the accuracy of subsequent pattern transfer, in this specific embodiment, the second sidewall 600 is removed before etching the substrate 201. The second sidewall 600 can be removed by a selective etching process to avoid affecting the patterned target layer 202a and the substrate 201. In this specific embodiment, the material of the second sidewall 600 is silicon oxide, and the second sidewall 600 can be wet-etched by a hydrofluoric acid solution. In other specific embodiments, the second sidewall 600 can also be removed by a dry etching process.

[0065] After removing the second sidewall 600, the substrate 201 is etched using the patterned target layer 202a as a mask. The pattern in the patterned target layer 202a is transferred to the substrate 201 to form an etched pattern 901. The width of the etched pattern 901 corresponds to the width of the second sidewall 600. Therefore, the width of the etched pattern 901 can be accurately controlled by controlling the width of the formed second sidewall 600.

[0066] Please refer to Figure 10 to Figure 11 , which is a structural schematic diagram of the formation process of a semiconductor structure according to another specific embodiment of the present invention.

[0067] Please refer to Fig.10 In this specific embodiment, one side of the first sidewall 1000 formed on the surface of the substrate 200 is a vertical sidewall, and the other side is a curved sidewall. The first sidewall 1000 includes a first sub-sidewall 1001 and a second sub-sidewall 1002 located above the first sub-sidewall 1001. The curvature of the curved sidewall of the second sub-sidewall 1002 is greater than the curvature of the curved sidewall of the first sub-sidewall 1001, so that the width uniformity of the second sub-sidewall 1002 is less than the width uniformity of the second sub-sidewall 1002.

[0068] The second sidewall is filled between the first sidewalls 1000. Since the two sides of the first sidewall 1000 have different morphologies, the second sidewall 1010 also has two different morphologies, including a second sidewall 1011 and a second sidewall 1012. The cross-section of the second sidewall 1012 along the length direction is a rectangle. In the cross-section of the second sidewall 1011 along the length direction, the sidewalls on both sides are arc-shaped and concave toward the inside of the second sidewall 1011.

[0069] Please refer to Fig.11 , along a direction perpendicular to the surface of the substrate 200 , an anisotropic etching process is used to etch the first sidewall 1000 to the surface of the substrate 200 to form an opening 1101 , wherein the width of the opening 1101 is uniform and has vertical sidewalls.

[0070] Since the second sidewall 1011 has an inwardly concave sidewall and the top width is greater than the bottom width, during the etching of the first sidewall 1000, part of the first sidewall residue 1102 is located at the concave sidewall of the second sidewall 1011 and is not etched.

[0071] One side of the opening 1101 is a second sidewall 1012 with a rectangular cross section, and the other side is a composite sidewall formed by the second sidewall 1011 and the first sidewall residue 1102 .

[0072] Subsequently, etching is performed downward along the opening 1101 to transfer the pattern of the opening 1101 into the substrate 200 .

[0073] The method for forming the semiconductor structure can reduce the etching load effect of the double patterning process and improve the morphology uniformity and dimensional accuracy of the etched pattern formed in the substrate.

[0074] A specific embodiment of the present invention further provides a semiconductor structure.

[0075] Please refer to Figure 7 , which is a schematic structural diagram of a semiconductor structure according to a specific embodiment of the present invention.

[0076] The semiconductor structure includes: a substrate 200; and a plurality of separate second sidewall spacers 600 located on the surface of the substrate 200. The tops of the second sidewall spacers 600 are flat, and the shapes and sizes of the openings 701 between adjacent second sidewall spacers 600 are the same.

[0077] The width of the second side wall 600 at different heights is the same, and the cross-sectional shape of the second side wall 600 in a direction perpendicular to the length of the second side wall 600 is a rectangle.

[0078] The second side wall 600 is formed by the method in the above-mentioned specific embodiment, so that the graphic morphology between the second side walls 600 is uniform and the size is accurate. Subsequently, the substrate 200 is etched using the second side wall 600 as a mask to accurately transfer the opening 701 into the substrate 200, forming an etched graphic with uniform morphology and accurate size that meets the requirements in the substrate 200.

[0079] Please refer to Fig.11 , a schematic structural diagram of a semiconductor structure according to another specific embodiment of the present invention.

[0080] In this specific embodiment, a plurality of discrete and spaced second sidewalls 1012 and composite sidewalls are formed on the surface of the substrate 200, and the second sidewalls 1012 and composite sidewalls are rectangular in cross-section along the vertical length direction. The openings 701 between the second sidewalls 1012 and composite sidewalls have the same morphology.

[0081] The composite sidewall includes a second sidewall 1011, which has an inwardly concave sidewall with a top width greater than a bottom width. The concave sidewall of the second sidewall 1011 is also filled with a first sidewall residue 1102, so that the sidewall of the composite sidewall is a vertical sidewall.

[0082] The above is only a preferred embodiment of the present invention. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: providing a substrate; forming a patterned sacrificial layer on the surface of the substrate; Forming a first sidewall on the sidewall surface of the sacrificial layer; removing the sacrificial layer; Filling a second sidewall between adjacent first sidewalls, wherein the top of the second sidewall is lower than the top of the first sidewall; Etching the first sidewall spacer to the surface of the substrate to form a plurality of discrete second sidewall spacers; Using the second sidewall as a mask, etching the substrate; The first sidewall spacer includes a first sub-sidewall spacer and a second sub-sidewall spacer located on the top of the first sub-sidewall spacer, and the width uniformity of the first sub-sidewall spacer is greater than the width uniformity of the second sub-sidewall spacer; The side wall of the first sidewall spacer away from the sacrificial layer is arc-shaped; and the curvature of the arc-shaped side wall of the second sub-sidewall spacer is greater than the curvature of the arc-shaped side wall of the first sub-sidewall spacer; The height of the second sidewall spacer is equal to or smaller than the height of the first sub-sidewall spacer.

2. The method for forming a semiconductor structure according to claim 1, wherein: The top of the second side wall is flat.

3. The method for forming a semiconductor structure according to claim 1, wherein: The first sidewall spacer is etched by a selective etching process or an anisotropic etching process.

4. The method for forming a semiconductor structure according to claim 3, characterized in that: When etching the first sidewall, an etching selectivity ratio between the first sidewall and the second sidewall is greater than 5:

1.

5. The method for forming a semiconductor structure according to claim 1, wherein: The distances between adjacent second side walls are the same.

6. The method for forming a semiconductor structure according to claim 1, wherein: The substrate includes: a substrate and a target layer located on the surface of the substrate; the method of etching the substrate using the second side wall as a mask includes: using the second side wall as a mask to etch the target layer to form a patterned target layer; removing the second side wall, using the patterned target layer as a mask to etch the substrate to form an etched pattern in the substrate.

7. The method for forming a semiconductor structure according to claim 1, wherein: The method for forming the first side wall comprises: forming a first side wall material layer covering the sacrificial layer and the surface of the substrate; etching away the first side wall material layer covering the top of the sacrificial layer and the surface of the substrate along a direction perpendicular to the surface of the substrate to form a first side wall covering the side wall of the sacrificial layer.

8. The method for forming a semiconductor structure according to claim 1, wherein: The method for forming the second side wall includes: forming a second side wall material layer, wherein the second side wall material layer fills the gap between adjacent first side walls and has a surface higher than the top of the first side wall; flattening the surface of the second side wall material layer; etching the second side wall material layer so that the height of the second side wall material layer decreases to form a second side wall whose top is lower than the top of the first side wall.

9. The method for forming a semiconductor structure according to claim 1, wherein: The sacrificial layer is removed by a selective etching process.

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