A watchdog integrated circuit and power supply system

Abstract

The embodiment of the present application discloses a watchdog integrated circuit and a power supply system, the circuit includes a linear regulator, a power supply power-off reset circuit, a watchdog circuit and a NAND gate, wherein: the linear regulator includes an operational amplifier, a PMOS power tube, a first resistor and a second resistor, the negative input end of the operational amplifier is connected to a reference voltage VREF, the positive input end is connected to one end of the first resistor and the second resistor, the other end of the second resistor is grounded, the other end of the first resistor is connected to the drain of the PMOS power tube, the source of the PMOS power tube is connected to an operating voltage VDD, and the gate of the PMOS power tube is connected to the output end of the operational amplifier; the positive input end of the operational amplifier is connected to the input end of the power supply power-off reset circuit, and the input end of the watchdog circuit receives a dog feeding signal sent by a microcontroller; the output ends of the power supply power-off reset circuit and the watchdog circuit are connected to the input end of the NAND gate, and the output end of the NAND gate is connected to the reset end of the microcontroller.

Description

Technical Field

[0001] The embodiments of the present application relate to the technical field of power supply systems, and in particular to a watchdog integrated circuit and a power supply system. Background Art

[0002] In some application scenarios that require high reliability MCU / MPU (Microcontroller Unit), an external hardware watchdog circuit is usually used. In this mode, the power supply system and the watchdog circuit are respectively composed of independent hardware, but at the same time, the two circuits are connected to each other, that is, the power supply system supplies power to the watchdog circuit, and the watchdog circuit monitors the voltage stability of the power supply system. The prior art can flexibly select the power supply system and the watchdog circuit separately, but the prior art only considers the two as independent circuits, but does not consider the coordination between the two. In this regard, the inventor found that when two independent circuits are used at the same time, the material cost is high and the integration is poor. Summary of the invention

[0003] The embodiments of the present application provide a watchdog integrated circuit and a power supply system, which can reduce the material cost of the power supply system and improve the integration of the power supply system.

[0004] In a first aspect, an embodiment of the present application provides a watchdog integrated circuit, comprising: a linear regulator, a power failure reset circuit, a watchdog circuit, and a NAND gate, wherein:

[0005] The linear regulator includes an operational amplifier, a PMOS power tube, a first resistor and a second resistor, wherein the negative input terminal of the operational amplifier is connected to a reference voltage VREF, the positive input terminal is connected to one end of the first resistor and the second resistor, the other end of the second resistor is grounded, the other end of the first resistor is connected to the drain of the PMOS power tube, the source of the PMOS power tube is connected to an operating voltage VDD, and the gate of the PMOS power tube is connected to the output terminal of the operational amplifier;

[0006] The positive input terminal of the operational amplifier is connected to the input terminal of the power failure reset circuit, and the input terminal of the watchdog circuit receives a watchdog feeding signal sent by the microcontroller;

[0007] The output ends of the power-off reset circuit and the watchdog circuit are connected to the input end of the NAND gate, and the output end of the NAND gate is connected to the reset end of the microcontroller.

[0008] Furthermore, the drain of the PMOS power tube is connected to the power supply end of the power failure reset circuit and the watchdog circuit.

[0009] Furthermore, the power-off reset circuit includes a comparator, a first RS trigger, a first inverter and a first AND gate, wherein:

[0010] The positive input terminal of the comparator is connected to the threshold voltage VTH, the negative input terminal of the comparator is connected to the positive input terminal of the operational amplifier, the output terminal of the comparator is connected to the input terminal of the first inverter and the reset terminal of the first RS trigger, the set terminal of the first RS trigger is connected to a high level, the clock terminal of the first RS trigger receives a preset clock pulse signal, the output terminal of the first RS trigger is connected to the first input terminal of the first AND gate, the output terminal of the first inverter is connected to the second input terminal of the first AND gate, and the output terminal of the first AND gate is connected to the first input terminal of the NAND gate.

[0011] Further, the watchdog circuit includes a multiplexer, an edge detector, a frequency divider, a timer, a second RS trigger, a second inverter and a second AND gate, wherein:

[0012] The first input end of the multiplexer receives the dog feeding signal sent by the microcontroller, the output end of the multiplexer is connected to the input end of the edge detector, the output end of the edge detector is connected to the input end of the timer, the output end of the timer is connected to the input end of the frequency divider and the clock end of the second RS trigger, the output end of the frequency divider is connected to the input end of the second inverter and the reset end of the second RS trigger, the set end of the second RS trigger is connected to a high level, the output end of the second RS trigger is connected to the first input end of the second AND gate, the second inverter is connected to the second input end of the second AND gate, the output end of the second AND gate is connected to the second input end of the NAND gate, the frequency divider is used to convert the square wave signal input by the timer into a square wave signal with twice the dog feeding time threshold as a period, the dog feeding time threshold is the maximum time interval between two dog feeding signals, if the time interval between two dog feeding signals is greater than the dog feeding time threshold, it is confirmed that the microcontroller is running incorrectly.

[0013] Furthermore, the watchdog circuit also includes a divider, the output end of the divider is connected to the input end of the divider, the output end of the divider is connected to the second input end of the multiplexer, and the divider is used to divide the dog feeding interval time output by the divider by a preset parameter to shorten the dog feeding interval time.

[0014] Furthermore, the multiplexer is provided with a chip select terminal and an enable terminal. When the enable terminal is connected to a high level, the chip select terminal selects the first input terminal of the multiplexer, the first input terminal of the multiplexer is a valid input terminal, and the second input terminal is an invalid input terminal. When the enable terminal is connected to a low level, the chip select terminal selects the second input terminal of the multiplexer, the second input terminal of the multiplexer is a valid input terminal, and the first input terminal is an invalid input terminal.

[0015] Furthermore, the watchdog integrated circuit also includes a manual reset circuit, an input end of the manual reset circuit receives a manual reset signal, and an output end of the manual reset circuit is connected to an input end of the NAND gate.

[0016] Furthermore, the drain of the PMOS power tube is connected to the power supply end of the manual reset circuit.

[0017] Furthermore, the manual reset circuit includes a third RS trigger, a third inverter and a third AND gate, the reset end of the third RS trigger and the input end of the third inverter receive the manual reset signal, the set end of the third RS trigger is connected to a high level, the clock end of the third RS trigger is connected to a preset clock signal, the output end of the third RS trigger is connected to the first input end of the third AND gate, the output end of the third inverter is connected to the second input end of the third AND gate, and the output end of the third AND gate is connected to the third input end of the NAND gate.

[0018] In a second aspect, an embodiment of the present application provides a power supply system, including:

[0019] As described in the first aspect, the watchdog integrated circuit, the microcontroller and the power supply unit, the watchdog integrated circuit is connected to the microcontroller and the power supply unit.

[0020] The embodiment of the present application integrates the watchdog circuit, the power-off reset circuit and the manual reset circuit into the same circuit, and connects the outputs of the watchdog circuit, the power-off reset circuit and the manual reset circuit through a NAND gate. Whenever any circuit outputs a reset signal, the NAND gate sends a reset signal to the microcontroller to reset the working state of the microcontroller in time to avoid the microcontroller from falling into an infinite loop and the microcontroller being unable to work normally. The voltage of the power supply system is collected through a linear regulator, and the voltage of the power supply system is monitored through a power-off reset circuit. When a voltage abnormality is detected, the power-off reset circuit outputs a reset signal, and the NAND gate sends a reset signal to the microcontroller to achieve real-time monitoring of the power supply system. Through the above-mentioned technical means, the linear regulator, the power-off reset circuit, the manual reset circuit and the watchdog circuit are integrated into one, the reliability of the peripheral devices of the power supply system is increased, the power supply system is highly integrated, and the material cost of the circuit is saved. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 It is a structural schematic diagram of a watchdog integrated circuit provided in Embodiment 1 of the present application;

[0022] Figure 2 It is a schematic diagram of the structure of the power-off reset circuit provided in the first embodiment of the present application;

[0023] Figure 3 is a schematic diagram of the structure of the watchdog circuit provided in Example 1 of the present application;

[0024] Figure 4 is a structural schematic diagram of a manual reset circuit provided in Example 1 of the present application;

[0025] In the figure, 10, linear regulator; VDD, operating voltage; VREF, reference voltage; VOUT, output voltage; VFB, sampling voltage; EA, operational amplifier; PMOS, PMOS power tube; R4, first resistor; R5, second resistor; 20, manual reset circuit; 21, third RS trigger; 22, third AND gate; 23, third inverter; S3, set end of third RS trigger; R3, reset end of third RS trigger; CK3, clock end of third RS trigger; TPR3, second clock pulse signal; MR, manual reset signal; Q3, output end of third RS trigger; 30, power failure reset circuit; 31, first RS trigger; 32, first AND gate; 33, first inverter; COMP, comparator; VTH, threshold voltage; S1, set end of first RS trigger; CK1, clock end of first RS trigger; R1, reset end of first RS trigger; Q 1. The first output terminal of the first RS flip-flop; TPR1, the first clock pulse signal; 40, the watchdog circuit; 41, the multiplexer; 42, the edge detector; 43, the timer; 44, the frequency divider; 45, the second RS flip-flop; 46, the divider; 47, the second inverter; 48, the second AND gate; IN1, the first input terminal of the multiplexer; IN2, the second input terminal of the multiplexer; D, the output terminal of the multiplexer; C, the chip select terminal of the multiplexer; ENB, the enable terminal of the multiplexer; WDI, the dog feeding signal; S2, the set terminal of the second RS flip-flop; R2, the reset terminal of the second RS flip-flop; CK2, the clock terminal of the second RS flip-flop; Q2, the first output terminal of the second RS flip-flop; 50, the NAND gate; Y1, the first input terminal of the NAND gate; Y2, the second input terminal of the NAND gate; Y3, the third input terminal of the NAND gate; 60, the microcontroller; RESET, the reset terminal of the microcontroller. DETAILED DESCRIPTION

[0026] In order to make the purpose, technical scheme and advantages of the present application clearer, the specific embodiments of the present application are further described in detail below in conjunction with the accompanying drawings. It is understood that the specific embodiments described herein are only used to explain the present application, rather than to limit the present application. It should also be noted that, for the convenience of description, only the part related to the present application but not all the contents are shown in the accompanying drawings. Before discussing the exemplary embodiments in more detail, it should be mentioned that some exemplary embodiments are described as processes or methods depicted as flow charts. Although the flow chart describes each operation (or step) as a sequential process, many of the operations therein can be implemented in parallel, concurrently or simultaneously. In addition, the order of each operation can be rearranged. The process can be terminated when its operation is completed, but it can also have additional steps not included in the accompanying drawings. The process can correspond to a method, a function, a procedure, a subroutine, a subprogram, etc.

[0027] The watchdog integrated circuit and power supply system provided by the present application are intended to integrate the watchdog circuit, the power failure reset circuit and the manual reset circuit in the same circuit, and connect the outputs of the watchdog circuit, the power failure reset circuit and the manual reset circuit through the NAND gate. Whenever any circuit outputs a reset signal, the NAND gate sends a reset signal to the microcontroller, and resets the working state of the microcontroller in time to avoid the microcontroller from falling into an infinite loop and the microcontroller cannot work normally. The voltage of the power supply system is collected by a linear regulator, and the voltage of the power supply system is monitored by the power failure reset circuit. When the voltage is abnormal, the power failure reset circuit outputs a reset signal, and the NAND gate sends a reset signal to the microcontroller to realize real-time monitoring of the power supply system. Compared with the traditional watchdog circuit and power supply system, the power supply system and the watchdog circuit are respectively composed of independent hardware, which only considers that the two are independent circuits, but does not consider the coordination problem of the two, and the material cost is high when two independent circuits are used at the same time. Based on this, the watchdog integrated circuit and power supply system provided in the embodiment of the present application. To solve the problem of reducing the material cost of the power supply system, the integration of the power supply system is improved.

[0028] Embodiment 1:

[0029] Figure 1 Schematic diagram of the structure of a watchdog integrated circuit provided in the first embodiment of the present application. Figure 1The watchdog integrated circuit includes a linear regulator 10, a power failure reset circuit 30, a watchdog circuit 40, a manual reset circuit 20 and a NAND gate 50, wherein: the linear regulator 10 includes an operational amplifier EA, a PMOS power tube PMOS, a first resistor R4 and a second resistor R5, the negative input terminal of the operational amplifier EA is connected to a reference voltage VREF, the positive input terminal is connected to one end of the first resistor R4 and the second resistor R5, the other end of the second resistor R5 is grounded, the other end of the first resistor R4 is connected to the drain of the PMOS power tube PMOS, and the PMOS power The source of the PMOS tube is connected to the working voltage VDD, and the gate of the PMOS power tube PMOS is connected to the output end of the operational amplifier EA; the positive input end of the operational amplifier EA is connected to the input end of the power failure reset circuit 30, the input end of the watchdog circuit 40 receives the dog feeding signal WDI sent by the microcontroller 60, and the input end of the manual reset circuit 20 receives the manual reset signal MR; the output ends of the power failure reset circuit 30, the watchdog circuit 40 and the manual reset circuit 20 are connected to the input end of the NAND gate 50, and the output end of the NAND gate 50 is connected to the reset end of the microcontroller 60. The drain of the PMOS power tube PMOS is connected to the power supply end of the power failure reset circuit 30, the watchdog circuit 40 and the manual reset circuit 20.

[0030] Exemplarily, the first resistor R4 and the second resistor R5 form a voltage-dividing resistor network, and the output voltage VOUT output by the PMOS power tube is sampled through the voltage-dividing resistor network to obtain a sampling voltage VFB, and the sampling voltage VFB is linearly related to the output voltage VOUT. The operational amplifier EA compares the reference voltage VREF input at the negative input terminal with the sampling voltage VFB input at the positive input terminal. When the sampling voltage VFB is less than the reference voltage VREF, the output voltage VOUT of the operational amplifier EA decreases, the driving capability of the PMOS power tube PMOS connected to the output terminal of the operational amplifier EA is enhanced, the output voltage VOUT increases, and the sampling voltage VFB which is linearly related to the output voltage VOUT increases. When the sampling voltage VFB is greater than the reference voltage VREF, the output voltage VOUT of the operational amplifier EA increases, the driving capability of the PMOS power tube is weakened, the output voltage VOUT decreases, and the sampling voltage VFB decreases. The output voltage VOUT is connected to the power supply terminal of the power-off reset circuit 30, the manual reset circuit 20 and the watchdog circuit 40, and the three reset circuits are powered by the output voltage VOUT, and the output voltage VOUT is dynamically adjusted by the linear regulator 10 to achieve stable power supply. The output ends of the three reset circuits are connected to the input end of the NAND gate 50. When any one of the three reset circuits outputs a low-level signal, the NAND gate 50 sends a high-level signal to the reset end of the microcontroller 60. The microcontroller 60 responds to the high-level signal input to the reset end and performs a reset operation. It can be understood that the reset signals output by the three reset circuits are low-level signals.

[0031] Furthermore, the sampling voltage VFB is connected to the power failure reset circuit 30, and the output voltage VOUT of the linear regulator 10 is monitored by the power failure reset circuit 30 to ensure the stable output of the output voltage VOUT. Specifically, Figure 2 3 is a schematic diagram of the structure of the power failure reset circuit 30 provided in the first embodiment of the present application. Figure 2 The power-off reset circuit 30 includes a comparator COMP, a first RS trigger 31, a first inverter 33 and a first AND gate 32, wherein: the positive input terminal of the comparator COMP is connected to the threshold voltage VTH, the negative input terminal of the comparator COMP is connected to the positive input terminal of the operational amplifier EA, the output terminal of the comparator COMP is connected to the input terminal of the first inverter 33 and the reset terminal R1 of the first RS trigger 31, the set terminal S1 of the first RS trigger 31 is connected to a high level, the clock terminal CK1 of the first RS trigger 31 receives the first clock pulse signal TPR1, the output terminal of the first RS trigger 31 is connected to the first input terminal of the first AND gate 32, the output terminal of the first inverter 33 is connected to the second input terminal of the first AND gate 32, and the output terminal of the first AND gate 32 is connected to the first input terminal Y1 of the NAND gate.

[0032] Exemplarily, the comparator COMP compares the threshold voltage VTH inputted at the positive input terminal with the sampling voltage VFB inputted at the negative input terminal. When the threshold voltage VTH is greater than the sampling voltage VFB, the comparator COMP sends a high-level signal to the input terminal of the first inverter 33. The first inverter converts the high-level signal into a low-level signal, and sends the low-level signal to the first AND gate 32. The first AND gate 32 responds to the low-level signal sent by the first inverter 33 and sends a low-level signal to the first input terminal Y1 of the NAND gate 50. The NAND gate 50 responds to the low-level signal and sends a high-level signal to the reset terminal RESET of the microcontroller 60. The microcontroller 60 responds to the high-level signal of the reset terminal RESET and performs a reset operation, thereby realizing a fast trigger reset. The comparator COMP also sends a high-level signal to the reset terminal R1 of the first RS trigger 31. The first RS trigger 31 responds to the high-level signal of the reset terminal R1, and when the first clock pulse signal TPR1 is at a high level, sets the current trigger state to 0, and the output terminal Q1 of the first RS trigger 31 outputs the current trigger state, that is, the output terminal Q1 of the first RS trigger 31 outputs a low-level signal. The output terminal Q1 of the first RS trigger sends a low-level signal to the first AND gate, but because the first inverter 33 has sent a low-level signal to the first AND gate 32, no matter what signal the first RS trigger 31 outputs, the reset has been triggered at this time. When the threshold voltage VTH is less than the sampling voltage VFB, the comparator COMP sends a low-level signal to the first inverter 33, and the first inverter 33 converts the low-level signal into a high-level signal and inputs the high-level signal to the first AND gate 32. At this time, whether the first AND gate 32 outputs a high-level signal or a low-level signal also depends on the output signal of the first RS trigger. The comparator COMP sends a low-level signal to the reset terminal R1 of the first RS flip-flop 31. Since the low-level signal input to the reset terminal R1 is an invalid input signal, and the set terminal S1 inputs a high-level signal, the first RS flip-flop 31 responds to the high-level signal of the set terminal S1, and when the first clock pulse signal TPR1 is at a high level, the current flip-flop state is set to 1, and the output terminal Q1 of the first RS flip-flop 31 outputs a high-level signal to the first AND gate 32. At this time, both input terminals of the first AND gate 32 are high-level signals, and the first AND gate 32 inputs a high-level signal to the NAND gate 50. If other reset circuits all output high-level signals at this time, the NAND gate 50 sends a low-level signal to the reset terminal RESET of the microcontroller 60 according to the high-level signals of all input terminals, and the microcontroller 60 responds to the low-level signal of the reset terminal RESET, and does not perform the reset operation or stops performing the reset operation.It should be noted that if the reset terminal R1 of the first RS trigger 31 inputs a low level, and the first clock pulse signal TPR1 inputted to the clock terminal CK1 of the first RS trigger 31 is a low level, the state of the current trigger is kept consistent with the state of the trigger at the previous moment, that is, if the first RS trigger 31 outputs a low level at the previous moment, the current first RS trigger 31 outputs a low level. After a period of time, when the first clock pulse signal TPR1 is converted from a low level signal to a high level signal, the first RS trigger 31 responds to the high level signal of the set terminal S1, and the output terminal Q1 outputs a high level signal, that is, the first RS trigger 31 converts the output signal after a period of delay. Among them, the current moment and the previous moment are two time periods within any cycle of the clock pulse signal.

[0033] Furthermore, the microcontroller 60 sends a dog feeding signal WDI to the input end of the watchdog circuit 40, and the watchdog circuit 40 monitors the operation status of the microcontroller 60. Specifically, Figure 3 4 is a schematic diagram of the structure of the watchdog circuit 40 provided in the first embodiment of the present application. Figure 3The watchdog circuit 40 includes a multiplexer 41, an edge detector 42, a frequency divider 44, a timer 43, a second RS trigger 45, a divider 46, a second inverter 47 and a second AND gate 48, wherein: the multiplexer 41 is provided with a first input terminal IN1, a second input terminal IN2, an output terminal D, a chip select terminal C and an enable terminal ENB, the first input terminal IN1 of the multiplexer 41 receives the dog feeding signal WDI sent by the microcontroller 60, the output terminal D of the multiplexer 41 is connected to the input terminal of the edge detector 42, the output terminal of the edge detector 42 is connected to the input terminal of the timer 43, and the output terminal of the timer 43 is connected The input end of the frequency divider 44 is connected to the clock end CK2 of the second RS flip-flop 45, the output end of the frequency divider 44 is connected to the input end of the second inverter 47 and the reset end R1 of the second RS flip-flop 45, the set end S1 of the second RS flip-flop 45 is connected to a high level, the output end of the second RS flip-flop 45 is connected to the first input end of the second AND gate 48, the output end of the second inverter 47 is connected to the second input end of the second AND gate 48, the output end of the second AND gate 48 is connected to the second input end Y2 of the NAND gate 50, the output end of the frequency divider 44 is connected to the input end of the divider 46, and the output end of the divider 46 is connected to the second input end of the multiplexer 41. The frequency divider 44 is used to convert the square wave signal input by the timer 43 into a square wave signal with a period of twice the dog feeding time threshold. The dog feeding time threshold is the maximum time interval between two dog feeding signals WDI. If the time interval between two dog feeding signals WDI is greater than the dog feeding time threshold, it is confirmed that the microcontroller 60 is running incorrectly. The divider 46 is used to divide the dog feeding interval output by the frequency divider 44 by a preset parameter to shorten the dog feeding interval. When the enable terminal ENB is connected to a high level, the chip select terminal C selects the first input terminal IN1 of the multiplexer 41, the first input terminal IN1 of the multiplexer 41 is a valid input terminal, and the second input terminal IN2 is an invalid input terminal. When the enable terminal ENB is connected to a low level, the chip select terminal C selects the second input terminal IN2 of the multiplexer 41, the second input terminal IN2 of the multiplexer 41 is a valid input terminal, and the first input terminal IN1 is an invalid input terminal.

[0034] Exemplarily, when the first input terminal IN1 is a valid input terminal, the multiplexer 41 receives the dog feeding signal WDI sent by the microcontroller 60 through the first input terminal IN1, and sends the dog feeding signal WDI to the edge detector 42. The edge detector 42 outputs a pulse signal according to the step change of the dog feeding signal WDI, and sends the pulse signal to the input terminal of the timer 43. The timer 43 clears the current timing state and re-times according to the pulse signal at the input terminal, outputs a square wave signal of a preset time period, and sends the square wave signal to the input terminal of the frequency divider 44 and the clock terminal of the second RS trigger 45, and uses the square wave signal output by the timer 43 as the clock pulse signal of the second RS trigger 45. The frequency divider 44 converts the square wave signal into a square wave signal with a period of twice the dog feeding time threshold according to the square wave signal at the input terminal, and sends it to the reset terminal of the second RS trigger 45. Exemplarily, the timer 43 outputs a square wave signal with a period of 2ms, and the dog feeding time threshold is 10ms, then the square wave signal with a period of 2ms is converted into a square wave signal of 20ms by the frequency divider 44. Assuming that the timer 43 receives a pulse signal sent by the edge detector 42 again 8ms after receiving the pulse signal sent by the edge detector 42, that is, the time interval between two consecutive dog feeding signals WDI is 8ms, the timer 43 generates a square wave signal with a length of 4 time periods according to the pulse signals sent by the edge detector 42 before and after, and the frequency divider 44 converts the square wave signal into a low-level signal with a length of 8ms. Assuming that the time interval between two consecutive dog feeding signals WDI is 12ms, the timer 43 generates a square wave signal with a length of 6 time periods, and the frequency divider 44 converts the square wave signal into a low-level signal of 10ms first and then a high-level signal of 2ms. It is understandable that if the time interval between two consecutive dog feeding signals WDI is greater than the dog feeding time threshold, the divider 44 will send a high level signal to the second RS trigger 45 and the second inverter 47 at the time node of the dog feeding time threshold after the timer 43 starts timing to trigger the reset output.

[0035] Further, when the second inverter 47 receives a high-level signal, it converts the high-level signal into a low-level signal and sends the low-level signal to the second AND gate 48. The second AND gate 48 responds to the low-level signal sent by the second inverter 47 and sends a low-level signal to the second input terminal Y2 of the NAND gate 50. The NAND gate 50 responds to the low-level signal and sends a high-level signal to the reset terminal RESET of the microcontroller 60. The microcontroller 60 responds to the high-level signal of the reset terminal RESET and performs a reset operation, thereby realizing a fast trigger reset. When the reset terminal R2 of the second RS trigger 45 receives a high-level signal, when the first clock pulse signal TPR1 is at a high level, the current trigger state is set to 0, and the output terminal Q2 of the second RS trigger 45 outputs the current trigger state, that is, the output terminal Q2 outputs a low-level signal. The output terminal Q2 of the second RS trigger 45 sends a low-level signal to the second AND gate, but since the second inverter 47 has sent a low-level signal to the second AND gate 48, no matter what signal the second RS trigger 45 outputs, the reset has been triggered at this time.

[0036] When the second inverter 47 receives a low-level signal, the second inverter 47 converts the low-level signal into a high-level signal, and inputs the high-level signal to the second AND gate 48. At this time, whether the first AND gate 48 outputs a high-level signal or a low-level signal also depends on the output signal of the second RS flip-flop. When the reset terminal R2 of the second RS flip-flop 45 receives a low-level signal, since the low-level signal input to the reset terminal R2 is an invalid input signal, and the set terminal S2 inputs a high-level signal, the second RS flip-flop 45 responds to the high-level signal of the set terminal S2, and when the square wave signal is high, the current trigger state is set to 1, and the output terminal Q2 of the second RS flip-flop 45 outputs the current trigger state, that is, the output terminal Q2 outputs a high-level signal to the second AND gate 48. At this time, both input terminals of the second AND gate 48 are high-level signals, and the second AND gate 48 inputs a high-level signal to the NAND gate 50. If all other reset circuits output high-level signals at this time, the NAND gate 50 sends a low-level signal to the reset terminal RESET of the microcontroller 60 according to the high-level signals of all input terminals, and the microcontroller 60 responds to the low-level signal of the reset terminal RESET and does not perform the reset operation or stops performing the reset operation. It should be noted that if a low level is input to the reset terminal of the second RS trigger 45, the square wave signal output by the timer 43 input by the clock terminal CK2 of the second RS trigger 45 is low, then the state of the current trigger is kept consistent with the state of the trigger at the previous moment, and if the second RS trigger 45 outputs a low level at the previous moment, the current second RS trigger 45 outputs a low level. After a period of time, the square wave signal is converted from a low level to a high level signal, and the second RS trigger 45 responds to the high level signal of the set terminal S2, and Q2 outputs a high level signal, that is, the second RS trigger 45 converts the output information after a period of delay.

[0037] Further, when the second input terminal IN2 is a valid input terminal, the multiplexer 41 receives the internal dog feeding signal output by the divider 46 through the second input terminal IN2, and sends the internal dog feeding signal to the edge detector 42. Assuming that the frequency divider 44 outputs a low-level signal with a length of 8ms, the divider 46 converts the low-level signal of 8ms into a low-level signal of 8ms / k (k is a real number and k>1) according to the preset parameters, shortens the dog feeding time interval, and ensures that the dog is automatically fed before the dog feeding time threshold is reached, the frequency divider 44 outputs a low-level signal, the trigger state of the second RS trigger 45 is set to 1, and the output terminal Q2 of the second RS trigger 45 remains at a high level, and the watchdog circuit 40 will not trigger the reset output. It can be understood that when the second input terminal IN2 and the first input terminal IN1 of the multiplexer are valid input terminals, the entire operation process of the watchdog circuit 40 is the same except that the input dog feeding signal is different, and the process from the edge detector 42 to the third AND gate 48 is not repeated here, and the details can be referred to the above embodiment.

[0038] Furthermore, the manual reset signal MR is input to the input end of the manual reset circuit 20. When other reset circuits fail to work properly or fail, the microcontroller 60 is forcibly reset through the manual reset circuit 20. Specifically, Figure 4 2 is a schematic diagram of the structure of the manual reset circuit 20 provided in the first embodiment of the present application. Figure 4 The manual reset circuit 20 includes a third RS trigger 21, a third inverter 23 and a third AND gate 22. The reset terminal R3 of the third RS trigger 21 and the input terminal of the third inverter 23 receive the manual reset signal MR. The set terminal S3 of the third RS trigger 21 is connected to a high level. The clock terminal CK3 of the third RS trigger 21 receives the second clock pulse signal TPR3. The output terminal of the third RS trigger 21 is connected to the first input terminal of the third AND gate 22. The output terminal of the third inverter is connected to the second input terminal of the third AND gate 22. The output terminal of the third AND gate 22 is connected to the third input terminal Y3 of the NAND gate 50.

[0039] Exemplarily, when the manual reset signal MR is a high-level signal, the third inverter 23 receives the high-level signal, converts the high-level signal into a low-level signal, and sends the low-level signal to the third AND gate 22. The third AND gate 22 responds to the low-level signal sent by the third inverter 23, and sends a low-level signal to the third input terminal Y3 of the NAND gate 50. The NAND gate 50 responds to the low-level signal and sends a high-level signal to the reset terminal RESET of the microcontroller 60. The microcontroller 60 responds to the high-level signal of the reset terminal RESET and performs a reset operation, thereby realizing a fast trigger reset. The reset terminal R3 of the third RS trigger 21 receives a high-level signal, and the third RS trigger 21 responds to the high-level signal of the reset terminal R3, and when the second clock pulse signal TPR3 is high, the current trigger state is set to 0, and the output terminal Q3 of the third RS trigger 21 outputs the current trigger state, that is, the output terminal Q3 outputs a low-level signal. The output terminal Q3 of the third RS trigger sends a low level signal to the third AND gate 22, but since the third inverter 23 has sent a low level signal to the third AND gate 22, no matter what signal the third RS trigger 21 outputs, the reset has been triggered at this time. When the manual reset signal MR is a low level signal, the third inverter 23 receives the low level signal, converts the low level signal into a high level signal, and inputs the high level signal to the third AND gate 33. At this time, whether the third AND gate 33 outputs a high level signal or a low level signal depends on the output signal of the third RS trigger. The reset terminal of the third RS trigger 21 receives a low level signal, and the third RS trigger 21 responds to the low level signal of the reset terminal R3. Since the low level signal input to the reset terminal R3 is an invalid input signal, and the set terminal S3 inputs a high level signal, the third RS trigger 21 responds to the high level signal of the set terminal S3, and when the second clock pulse signal TPR3 is high, the current trigger state is set to 1, and the output terminal Q3 sends a high level signal to the third AND gate 22. At this time, both input terminals of the third AND gate 22 are high-level signals, and the third AND gate 22 inputs a high-level signal to the NAND gate 50. If the other reset circuits all output high-level signals at this time, the NAND gate 50 sends a low-level signal to the reset terminal of the microcontroller 60 according to the high-level signals of all input terminals, and the microcontroller 60 responds to the low-level signal of the reset terminal and does not perform the reset operation or stops performing the reset operation. It should be noted that if the reset terminal R3 of the third RS trigger 21 inputs a low level, and the second clock pulse signal TPR3 inputted by the clock terminal CK3 of the third RS trigger 21 is a low level, the state of the current trigger is kept consistent with the state of the trigger at the previous moment, that is, if the third RS trigger 21 outputs a low level at the previous moment, the current third RS trigger 21 outputs a low level.After a period of time, when the second clock pulse signal TPR3 is converted from a low level signal to a high level signal, the third RS trigger 21 responds to the high level signal of the set terminal S3, and the output terminal Q3 outputs a high level signal, that is, the third RS trigger 21 converts the output signal after a period of delay.

[0040] In one embodiment, a power supply system includes a watchdog integrated circuit, a microcontroller 60 and a power supply unit, wherein the first input terminal IN1 of the multiplexer 41 of the watchdog circuit 40 of the watchdog integrated circuit is connected to the output terminal of the dog feeding signal WDI of the microcontroller 60, the output terminal of the NAND gate 50 is connected to the reset terminal RESET of the microcontroller 60, and the power output terminal of the power supply unit is connected to the source of the PMOS power tube PMOS of the linear regulator 10 of the watchdog integrated circuit, that is, the power supply unit provides the working voltage VDD for the watchdog integrated circuit.

[0041] The above are only preferred embodiments of the present application and the technical principles used. The present application is not limited to the specific embodiments described herein, and various obvious changes, readjustments and substitutions that can be made by those skilled in the art will not deviate from the scope of protection of the present application. Therefore, although the present application is described in more detail through the above embodiments, the present application is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present application, and the scope of the present application is determined by the scope of the claims.

Claims

1. A watchdog integrated circuit, characterized in that: include: Linear regulator, power-off reset circuit, watchdog circuit and NAND gate, among which: The linear regulator includes an operational amplifier, a PMOS power tube, a first resistor and a second resistor, wherein the negative input terminal of the operational amplifier is connected to a reference voltage VREF, the positive input terminal is connected to one end of the first resistor and the second resistor, the other end of the second resistor is grounded, the other end of the first resistor is connected to the drain of the PMOS power tube, the source of the PMOS power tube is connected to an operating voltage VDD, and the gate of the PMOS power tube is connected to the output terminal of the operational amplifier; The positive input terminal of the operational amplifier is connected to the input terminal of the power failure reset circuit, and the input terminal of the watchdog circuit receives a watchdog feeding signal sent by the microcontroller; The output ends of the power-off reset circuit and the watchdog circuit are connected to the input end of the NAND gate, and the output end of the NAND gate is connected to the reset end of the microcontroller; The drain of the PMOS power tube is connected to the power supply end of the power failure reset circuit and the watchdog circuit; The watchdog integrated circuit also includes a manual reset circuit, an input end of the manual reset circuit receives a manual reset signal, and an output end of the manual reset circuit is connected to an input end of the NAND gate.

2. The circuit according to claim 1, characterized in that The power-off reset circuit comprises a comparator, a first RS trigger, a first inverter and a first AND gate, wherein: The positive input terminal of the comparator is connected to the threshold voltage VTH, the negative input terminal of the comparator is connected to the positive input terminal of the operational amplifier, the output terminal of the comparator is connected to the input terminal of the first inverter and the reset terminal of the first RS trigger, the set terminal of the first RS trigger is connected to a high level, the clock terminal of the first RS trigger receives a preset clock pulse signal, the output terminal of the first RS trigger is connected to the first input terminal of the first AND gate, the output terminal of the first inverter is connected to the second input terminal of the first AND gate, and the output terminal of the first AND gate is connected to the first input terminal of the NAND gate.

3. The circuit according to claim 1, characterized in that The watchdog circuit comprises a multiplexer, an edge detector, a frequency divider, a timer, a second RS trigger, a second inverter and a second AND gate, wherein: The first input end of the multiplexer receives the dog feeding signal sent by the microcontroller, the output end of the multiplexer is connected to the input end of the edge detector, the output end of the edge detector is connected to the input end of the timer, the output end of the timer is connected to the input end of the frequency divider and the clock end of the second RS trigger, the output end of the frequency divider is connected to the input end of the second inverter and the reset end of the second RS trigger, the set end of the second RS trigger is connected to a high level, the output end of the second RS trigger is connected to the first input end of the second AND gate, the second inverter is connected to the second input end of the second AND gate, the output end of the second AND gate is connected to the second input end of the NAND gate, the frequency divider is used to convert the square wave signal input by the timer into a square wave signal with twice the dog feeding time threshold as a period, the dog feeding time threshold is the maximum time interval between two dog feeding signals, if the time interval between two dog feeding signals is greater than the dog feeding time threshold, it is confirmed that the microcontroller is running incorrectly.

4. The circuit according to claim 3, characterized in that The watchdog circuit also includes a divider, the output end of the divider is connected to the input end of the divider, the output end of the divider is connected to the second input end of the multiplexer, and the divider is used to divide the dog feeding interval time output by the divider by a preset parameter to shorten the dog feeding interval time.

5. The circuit according to claim 4, characterized in that The multiplexer is provided with a chip select terminal and an enable terminal. When the enable terminal is connected to a high level, the chip select terminal selects the first input terminal of the multiplexer, the first input terminal of the multiplexer is a valid input terminal, and the second input terminal is an invalid input terminal. When the enable terminal is connected to a low level, the chip select terminal selects the second input terminal of the multiplexer, the second input terminal of the multiplexer is a valid input terminal, and the first input terminal is an invalid input terminal.

6. The circuit according to claim 1, characterized in that The drain of the PMOS power tube is connected to the power supply end of the manual reset circuit.

7. The circuit according to claim 1, characterized in that The manual reset circuit includes a third RS flip-flop, a third inverter and a third AND gate, the reset end of the third RS flip-flop and the input end of the third inverter receive the manual reset signal, the set end of the third RS flip-flop is connected to a high level, the clock end of the third RS flip-flop is connected to a preset clock signal, the output end of the third RS flip-flop is connected to the first input end of the third AND gate, the output end of the third inverter is connected to the second input end of the third AND gate, and the output end of the third AND gate is connected to the third input end of the NAND gate.

8. A power supply system, characterized in that: The power supply system comprises: A watchdog integrated circuit, a microcontroller and a power supply unit as described in any one of claims 1 to 7, wherein the watchdog integrated circuit is connected to the microcontroller and the power supply unit.

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