A Trench MOSFET Circuit Model Based on Physical Structure and Its Establishment Method

Abstract

The embodiment of the present application provides a trench MOSFET circuit model based on physical structure and a method for establishing the same, including a voltage-controlled voltage source, a first MOSFET, a second MOSFET, a first resistor, a second resistor, a first capacitor, a second capacitor and a diode; the technical solution provided by the present application is based on parameter fitting of the current-voltage equation, combined with SPICE simulation technology, to achieve a SPICE macro model with high accuracy, high speed and conformity to the physical characteristics of the device. The model is suitable for trench MOSFET devices, is compatible with various SPICE simulators, improves simulation accuracy and speed, and shortens the design cycle of power supply devices.

Description

Technical Field

[0001] The embodiments of the present application belong to the field of modeling and simulation of conductor devices, and specifically relate to a trench MOSFET circuit model based on physical structure and a method for establishing the same. Background Art

[0002] In recent years, trench MOSFET has been widely used in circuit output interface, LCD driver, power management and other circuits. Its operating voltage is about 14-60V, the process is simpler than lateral diffusion MOS (LDMOS), and it is compatible with traditional CMOS process. While improving the withstand voltage, it greatly reduces the cost. It is a key and basic product for the transformation of power electronics from low frequency to high frequency and the breakthrough of power frequency conversion. The widespread application of trench MOSFET has led to the need for accurate transistor models in more and more ultra-large-scale integrated circuit design simulations.

[0003] The industry uses the following two methods to model power MOSFETs: (1) using the Berkeley short-channel insulated-gate field-effect transistor model (BSIM) to model the device; (2) constructing a macro model based on SPICE3 to model the device.

[0004] The BSIM model, which is currently the most widely used model in the power device industry, has a higher accuracy than SPICE3, but its simulation modeling difficulty is greatly increased, which brings many unfavorable factors to the modeling work. The macro model constructed based on SPICE3 can achieve faster modeling while ensuring a certain accuracy, and is more convenient for circuit simulation and use, but lacks the reflection of physical structure parameters, and it is difficult to ensure the self-consistency of device characteristics.

[0005] Because the existing trench MOSFET models have various shortcomings, it is necessary to create a new trench MOSFET macro model that is more accurate, fast, and physically meaningful. Summary of the invention

[0006] The embodiment of the present application aims to overcome the above-mentioned problems or at least partially solve or alleviate the above-mentioned problems. The technical solution provided by the present application is based on parameter fitting of the current-voltage equation, combined with SPICE simulation technology, to realize a SPICE macro model with high accuracy, high speed and conformity to the physical characteristics of the device.

[0007] In a first aspect, an embodiment of the present invention provides a trench MOSFET circuit model based on a physical structure, including a voltage-controlled voltage source, a first MOSFET, a second MOSFET, a first resistor, a second resistor, a first capacitor, a second capacitor and a diode;

[0008] The input end of the voltage-controlled voltage source is connected to the first end of the first resistor, and the second end of the first resistor leads to the gate of the circuit model;

[0009] The drain of the first MOSFET is connected to the first end of the second resistor, the second end of the second resistor leads to the drain of the circuit model, and the source of the first MOSFET leads to the source of the circuit model; the substrate of the first MOSFET is connected to the source of the first MOSFET, and the gate of the first MOSFET is connected to the output end of the voltage-controlled voltage source;

[0010] The source and drain of the second MOSFET are both connected to the source of the first MOSFET, the gate of the second MOSFET is connected to the output end of the voltage-controlled voltage source, and the substrate of the second MOSFET is connected to the second end of the second resistor;

[0011] A first end of the first capacitor is connected to the gate of the first MOSFET, and a second end of the first capacitor is connected to the source of the first MOSFET;

[0012] A first end of the second capacitor is connected to the gate of the second MOSFET, and a second end of the second capacitor is connected to the substrate of the second MOSFET;

[0013] Two ends of the diode are respectively connected to the source and drain of the first MOSFET.

[0014] As a preferred embodiment of the present invention, the first MOSFET is of N type and the second MOSFET is of P type; or,

[0015] The first MOSFET is of P type, and the second MOSFET is of N type.

[0016] As a preferred embodiment of the present invention, the voltage-controlled voltage source includes a voltage source, a current source and a third resistor;

[0017] The control input end of the voltage-controlled voltage source is connected to the positive electrode of the voltage source, the control output end of the voltage-controlled voltage source is connected to the first end of the third resistor and the outflow end of the current source, and the negative electrode of the voltage source, the second end of the third resistor and the inflow end of the current source are commonly connected to the source of the first MOSFET.

[0018] As a preferred embodiment of the present invention, the first MOSFET is used to simulate the characteristics of the channel current of the device changing with the gate voltage;

[0019] The second resistor is used to simulate the path series resistance generated by the connection between the epitaxial layer and substrate of the device and the drain of the first MOSFET;

[0020] The second MOSFET is used to simulate the capacitance formed by using the epitaxial layer as the substrate at the bottom of the device gate and the first MOSFET substrate region as the source and drain;

[0021] The voltage-controlled voltage source and its control terminal are used to adjust the high-temperature and low-temperature transfer curve characteristics of the analog device;

[0022] The first resistor is used to adjust the path resistance of the gate of the analog device;

[0023] The first capacitor and the second capacitor are used to adjust the capacitance effect of the gate-source and gate-drain ports of the analog device;

[0024] The diode is used to simulate the parasitic body diode between the source and drain of the device.

[0025] Compared with the prior art, the technical solution provided by the present application is based on parameter fitting of the current-voltage equation and combined with SPICE simulation technology to realize a SPICE macro model with high precision, high speed and conformity to the physical characteristics of the device. The model is suitable for trench MOSFET devices and is compatible with various SPICE simulators, which improves the simulation accuracy and speed and shortens the design cycle of power supply devices.

[0026] In a second aspect, an embodiment of the present invention further provides a method for establishing a trench MOSFET circuit model based on a physical structure, comprising:

[0027] Construct a normal temperature DC model of the MOSFET circuit model;

[0028] A normal temperature DC circuit model, including a first MOSFET, a second resistor, and a diode;

[0029] The drain of the first MOSFET is connected to the first end of the second resistor, the second end of the second resistor leads to the drain of the circuit model, the gate of the first MOSFET is connected to the output end of the voltage-controlled voltage source, and the two ends of the diode are respectively connected to the source and drain of the first MOSFET;

[0030] Construct high and low temperature DC models for MOSFET circuit models;

[0031] The high and low temperature DC circuit model includes a voltage-controlled voltage source, which includes a voltage source, a current source and a third resistor;

[0032] The input end of the voltage-controlled voltage source is connected to the first end of the first resistor, the control input end of the voltage-controlled voltage source is connected to the positive electrode of the voltage source, the control output end of the voltage-controlled voltage source is connected to the first end of the third resistor and the outflow end of the current source, and the negative electrode of the voltage source, the second end of the third resistor and the inflow end of the current source are commonly connected to the source electrode of the first MOSFET, so as to adjust the high-temperature and low-temperature transfer characteristics of the MOSFET device;

[0033] Construct a complete capacitor model for the MOSFET circuit model;

[0034] A capacitor model, including a second MOSFET, a first resistor, a first capacitor and a second capacitor;

[0035] The source and drain of the second MOSFET are both connected to the source of the first MOSFET, the gate of the second MOSFET is connected to the input end of the voltage-controlled voltage source, the substrate of the second MOSFET is connected to the second end of the second resistor, the first end of the first resistor is connected to the input end of the voltage-controlled voltage source, the second end of the first resistor leads to the gate of the circuit model, the first end of the first capacitor is connected to the gate of the first MOSFET, and the second end of the first capacitor is connected to the source of the first MOSFET; the first end of the second capacitor is connected to the gate of the second MOSFET, and the second end of the second capacitor is connected to the substrate of the second MOSFET. In a second aspect, an embodiment of the present invention also provides a method for establishing a trench MOSFET circuit model based on a physical structure, comprising:

[0036] Compared with the prior art, the beneficial effects of the embodiments provided in the second aspect of the present application are the same as the beneficial effects of any of the above-mentioned technical solutions, which will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. Some specific embodiments of the present application will be described in detail in an illustrative and non-restrictive manner with reference to the drawings. The same reference numerals in the drawings indicate the same or similar components or parts. It should be understood by those skilled in the art that these drawings are not necessarily drawn to scale. In the drawings:

[0038] Figure 1 A structure diagram of a trench MOSFET circuit model based on a physical structure in a specific embodiment of the present application;

[0039] Figure 2 A circuit structure diagram of a voltage-controlled voltage source in a specific embodiment of the present application;

[0040] Figure 3 A flow chart of a method for establishing a circuit model of a trench MOSFET based on physical structure provided in a specific embodiment of the present application. DETAILED DESCRIPTION

[0041] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present application.

[0042] like Figure 1 As shown, the embodiment of the present invention provides a trench MOSFET circuit model based on a physical structure, including a voltage-controlled voltage source 03, a first MOSFET 01, a second MOSFET 02, a first resistor 08, a second resistor 04, a first capacitor 06, a second capacitor 05 and a diode 07;

[0043] The input end of the voltage-controlled voltage source 03 is connected to the first end of the first resistor 08, and the second end of the first resistor 08 leads to the gate G of the circuit model;

[0044] like Figure 2 As shown, the voltage-controlled voltage source 03 includes a voltage source 03-1, a current source 03-2 and a third resistor 03-3;

[0045] The control input end of the voltage-controlled voltage source 03 is connected to the positive electrode of the voltage source 03-1, the negative electrode of the voltage source 03-1 is connected to the source of the first MOSFET 01, the control output end of the voltage-controlled voltage source 03 is connected to the first end of the third resistor 03-3 and the outflow end of the current source 03-2, and the second end of the third resistor 03-3 and the inflow end of the current source 03-2 are commonly connected to the source of the first MOSFET 01.

[0046] The drain of the first MOSFET 01 is connected to the first end of the second resistor 04, the second end of the second resistor 04 leads to the drain D of the circuit model, and the source of the first MOSFET 01 leads to the source S of the circuit model; the substrate of the first MOSFET 01 is connected to the source of the first MOSFET 01, and the gate of the first MOSFET 01 is connected to the output end of the voltage-controlled voltage source 03. The first MOSFET 01 is used to simulate the characteristics of the channel current of the device changing with the gate voltage. The second resistor 08 is used to simulate the path series resistance generated by the connection between the epitaxial layer and the substrate of the device and the drain of the first MOSFET; the second MOSFET 02 is used to simulate the capacitance formed at the bottom of the gate of the device with the epitaxial layer as the substrate and the substrate area of ​​the first MOSFET 01 as the source and drain; the voltage-controlled voltage source 03 and its control end are used to adjust the high-temperature and low-temperature transfer curve characteristics of the simulated device; the first capacitor 06 and the second capacitor 05 are used to adjust the capacitance effect of the gate-source and gate-drain ports of the simulated device.

[0047] Diode 07 is used to simulate the parasitic body diode between the source and drain of the device.

[0048] The source and drain of the second MOSFET 02 are both connected to the source of the first MOSFET 01, the gate of the second MOSFET 02 is connected to the output end of the voltage-controlled voltage source 03, and the substrate of the second MOSFET 01 is connected to the second end of the second resistor;

[0049] The first resistor is used to simulate the path resistance of the gate of the adjustment device;

[0050] A first end of the first capacitor 06 is connected to the gate of the first MOSFET 01, and a second end of the first capacitor 06 is connected to the source of the first MOSFET 01;

[0051] A first end of the second capacitor 05 is connected to the gate of the second MOSFET 02 , and a second end of the second capacitor 05 is connected to the substrate of the second MOSFET 02 .

[0052] The two ends of diode 07 are connected to the source and drain of the first MOSFET 01 respectively, that is, for NMOS, the anode of diode 07 is connected to the source of the first MOSFET, and the cathode of diode 07 is connected to the drain of the first MOSFET; for PMOS, the anode of diode 07 is connected to the drain of the first MOSFET, and the cathode of diode 07 is connected to the source of the first MOSFET.

[0053] In the embodiment of the present invention, if the characterized device is NMOS, the first MOSFET 01 is NMOS and the second MOSFET 02 is PMOS; if the characterized device is PMOS, the first MOSFET 01 is PMOS and the second MOSFET 02 is NMOS, the first MOSFET 01 is the main MOSFET in the circuit model, and the second MOSFET 02 is a parasitic MOSFET.

[0054] like Figure 3 As shown, Figure 3 A method for establishing a trench MOSFET circuit model based on a physical structure is provided in an embodiment of the present invention, and the method comprises:

[0055] Step S31, constructing a room temperature DC model of the MOSFET circuit model;

[0056] The normal temperature DC circuit model includes a first MOSFET 01, a second resistor 04, and a diode 07;

[0057] The drain of the first MOSFET 01 is connected to the first end of the second resistor 04, the second end of the second resistor 04 leads to the drain D of the circuit model, connected to the output end of the voltage-controlled voltage source, and the two ends of the diode are respectively connected to the source and drain of the first MOSFET 01;

[0058] The first MOSFET 01 uses the SPICE MOS LEVEL 3 model. Before importing data for SPICE model parameter fitting, use the formula R DS(ON) =1 / (W / L*KP*(V GS -V TH )+R DS ), for the macro model parameters KP, V TH and R DS Fitting is performed, where W is the total channel width, which can be estimated using the design layout; L is the total channel length, which can be estimated using the process simulation results; KP is the transconductance coefficient; V TH is the threshold voltage of the fitting, which can be compared with the measured data to determine the reliability of the fitting; R DS is the substrate series resistance. According to experience, for linear conduction low-voltage power MOS, R DS / R DS(ON) The ratio should be between 0.6-0.85.

[0059] According to the estimated KP and R DS / R DS(ON) , the model is simulated, and the simulation objects mainly include the normal temperature output characteristics and normal temperature transfer characteristics, and the complete SPICE parameters of the first MOSFET are obtained.

[0060] Perform SPICE simulation on the diode. Here, you can simulate the DC, CV and temperature characteristics at the same time.

[0061] Step S32, constructing a high and low temperature DC model of the MOSFET circuit model;

[0062] The high and low temperature DC circuit model includes a voltage-controlled voltage source 03, and the voltage-controlled voltage source 03 includes a voltage source 03-1, a current source 03-2 and a third resistor 03-3;

[0063] An input end of the voltage-controlled voltage source 03 is connected to a first end of a first resistor 08;

[0064] The control input end of the voltage-controlled voltage source 03 is connected to the positive electrode of the voltage source and the source electrode of the first MOSFET 01. The control output end of the voltage-controlled voltage source 03 is connected to the first end of the third resistor 03-3 and the outflow end of the current source 03-2. The negative electrode of the voltage source 03-1, the second end of the third resistor 03-3 and the inflow end of the current source 03-2 are connected to the source electrode of the first MOSFET 01, so as to adjust the high-temperature and low-temperature transfer characteristics of the MOSFET device.

[0065] The voltage generated by the third resistor 03-3 connected in parallel with the current source 03-2 is directly compared with the voltage source 03-1, and a voltage difference is output between the gate of the first MOSFET and the external gate of the circuit model. The voltage difference is determined by the high temperature and low temperature curves measured by the MOSFET, thereby realizing a lateral shift of the fitting curve along VGS to achieve accurate fitting.

[0066] To facilitate the solution and avoid introducing excessive gate leakage, the voltage source value can be agreed to be 1V, the current source value can be 1uA, and the resistance value of the third resistor 03-3 can be 1MΩ. Therefore, at room temperature, the SPICE formula of the third resistor 03-3 is: R=RES*(R*(1+TC1*(TT R) +TC2*(TT R ) 2 )). RES is the resistance value, R is the resistance coefficient, the default value is 1.0, TC1 is the temperature coefficient, TC2 is the temperature index, T R is the room temperature constant, which is 25°C by default. Given a gate voltage difference that can make the high and low temperature transfer characteristics conform to the measured curve, the temperature coefficient TC1 and temperature index TC2 of the third resistor 03-3 can be obtained by substituting it into the above formula.

[0067] The power MOSFET circuit model also needs to accurately reflect the R DS(ON) -V GS Characteristics, so it is necessary to perform temperature simulation on the second resistor 04. The second resistor 04 also satisfies RDS=RES*(R*(1+TC1*(TT R )+TC2*(TT R ) 2 )), substituting the simulation and measured data into the formula and performing regression fitting, the temperature coefficient TC1 and temperature index TC2 of the second resistor 04 can be obtained.

[0068] Step S33, constructing a complete capacitance model of the MOSFET circuit model;

[0069] A capacitor model, including a second MOSFET, a first resistor, a first capacitor and a second capacitor;

[0070] The source and drain of the second MOSFET 02 are both connected to the source of the first MOSFET, the gate of the second MOSFET 02 is connected to the output end of the voltage-controlled voltage source 03, and the substrate of the second MOSFET 01 is connected to the second end of the second resistor;

[0071] A first end of the first resistor 08 is connected to the input end of the voltage-controlled voltage source 03, and a second end of the first resistor 08 leads to a gate G of the circuit model;

[0072] A first end of the first capacitor 06 is connected to the gate of the first MOSFET 01, and a second end of the first capacitor 06 is connected to the source of the first MOSFET 01;

[0073] A first end of the second capacitor 05 is connected to the gate of the second MOSFET 02 , and a second end of the second capacitor 05 is connected to the substrate of the second MOSFET 02 .

[0074] The gate-drain capacitance of the MOSFET macro model is simulated, and the difference between the gate-drain capacitance and the actual measured value is taken to obtain the value of the second capacitor 05.

[0075] The gate-source capacitance of the MOSFET circuit model is simulated, and the SPICE model of the second MOSFET 02 is continuously adjusted and compared with the measured value to minimize the standard deviation of the difference of the first capacitance. This difference is used as the value of the first capacitance.

[0076] Compared with the prior art, the technical solution provided by the present application is based on parameter fitting of the current-voltage equation and combined with SPICE simulation technology to realize a SPICE macro model with high precision, high speed and conformity to the physical characteristics of the device. The model is suitable for trench MOSFET devices and is compatible with various SPICE simulators, which improves the simulation accuracy and speed and shortens the design cycle of power supply devices.

[0077] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A trench MOSFET circuit model based on physical structure, characterized in that: It includes a voltage-controlled voltage source, a first MOSFET, a second MOSFET, a first resistor, a second resistor, a first capacitor, a second capacitor and a diode; The input end of the voltage-controlled voltage source is connected to the first end of the first resistor, and the second end of the first resistor leads to the gate of the circuit model; The drain of the first MOSFET is connected to the first end of the second resistor, the second end of the second resistor leads to the drain of the circuit model, and the source of the first MOSFET leads to the source of the circuit model; the substrate of the first MOSFET is connected to the source of the first MOSFET, and the gate of the first MOSFET is connected to the output end of the voltage-controlled voltage source; The source and drain of the second MOSFET are both connected to the source of the first MOSFET, the gate of the second MOSFET is connected to the output end of the voltage-controlled voltage source, and the substrate of the second MOSFET is connected to the second end of the second resistor; A first end of the first capacitor is connected to the gate of the first MOSFET, and a second end of the first capacitor is connected to the source of the first MOSFET; A first end of the second capacitor is connected to the gate of the second MOSFET, and a second end of the second capacitor is connected to the substrate of the second MOSFET; Two ends of the diode are respectively connected to the source and drain of the first MOSFET.

2. A physical structure-based trench MOSFET circuit model as claimed in claim 1, characterized in that: The first MOSFET is of N type and the second MOSFET is of P type; or, The first MOSFET is of P type, and the second MOSFET is of N type.

3. A physical structure-based trench MOSFET circuit model as claimed in claim 2, characterized in that: The voltage-controlled voltage source includes a voltage source, a current source and a third resistor; The control input end of the voltage-controlled voltage source is connected to the positive electrode of the voltage source, the control output end of the voltage-controlled voltage source is connected to the first end of the third resistor and the outflow end of the current source, and the negative electrode of the voltage source, the second end of the third resistor and the inflow end of the current source are commonly connected to the source of the first MOSFET.

4. A physical structure-based trench MOSFET circuit model as claimed in claim 1, characterized in that: The first MOSFET is used to simulate the characteristics of the device's channel current changing with the gate voltage; The second resistor is used to simulate the path series resistance generated by the connection between the epitaxial layer and substrate of the device and the drain of the first MOSFET; The second MOSFET is used to simulate the capacitance formed by using the epitaxial layer as the substrate at the bottom of the device gate and the first MOSFET substrate region as the source and drain; The voltage-controlled voltage source and its control terminal are used to adjust the high-temperature and low-temperature transfer curve characteristics of the analog device; The first resistor is used to adjust the path resistance of the gate of the analog device; The first capacitor and the second capacitor are used to adjust the capacitance effect of the gate-source and gate-drain ports of the analog device; The diode is used to simulate the parasitic body diode between the source and drain of the device.

5. A method for establishing a trench MOSFET circuit model based on physical structure, characterized in that: include, Construct a normal temperature DC model of the MOSFET circuit model; A normal temperature DC circuit model, including a first MOSFET, a second resistor, and a diode; The drain of the first MOSFET is connected to the first end of the second resistor, the second end of the second resistor leads to the drain of the circuit model, the gate of the first MOSFET is connected to the output end of the voltage-controlled voltage source, and the two ends of the diode are respectively connected to the source and drain of the first MOSFET; Construct high and low temperature DC models for MOSFET circuit models; The high and low temperature DC circuit model includes a voltage-controlled voltage source, which includes a voltage source, a current source and a third resistor; The input end of the voltage-controlled voltage source is connected to the first end of the first resistor, the control input end of the voltage-controlled voltage source is connected to the positive electrode of the voltage source, the control output end of the voltage-controlled voltage source is connected to the first end of the third resistor and the outflow end of the current source, and the negative electrode of the voltage source, the second end of the third resistor and the inflow end of the current source are commonly connected to the source electrode of the first MOSFET, so as to adjust the high-temperature and low-temperature transfer characteristics of the MOSFET device; Construct the capacitance model of MOSFET circuit model; A capacitor model, including a second MOSFET, a first resistor, a first capacitor and a second capacitor; The source and drain of the second MOSFET are both connected to the source of the first MOSFET, the gate of the second MOSFET is connected to the input end of the voltage-controlled voltage source, the substrate of the second MOSFET is connected to the second end of the second resistor, the first end of the first resistor is connected to the input end of the voltage-controlled voltage source, the second end of the first resistor leads to the gate of the circuit model, the first end of the first capacitor is connected to the gate of the first MOSFET, and the second end of the first capacitor is connected to the source of the first MOSFET; the first end of the second capacitor is connected to the gate of the second MOSFET, and the second end of the second capacitor is connected to the substrate of the second MOSFET.

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