Method and apparatus for secure key generation

Abstract

A key determination device (13) for determining one or more keys in a cryptographic device (1) is provided, the cryptographic device (1) being configured to execute one or more test programs, the cryptographic device (1) comprising one or more components (11‑i), each component (11‑i) being configured to generate static data and dynamic data, the dynamic data being generated in response to the execution of the one or more test programs, wherein the key determination device (13) comprises: a data extraction unit (131) configured to extract at least a portion of the static data and at least a portion of the dynamic data generated by the one or more components (11‑i), and a key generator (132) configured to combine at least a portion of the static data and at least a portion of the dynamic data, and determine the one or more keys by applying a cryptographic function to the combined data.

Description

Technical Field

[0001] The present invention relates generally to cryptographic systems, and more particularly to methods and apparatus for determining cryptographic keys. Background Art

[0002] Cryptographic devices are used in many fields to ensure the security, authentication, protection and privacy of data during data storage and / or data transmission. With the tremendous and continuous progress in the fields of computer science and computer hardware technology, cryptographic devices have become an indispensable item. Low-cost, fast and small cryptographic devices are deployed in various systems (e.g., communication systems and data processing systems) for many applications.

[0003] Cryptographic devices use one or more keys to generate secure data from original data to prevent hackers or attackers from recovering the original data, and access to the secure data requires access to the keys. Cryptographic devices therefore store sensitive private data (e.g., keys). An attack on cryptographic hardware may have catastrophic effects on data security, including, for example, loss of privacy and loss of protection and security.

[0004] The attacker's goal with respect to the cryptographic device depends on the application. For example, the attacker may aim to learn private parameters (e.g., keys), or attempt to exploit leaked information from the attacked cryptographic device without knowing the private parameters or compromising the normal serviceability of the system.

[0005] In a secure cryptographic device, it is intended that an attacker cannot gain any knowledge of private data by observing or manipulating the inputs / outputs of units that store sensitive data or implement cryptographic mechanisms involving sensitive private data. An attacker may attempt to recover sensitive data by performing an exhaustive search (e.g., an exhaustive search of the entire space of keys if the attacker's goal is to extract one or more keys).

[0006] There are several types of attacks on cryptographic devices, including, for example, hardware attacks that target the physical implementation of the cryptographic algorithm, and network attacks that target the behavior of the cryptographic device when software code / programs are executed on a processor. Exemplary physical hardware attacks include side channel attacks and fault attacks.

[0007] Side-channel attacks use any physically leaked information (e.g., power consumption, processing time, electromagnetic radiation, sound, and infrared radiation) that can be used by an attacker as an additional source of knowledge about the physical implementation of a cryptographic mechanism. The leaked information can reveal characteristics of the internal structure of the attacked device and characteristics of the cryptographic mechanism being run. For example, measuring the power consumption of a cryptographic device over time, or measuring the time required to run a cryptographic mechanism or to run the computational operations used to generate keys, may disclose information about private data.

[0008] In a glitch attack, the attacker forces the cryptographic device to perform some erroneous operation, with the goal of exploiting any leaked information during the erroneous behavior of the attacked device to determine the private parameters involved during the operation of the erroneous operation. There are several methods for causing glitch attacks, including, for example, providing noisy power or clock signals, incorrect voltages, or excessive temperatures.

[0009] Cyber ​​attacks exploit machine code execution performed by a processing element / component / unit to access and gain control of a victim device. In particular, memory-based attacks on hardware / software designs rely on corrupting memory addresses (locations) to hijack control flow. For example, arbitrary program execution can be achieved by corrupting code / program memory locations (e.g., return addresses).

[0010] There are several protection techniques against hardware attacks and network attacks.

[0011] Side channel attacks can be countered by providing cryptographic mechanisms and algorithms that run in constant time or developing cryptographic programs that work under a constant program flow (regardless of the security data). These techniques allow mitigation of side channel attacks. However, their practical implementation is not feasible in applications where hardware resources (storage space, processing power) are limited, for example due to cost or size considerations. In addition, data values ​​manipulated by the algorithm may also be leaked. Therefore, other side channel mitigation solutions have been disclosed in the following documents:

[0012] - "S.Chari,CSJutla,JRRao and P.Rohatgi.Towards Sound Approaches to Counteract Power-Analysis Attacks.Advances in Cryptology-CRYPTO.Volume 251666of the Series Lecture Notes in Computer Science.Pages 398-412.1999";

[0013] - "S.Chari,JRRao and P.Rohatgi.Template Attacks.Cryptographic Hardwareand Embedded Systems(CHES).Volume 2523 of the Series Lecture Notes in ComputerScience.Pages 13-28.2003"; and

[0014] - "JS.Coron and L.Goubin.On Boolean and Arithmetic Masking againstDifferential Power Analysis.Cryptographic Hardware and Embedded Systems(CHES).Volume 1965of the Series Lecture Notes in Computer Science.Pages231-237.2000".

[0015] These solutions are based on randomization techniques such as secret splitting or masking schemes, which aim to add a layer of protection to the cryptographic mechanism through the use of random unknowns, which prevent accidental recipients or attackers from predicting secret values ​​based on leaked information. Masking schemes are efficient when the attacker uses physical leaked information observed at one moment. However, for some attacks based on multiple leaked information in multiple moments (e.g., high-order differential analysis), randomization techniques cannot prevent the attacker from successfully recovering the desired secret value (in "P. C Kocher, J. Jaffe, and B. Jun. Differential Power Analysis. Advances in Cryptology-CRYPTO. Volume 1666 of the Series Lecture Notes in Computer Science. Pages 388-297, 1999").

[0016] Protection against fault attacks in hardware or software aims to help circuits avoid detection and / or correction faults. There are passive protections and active protections. Exemplary passive protections include randomization of clock cycles, buses, and memory encryption. Exemplary active protections include the use of sensors and detectors to infer abnormal circuit behavior.

[0017] Protection against cyber attacks includes:

[0018] -Antivirus programs to detect / identify the presence of malware code;

[0019] -Use of canaries to detect overflows;

[0020] - Dynamic information flow tracking for identifying and tracking unsafe data;

[0021] - Combined with non-executable stack and heap deployment, address space layout randomization, and stack canaries, using virtual memory addresses instead of physical addresses; such protection measures provide memory access constraints and prevent attackers from code injection and / or execution, and

[0022] -Control flow integrity based on detection of any modification of flow control.

[0023] Existing protections against hardware and software attacks that target the extraction of cryptographic keys stored in / used by cryptographic devices provide partial protection and are insufficient to fully protect cryptographic devices.

[0024] Therefore, there is a need to develop efficient key generation techniques that prevent attacks aimed at recovering the keys implemented in cryptographic devices. Summary of the invention

[0025] To solve these and other problems, a key determination device for determining one or more keys in a cryptographic device is provided, the cryptographic device being configured to execute one or more test programs, the cryptographic device comprising one or more components, each component being configured to generate static data and dynamic data, the dynamic data being generated in response to the execution of the one or more test programs. Advantageously, the key determination device comprises:

[0026] - a data extraction unit configured to extract at least a portion of static data and at least a portion of dynamic data generated by one or more components; and

[0027] - a key generator configured to combine at least a portion of the static data and at least a portion of the dynamic data and to determine one or more keys by applying a cryptographic function to the combined data.

[0028] In some embodiments, the cryptographic device may be configured to execute one or more test procedures continuously.

[0029] In another embodiment, the cryptographic device may be configured to periodically execute one or more test procedures according to predefined time intervals.

[0030] In yet another embodiment, the execution of the one or more test programs may be event driven, with the cryptographic device being configured to execute the one or more test programs in response to one or more events.

[0031] In yet another embodiment, the cryptographic device may be configured to execute one or more test procedures in response to an interrupt action or a user-initiated action.

[0032] In some embodiments, execution of the one or more test programs may be implemented by a cryptographic device to perform a system startup test, the cryptographic device being configured to execute the one or more test programs each time the system is started.

[0033] In one embodiment, execution of one or more test programs may be implemented by a cryptographic device to perform memory tests for testing one or more memory units implemented in the cryptographic device.

[0034] In another embodiment, execution of one or more test programs may be implemented dependent on one or more test parameters, the test parameters being selected from the group consisting of test duration and test complexity.

[0035] A component in the one or more components may be a processor or a memory.

[0036] In particular, the key generator may be a random number generator or a physically unclonable function.

[0037] In some embodiments, a cryptographic device may be configured to use one or more keys in one or more applications including data encryption, data decryption, message authentication, and digital signatures.

[0038] Data encryption may be performed using a symmetric encryption algorithm selected from the group consisting of DES, 3DES, AES, and RC4.

[0039] Alternatively, data encryption may be performed using an asymmetric encryption algorithm, such as RSA or ECDSA.

[0040] In some embodiments, one or more keys may be stored within the cryptographic device, or shared within the cryptographic device, or shared with an external device, or shared with an external system.

[0041] There is further provided a method for determining one or more keys, the method comprising:

[0042] - execute one or more test procedures;

[0043] - generating static data and dynamic data, the dynamic data being generated in response to execution of one or more test programs.

[0044] Advantageously, the method comprises:

[0045] - extracting at least a portion of the static data and at least a portion of the dynamic data;

[0046] - combining at least a portion of the static data and at least a portion of the dynamic data; and

[0047] -Determining one or more keys by applying a cryptographic function to the combined data.

[0048] Advantageously, according to various embodiments of the present invention, determining the key based on dynamic data representing the dynamic behavior of the cryptographic device protects the cryptographic device from attacks aimed at recovering the key. The reliance on the dynamic behavior of the cryptographic device requires an attacker to reverse engineer the entire system to recover the key.

[0049] Advantageously, various embodiments of the present invention provide efficient techniques for enhancing the security and protection of cryptographic devices by increasing the difficulty of reverse engineering efforts aimed at extracting cryptographic keys.

[0050] Advantageously, various embodiments of the present invention provide for secure initialization of cryptographic devices.

[0051] Additional advantages of the present invention will become apparent to those skilled in the art upon examination of the drawings and detailed description, which are provided for illustrative purposes only. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate various embodiments of the invention together with the general description of the invention given above and the detailed description of the embodiments given below.

[0053] Figure 1 is a block diagram illustrating the structure of a cryptographic device according to some embodiments of the present invention.

[0054] Figure 2 is a flow chart illustrating a method of determining one or more keys based on static and dynamic data generated in response to execution of one or more test programs. DETAILED DESCRIPTION

[0055] Embodiments of the present invention provide apparatus and methods for protecting cryptographic devices from hardware and / or software attacks that are intended to recover cryptographic keys stored in / generated by the cryptographic devices. In particular, the apparatus and methods of the present invention provide for the determination of cryptographic keys by relying on dynamic data dynamically generated at the cryptographic device and representing the dynamic behavior of the cryptographic device.

[0056] A cryptographic device refers to a device that implements hardware and / or software cryptographic mechanisms to ensure data and / or signal security, authentication, protection and / or privacy.

[0057] The secure cryptographic devices and methods according to various embodiments of the present invention can be implemented in a variety of devices or systems (e.g., industrial, information, and consumer devices). The secure cryptographic devices and methods according to embodiments of the present invention can be used in a wide range of applications (e.g., civil or military communication applications or data processing applications), including, for example:

[0058] -Digital electronics;

[0059] - Communications used to ensure secure transmission of data over insecure transmission channels;

[0060] -Computing networks / systems used to protect data center interconnections;

[0061] -Cloud computing applications and cloud servers;

[0062] - Communication applications (e.g., communication on a wire-tap channel);

[0063] - The automotive industry for ensuring protection against theft;

[0064] - Service provider systems for providing restricted access;

[0065] - Mobile phone devices for authenticating control and access to batteries and accessories;

[0066] -Banking for protecting bank accounts and financial transactions;

[0067] - Medicine, for the protection of medical data and medical devices (e.g. implantable medical devices) that can be implanted in the body to treat a disease or monitor the state of function of some body part (e.g. pacemakers, defibrillators for monitoring and treating heart disease, brain monitoring or stimulation devices (e.g. neurostimulators) for deep brain stimulation in cases such as epilepsy or Parkinson's disease, drug delivery systems, biosensors);

[0068] -Sensitive applications in FPGAs, hardware security modules, and electronic components embedded in smart cards or electric vehicles (EVs);

[0069] -etc.

[0070] In the context of secure boot, the generation of keys when the device boots up is crucial. Security-critical devices really need to protect themselves when they are at rest. This is because when the power is cut, an attacker may be able to observe the contents of the memory with a microscope and even delayer different metallization layers to more easily access the silicon for better observability. Some attackers may also try to modify the code in the memory. In this context, a strong defense consists of encrypting and authenticating the memory. Both operations require keys: one for encryption and the other for authentication functions. This operation is called converting "red" (sensitive) information into "black" (non-sensitive) information. However, in order to prevent attackers from trying to read the keys in the first place, the keys should not be easily found. Otherwise, after such a step, the attacker will be able to decrypt the memory or change them while regenerating the value authentication tags. Therefore, a strictly protected master key is needed. The key can be called the basis of the root of trust (RoT).

[0071] refer to Figure 1 , showing an exemplary implementation of the security cryptographic device 1 in the system 100 .

[0072] System 100 can be, for example, a communication system (e.g., digital, wired, wireless, cellular, optical, satellite, acoustic, and molecular communication systems), a data processing system (e.g., online sales systems, financial systems, electronic passport systems, banking), a data storage system (e.g., a database), a recording system (e.g., magnetic and optical recording), a positioning system, etc.

[0073] The cryptographic device 1 may be any device, computer, computing machine or embedded system programmed and / or programmable to execute cryptographic mechanisms or algorithms involving the use, generation and / or storage of one or more cryptographic keys.

[0074] Exemplary cryptographic devices 10 include, but are not limited to:

[0075] - Smart cards, tokens for storing keys (e.g., wallets), smart card readers (e.g., automated teller machines (ATMs)), which are used, for example, in financial transactions, restricted access, telecommunications, military applications, secure communication equipment, and TV set-top boxes;

[0076] - Electrical and digital electronic devices, such as RFID tags and electronic keys;

[0077] -Embedded secure element;

[0078] - Computers (e.g., desktops and laptops), tablets;

[0079] - Routers, switches, printers;

[0080] - Mobile phones, such as smartphones, base stations, relay stations, satellites;

[0081] - Internet of Things (IoT) devices, robots, drones; and

[0082] - Voice recorders, multimedia players, removable storage devices (e.g. memory cards and hard disks), where login access is monitored via a password mechanism.

[0083] In the application of the present invention to a communication system, the cryptographic device 1 may be fixed or mobile, and is configured to operate in a wired, wireless or fiber-based communication network.

[0084] Furthermore, the cryptographic device 1 may be a standalone device, or may be connected to an external device, machine or system.The cryptographic device 1 may be implemented, for example, in a computer networking system (using, for example, one or more small or large area wired or wireless access networks).

[0085] One or more tests may be implemented to test the cryptographic device 1, for example in order to diagnose the serviceability and / or correct the operation of the cryptographic device 1. In particular, design tests may be performed during design or manufacture of the cryptographic device 1 or during operability of said cryptographic device 1.

[0086] The cryptographic device 1 can be designed to be tested using an external test device (or "equipment") commonly referred to as "automatic test equipment" or "automated test equipment" (ATE). Automatic test equipment is configured to perform tests on cryptographic devices, which are referred to as "device under test" (DUT), "equipment under test" (EUT) or "unit under test" (UUT). Automatic test equipment implements a process for quickly performing measurements and analyzing test results. Automated test equipment can be a simple computer-controlled digital multimeter, or a complex system containing dozens of complex test instruments (real or simulated electronic test equipment) that can automatically test and diagnose faults in complex electronic packaging parts or wafer testing, including systems on chip and integrated circuits.

[0087] According to some embodiments of the present invention, the cryptographic device 1 may be a device, a computer, a computing machine or an embedded system that is programmed and / or programmable to self-execute one or more designed test programs without relying on external test equipment.

[0088] Design testing, known as "built-in self-test" (BIST) or "built-in test" (BIT), is a mechanism that enables a machine to test itself without reliance on external test equipment.

[0089] The BIST may be designed to meet several requirements including high reliability, low maintenance cycles, or subject to several constraints including limited technician accessibility and increased testing costs during manufacturing.

[0090] By reducing test cycle duration and test / probe setup complexity, BIST provides a reduction in complexity and cost over reliance on external test equipment to test the device / machine.

[0091] Built-in self-test is used to test the functionality of several devices and systems, including but not limited to those used in automotive, avionics, electronics, and medical equipment.

[0092] In particular, automotive equipment performs BIST to enhance safety and reliability. For example, most vehicles with anti-lock brakes test them once every safety interval. If the anti-lock brake system has a broken wire or other fault, the brake system reverts to functioning as a normal brake system. Most automotive engine controllers incorporate a "limp mode" for each sensor so that if a sensor or its wiring fails, the engine will continue to operate.

[0093] In avionics, BIST is performed in civil and military aircraft during the manufacturing phase or during flight to minimize the ground time required to repair detected faulty equipment and to increase the level of safety of the aircraft systems.

[0094] Exemplary applications of BIST in electronics include BIST performed by integrated circuits and computers. BIST is used in integrated circuit manufacturing to allow faster, cheaper integrated circuit manufacturing testing. Computers including embedded systems perform BIST to self-test their processors and / or memory and / or software.

[0095] In medicine, medical devices perform BIST to test themselves for continued safety. Safety-critical devices often define a "safety interval" which is a period of time short enough to prevent harm from occurring. Medical devices perform BIST on the most critical functions at least once per safety interval.

[0096] Various embodiments of the present invention provide an improved secure cryptographic device in which the determination of one or more keys depends on data generated during the execution of a built-in self-test. More specifically, the key generation is based on dynamic data generated by components implemented in the cryptographic device in response to the built-in self-test being executed.

[0097] refer to Figure 1, shows a key determination device 13 implemented in a cryptographic device 1 for determining one or more keys in the cryptographic device 1. The cryptographic device 1 is configured to execute one or more test programs corresponding to the designed test. The cryptographic device 1 includes one or more components 11-i (where i=1,...,N), each component 11-i being configured to generate static data and dynamic data in response to the execution of one or more test programs corresponding to the designed test performed by the cryptographic device 1. The key determination device 13 includes:

[0098] a data extraction unit 131 configured to extract at least a portion of static data and at least a portion of dynamic data generated by one or more components 11 - i, and

[0099] A key generator 133 configured to determine combined data by combining the extracted at least a portion of the static data and at least a portion of the dynamic data, and to determine one or more keys by applying a cryptographic function to the combined data.

[0100] The cryptographic device 1 may be configured to perform one or more design tests to reduce the likelihood of hardware and / or software failures by predicting such failures and identifying possible failure points. Failure points may occur at the processor and / or circuits around the processor or one or more peripheral devices and / or memory and / or software.

[0101] When a processor failure occurs, it is unlikely that any instructions will be executed. Design testing in such an event is therefore irrelevant. Since such failures are most likely to occur at power-up, the system monitor / manager / hypervisor may notice and handle such failures.

[0102] In some embodiments, where the cryptographic device 1 is a multi-processor device (the processor is a single-core processor or a multi-core processor) in which two or more processors are separately implemented on a chip in a manner in which a failure of one of the processors will not affect the remaining processors, the cryptographic device 1 can be configured to execute one or more test programs corresponding to one or more design tests to verify and / or identify whether any failure has occurred at one of the two or more processors or at one or more of the cores of the multi-core processor.

[0103] The results of the design tests may be displayed on a panel (which is part of the cryptographic device 1 ), output to an external device connected to the cryptographic device 1 , or stored for future retrieval by a diagnostic tool or system monitor / manager / hypervisor.

[0104] In some embodiments, the cryptographic device 1 may be configured to continuously execute one or more test programs corresponding to the designed test. In such embodiments, the data extraction unit 131 may be configured to periodically perform extraction of at least a portion of static data and at least a portion of dynamic data generated by one or more components 11-i at time intervals (e.g., specific, predefined, predetermined, or selected time intervals).

[0105] In some embodiments, the cryptographic device 1 may be configured to periodically execute one or more test procedures corresponding to a designed test according to a predefined time interval (e.g., a designed test time interval). The designed test interval may, for example, correspond to a security interval for a cryptographic device used in, for example, medical applications.

[0106] In some embodiments, the execution of one or more test programs may be event driven, and the cryptographic device 1 is configured to execute one or more test programs corresponding to event driven design tests in response to one or more events. Exemplary event driven design tests include design tests performed at aircraft systems after the aircraft lands.

[0107] In some embodiments, the cryptographic device 1 may be configured to execute one or more test programs corresponding to a designed test in response to an interrupt action or a user-initiated action.

[0108] In some embodiments, the data extraction unit 133 can be configured to extract static data and dynamic data based on a data volume threshold, which is previously determined depending on the security level / performance level / key calculation complexity and / or delay required to generate one or more keys based on the extracted data.

[0109] In some embodiments, the duration and / or frequency of static and dynamic data extraction may be configurable / configured to meet a target performance / security tradeoff.

[0110] In some embodiments, the duration and / or frequency of static and dynamic data extraction may be performed by a combination of at least some of the aforementioned features.

[0111] In some embodiments, the execution of one or more test programs may be implemented by the cryptographic device 1 to perform a system startup test at each system startup immediately after the cryptographic device 1 is powered on. In such an embodiment, the key generator 133 may be configured to determine one or more keys for protecting the system startup and ensuring secure initialization of the cryptographic device 1 based on system startup data generated by one or more components 11-i included in the cryptographic device 1.

[0112] System startup testing may include one or more test procedures to perform one or more of the following actions:

[0113] - verifying the integrity of the registers of one or more processing units (or processors) included in the cryptographic device 1;

[0114] - Verify the integrity of some components (e.g., timers and interrupt controllers);

[0115] - Find the main memory of the cryptographic device 1, determine its size and verify it;

[0116] - Identify, organize and select equipment / components available for launch;

[0117] -Discover, initialize and catalog all system buses and components;

[0118] - Provide a user interface for system configuration;

[0119] In some embodiments, a successful system startup test may be followed by the loading of an operating system and / or the initialization of one or more components referred to as “system startup components.” System startup components may include, for example, peripheral devices.

[0120] Advantageously, the test data may not be recorded so that an invasive attack aimed at recovering the key would require reversing the entire chip, since the key is constructed by reading at various locations in the chip.

[0121] In some embodiments, execution of one or more test programs may be implemented by the cryptographic device 1 to perform a memory test, the cryptographic device 1 being configured to perform the memory test to test one or more memory units implemented in the cryptographic device 1 .

[0122] Memory testing can be performed to detect / identify memory failures. Memory failures can be transient, or they can be hard. Transient failures / errors are non-permanent failures that occur from time to time and are nearly impossible to prevent. Hard failures are permanent malfunctions that can appear in three forms:

[0123] 1) The memory does not respond at all to being addressed;

[0124] 2) One or more bits are stuck at "0" or "1";

[0125] 3) There is crosstalk; addressing one bit affects one or more other bits.

[0126] A memory test may be performed by the cryptographic device 1 to detect such hard memory failures.Such a memory test may be performed at system startup and / or as a background task during operability of the cryptographic device 1 .

[0127] Memory testing may be advantageously performed at system startup, which is a time when memory is most likely to fail and therefore memory that does not yet contain potentially sensitive data is tested.

[0128] As long as interruptions in program execution are tolerated, background memory testing can be performed by testing individual bytes / words of memory during operability of the cryptographic device 1. Such memory testing can be performed, for example, during idle time or as a background task when no program / instructions are being executed.

[0129] In some embodiments, the execution of one or more test procedures may be implemented in the cryptographic device 1 depending on one or more test parameters, the test parameters being selected from the group consisting of test duration and test complexity.

[0130] In one embodiment, a component 11 - i among one or more components 11 - i (where i=1, . . . , N) included in the cryptographic device 1 may be selected from the group consisting of a processor, a memory unit, a cryptographic unit, and a peripheral device.

[0131] A processor refers to a component configured to execute instructions of one or more programs stored in a memory unit using one or more processing units (referred to as "cores") by performing arithmetic, logic, control, and input / output operations specified by the instructions.

[0132] According to some embodiments, the cryptographic device 1 may be a multi-processor including at least two processors 11 - i .

[0133] In some embodiments, the processor 11-i may be a single-core processor including a single processing unit ( Figure 1 not shown).

[0134] In other embodiments, processor 11-i may be a multi-core processor including multiple cores configured to execute tasks at a given time (e.g., as used in embedded systems, digital signal processing, or graphics processing units). Tasks may be software processes and / or threads scheduled by an operating system.

[0135] In such an embodiment, the processor 11-i may be a single computing component that is configured to run multiple instructions simultaneously on separate cores, thereby increasing the overall speed of program execution suitable for parallel computing. The different cores may be integrated onto a single integrated circuit die (also referred to as a chip multiprocessor), or onto multiple dies in a single chip package.

[0136] Furthermore, the cores in the multi-core processor 11 - i may or may not share memory units (eg, cache memories). In some embodiments, the cores may be configured to implement a message passing or shared memory inter-core communication method.

[0137] In an embodiment where the cryptographic device 1 is a multi-processor, the cryptographic device 1 may include one or more single-core processors and one or more multi-core processors.

[0138] Furthermore, in some embodiments in which the cryptographic device 1 includes a plurality of processors 11 - i , the processors 11 - i may be concentrated in a space or distributed in a space such as a server cluster and a server farm.

[0139] According to some embodiments, the cryptographic device 1 may include at least one virtual processor 11 - i , which is a physical central processing unit assigned to a virtual machine (eg, in a cloud computing application, a cloud server, etc.).

[0140] In particular, the processor 11-i may include:

[0141] - one or more processing units ( Figure 1 ), which is configured to execute program instructions; each processing unit may include: an arithmetic and logic unit (ALU) configured to perform arithmetic and logic operations, and a processor register configured to provide operands to the ALU and store the results of the ALU operation; and

[0142] -Control Unit( Figure 1 ), which is configured to decode program instructions and arrange / coordinate the extraction and execution of instructions (from a memory unit or storage device) by directing the coordinated operation of the ALU, registers and other components of the cryptographic device 1.

[0143] Processor registers may form small and very fast memory units (as opposed to slower RAM main memory) that are used to speed up program execution by providing fast access to commonly used values. Processor registers may specifically include certain internal registers - registers that are not accessible by instructions but are used only internally for processor operations, including:

[0144] -Program Counter, also called "Instruction Register" ( Figure 1 (not shown): The program counter may indicate the position of the processor 11-i in its instruction sequence. Depending on the particular system, the program counter may be configured to hold the address of the instruction being executed or the address of the next instruction to be executed;

[0145] -Memory Address Registers ( Figure 1), which is configured to: store a memory address from which data will be fetched to the processor 11-i (i.e., the memory location of the data to be loaded from the memory unit to the processor 11-i), or an address to which data will be sent for storage (i.e., the memory location where the data will be stored), and

[0146] -Memory Data Registers ( Figure 1 ), which is configured to store data extracted / retrieved from a memory unit (either from a processor cache or from a memory unit) and ready to be processed, or data waiting to be stored in other memory units.

[0147] According to some embodiments, the cryptographic device 1 may further include a memory bus configured to route data and / or metadata between the one or more components 11 - i .

[0148] The cryptographic unit 11 - i may be a processing unit or a storage unit configured to generate / store / manage / use cryptographic data and a key different from a key generated by the key generator 133 .

[0149] The cryptographic unit 11-i may be a secure cryptographic processor 11-i that is dedicated to performing cryptographic operations to protect sensitive data in memory from hardware and / or software attacks. The cryptographic processor 11-i may be configured to perform cryptographic mechanisms for encryption, integrity, and replay protection. Advantageously, memory encryption achieves protection of the confidentiality of memory-resident data, integrity protection achieves prevention of attackers from making hidden modifications to encrypted data stored in memory, and replay protection achieves elimination of undetected temporary replacements of encrypted data. Exemplary cryptographic processors include smart cards that are used, for example, in financial transactions, restricted access, telecommunications, military applications, secure communications equipment, ATMs, TV set-top boxes, and the like.

[0150] According to some embodiments, the memory unit 11 - i may include:

[0151] - a data storage device configured to store data ( Figure 1 not shown);

[0152] -Instruction Memory ( Figure 1 ), which is configured to store instructions of a program (including instructions of a test program); and

[0153] - Metadata Storage ( Figure 1 ), which is configured to store metadata associated with each memory location (corresponding to a data or instruction memory location).

[0154] In order to speed up the processing of programs and reduce the average cost (time or effort) of accessing data from the memory unit 11-i, a smaller and faster cache memory may be used.

[0155] Thus, the memory unit 11-i may include a processor cache associated with each processor implemented in the cryptographic device 1, the processor cache being configured to access data and / or instructions included in a program to be executed by the processor associated therewith. The processor cache may be configured to store copies of data and / or instructions from frequently requested locations in the memory unit 11-i, so that they are immediately available to the processor when needed. In particular, the data stored in the processor cache may be the result of an earlier calculation, or a copy of data stored elsewhere.

[0156] Processor caches may include different independent caches, including data caches and / or instruction caches.

[0157] In some embodiments, processor caches may be organized into a hierarchy of cache levels.

[0158] According to some embodiments, the processor cache may be located internal to the processor 11 - i chip (internal cache).

[0159] Alternatively, the processor cache may be located external to the processor 11-i chip (external cache).

[0160] According to some embodiments, the memory unit 11 - i may correspond to a main memory of the cryptographic device 1 .

[0161] According to some embodiments, the memory cell 11 - i may be selected from the group consisting of a volatile memory, a nonvolatile memory, a combination of both a volatile memory cell and a nonvolatile memory cell.

[0162] The volatile memory may use one or more of RAM, DRAM (e.g., DDR, SDRAM), SRAM, T-RAM, and Z-RAM. Volatile memory is generally advantageous in terms of improved read / write performance, and has lower cost / occupancy compared to non-volatile writable memory.

[0163] The non-volatile memory may use one or more of a mask ROM, a PROM, an EPROM, an EEPROM, an NVRAM, a flash memory, a solid-state storage device, nvSRAM, a FeRAM (ferroelectric RAM), an MRAM (magnetic RAM), a PRAM. Non-volatile memory is often advantageous in providing access to previously stored information after a reboot and / or a restart.

[0164] According to some embodiments, the components 11 - i included in the cryptographic device 1 may be internal or external peripheral devices including input devices, output devices, and input / output.

[0165] Input devices can be configured to interact with the computer or to send data from a user to the computer. Exemplary input devices include keyboards, computer mice, graphics tablets, barcode readers, image scanners, microphones, webcams, game controllers, light pens, and digital cameras.

[0166] The output device may be configured to provide output to a user from the cryptographic device 1. Exemplary output devices include a computer monitor, a printer, a projector, computer speakers, a webcam.

[0167] The input / output device may be configured to perform both functions. An exemplary input / output device includes a touch screen.

[0168] In some embodiments, the key generator 123 may be a random number generator or a physically unclonable function.

[0169] In some embodiments, the random number generator may be selected from the group consisting of a pseudo-random number generator and a true random number generator.

[0170] According to some embodiments, the cryptographic device 1 may be configured to use one or more keys determined by the key generator 133 in one or more applications including data encryption, data decryption, message authentication, and digital signature.

[0171] Data encryption may use one or more encryption mechanisms to implement one or more of error correction codes (eg, Hamming codes, BCH codes), hash functions, and key-based cryptographic algorithms (using symmetric or asymmetric keys).

[0172] The symmetric encryption algorithm may be selected from the group consisting of DES (Data Encryption Standard), 3DES, AES (Advanced Encryption Standard), and RC4 (Rivest Cipher 4).

[0173] The asymmetric encryption algorithm may be selected from the group consisting of RSA (Rivest-Shamir-Adleman) and ECDSA (Elliptic Curve Digital Signature Algorithm).

[0174] In some embodiments, the encryption and decryption algorithms may be selected based on a tradeoff between performance, memory, and security levels required by the application and / or a defined user.

[0175] The key generator 133 can be configured to determine one or more keys depending on one or more secret parameters, such as a password or an external secret value, for the purpose of sharing one or more keys determined by the cryptographic device 1, for example between the cryptographic device 1 and one or more external devices / machines / users connected to the system 100.

[0176] In one embodiment, one or more keys may be stored within a cryptographic device, shared within a cryptographic device, shared with external devices, or shared with other systems (eg, user systems).

[0177] The key may be destroyed upon reboot and / or shutdown, and may be initialized (in a deterministic or random manner) upon initialization of the cryptographic device 1 .

[0178] refer to Figure 2 , a method for determining one or more keys is shown, the method comprising:

[0179] - At step 21, performing the design test by executing one or more test programs;

[0180] - at step 23, generating static data and dynamic data in response to the design tests being performed;

[0181] - at step 25, extracting at least a portion of the generated static data and at least a portion of the generated dynamic data;

[0182] - at step 27, determining combined data by combining the extracted at least part of the generated static data and the extracted at least part of the generated dynamic data; and

[0183] - At step 29, one or more keys are determined by applying a cryptographic function to the combined data.

[0184] One or more design tests may be performed to predict / prevent / identify any hardware or software failures.

[0185] One or more test procedures corresponding to the designed tests may be executed continuously, or periodically according to predefined designed test time intervals, or in response to one or more events, or in response to an interrupt action or a user-initiated action.

[0186] In some embodiments, extraction of static and dynamic data may be performed based on a data volume threshold that is previously determined depending on security level / performance level / key calculation complexity and / or the delay required to generate one or more keys based on the extracted data.

[0187] In some embodiments, the duration and / or frequency of static data and dynamic data extraction may be configurable / configured to meet a target performance / security tradeoff.

[0188] In some embodiments, the duration and / or frequency of static data and dynamic data extraction may be performed by a combination of at least some of the aforementioned features.

[0189] In some embodiments, the design test may be a system startup test that is performed each time the system is started.

[0190] In some embodiments, the design test may be a memory test performed to detect / identify memory failures.

[0191] In some embodiments, the designed test may be performed according to one or more designed test parameters. The designed test parameter may be a test duration (also referred to as "designed test duration") or a test complexity (also referred to as "designed test complexity").

[0192] In some embodiments, one or more keys may be determined using a cryptographic function, which may be a random number generator or a physically unclonable function.

[0193] In some embodiments, the random number generator may be a pseudo-random number generator or a true random number generator.

[0194] In some embodiments, one or more keys may be used in one or more applications including data encryption, data decryption, message authentication, and digital signatures.

[0195] Data encryption may use one or more encryption mechanisms that implement one or more of error-correcting codes (eg, Hamming codes, BCH codes), hash functions, and key-based cryptographic algorithms (using symmetric or asymmetric keys).

[0196] The symmetric encryption algorithm may be selected from the group consisting of DES, 3DES, AES, and RC4.

[0197] The asymmetric encryption algorithm can be RSA or ECDSA.

[0198] In some embodiments, the encryption and decryption algorithms may be selected based on the desired tradeoff between performance, memory, and security levels required by the application and / or a defined user.

[0199] In some embodiments, one or more keys may be determined depending on one or more secret parameters (eg, a password or an external secret value).

[0200] In some embodiments, the determined key or keys may be stored for further use / sharing / distribution.

[0201] The methods described herein may be implemented by computer program instructions provided to a processor of any type of computer to produce a machine having a processor that executes instructions to implement the functions / actions specified herein. These computer program instructions may also be stored in a computer-readable medium that can direct a computer to operate in a particular manner. To this end, the computer program instructions may be loaded onto a computer to cause the execution of a series of operational steps and thereby produce a computer-implemented process such that the executed instructions provide a process for implementing the functions specified herein.

[0202] Although embodiments of the present invention have been illustrated by the description of various examples, and although these embodiments have been described in considerable detail, it is not the intention of the applicant to limit or in any way restrict the scope of the appended claims to such embodiments. Where appropriate, some of those embodiments may be advantageously combined. Additional advantages and modifications will be apparent to those skilled in the art. The present invention in its broader aspects is therefore not limited to the specific details, representative methods, and illustrative examples shown and described.

Claims

1. A key determination device (13) for determining one or more keys in a cryptographic device (1), the cryptographic device (1) being configured to execute one or more test programs, the cryptographic device (1) comprising one or more components (11-i), each component (11-i) being configured to generate static data and dynamic data, the dynamic data being generated in response to the execution of the one or more test programs and representing the dynamic behavior of the cryptographic device, wherein The key determination device (13) comprises: - a data extraction unit (131) configured to extract at least a portion of the static data and at least a portion of the dynamic data generated by the one or more components (11-i) according to a data volume threshold value, the data volume threshold value being previously determined depending on a security level, a performance level, a key calculation complexity and a delay required for generating one or more keys based on the extracted data; and - a key generator (133) configured to combine said at least part of said static data and said at least part of said dynamic data and to determine said one or more keys by applying a cryptographic function to the combined data.

2. The key determination device (13) according to claim 1, wherein: The cryptographic device (1) is configured to execute the one or more test programs continuously.

3. The key determination device (13) according to claim 1, wherein: The cryptographic device (1) is configured to periodically execute the one or more test procedures according to a predefined time interval.

4. The key determination device (13) according to claim 1, wherein: The execution of the one or more test programs is event driven, the cryptographic device (1) being configured to execute the one or more test programs in response to one or more events.

5. The key determination device (13) according to claim 1, wherein: The cryptographic device (1) is configured to execute the one or more test programs in response to an interrupt action or an action initiated by a user.

6. The key determination device (13) according to claim 1, wherein: The execution of one or more test programs is implemented by the cryptographic device (1) to perform a system startup test, and the cryptographic device (1) is configured to execute the one or more test programs each time the system is started.

7. The key determination device (13) according to claim 1, wherein: The execution of one or more test programs is implemented by the cryptographic device (1) to perform a memory test for testing one or more memory units implemented in the cryptographic device (1).

8. The key determination device (13) according to claim 1, wherein: The execution of the one or more test programs is effected dependent upon one or more test parameters selected from the group consisting of test duration and test complexity.

9. The key determination device (13) according to claim 1, wherein: A component among the one or more components is a processor or a memory.

10. The key determination device (13) according to claim 1, wherein: The key generator (133) is a random number generator or a physically unclonable function.

11. The key determination device (13) according to claim 1, wherein: The cryptographic device (1) is configured to use the one or more keys in one or more applications including data encryption, data decryption, message authentication, and digital signature.

12. The key determination device (13) according to claim 11, wherein: Data encryption is performed using a symmetric encryption algorithm selected from the group consisting of DES, 3DES, AES, and RC4.

13. The key determination device (13) according to claim 11, wherein: Data encryption is performed using an asymmetric encryption algorithm, which is either RSA or ECDSA.

14. The key determination device (13) according to claim 1, wherein: The one or more keys are stored within the cryptographic device or shared within the cryptographic device, or shared with an external device or shared with an external system.

15. A method for determining one or more keys, the method comprising: - executing (21) one or more test procedures; - generating (23) static data and dynamic data, said dynamic data being generated in response to said execution of said one or more test programs and representing dynamic behavior of a cryptographic device; Wherein, the method comprises: - extracting (25) at least a portion of the static data and at least a portion of the dynamic data according to a data volume threshold value, the data volume threshold value being previously determined depending on the security level, performance level, key calculation complexity and latency required to generate one or more keys based on the extracted data; - combining (27) said at least part of said static data and said at least part of said dynamic data; and - determining (29) the one or more keys by applying a cryptographic function to the combined data.

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