33-bit adder and its implementation method, operation circuit and chip

Abstract

The embodiment of the present application provides a 33-bit adder and its implementation method, operation circuit and chip, the 33-bit adder includes N carry modules and a summation module; each carry module corresponds to multiple bits in a first addend and a second addend, and includes a preprocessing unit and multiple carry calculation units; the preprocessing unit included in the nth carry module is used to preprocess multiple bits in the corresponding first addend and the second addend; the multiple carry calculation units included in the nth carry module are used to perform operations based on the preprocessing results and the inter-stage carry parameters of the n-1th carry module to generate the carry output of each bit corresponding to the nth carry module and the inter-stage carry parameters of the nth carry module, basically realizing parallel calculation of the carry output of each bit in 33-bit binary data for summation operation, thereby shortening the duration of the entire calculation process and improving the calculation speed.

Description

Technical Field

[0001] Embodiments of the present application relate to the field of circuits, and in particular to a 33-bit adder and an implementation method thereof, a computing circuit, and a chip. Background Art

[0002] The 33-bit adder is one of the commonly used circuits in digital circuit design. For example, the 33-bit adder is often used in complex logic chips such as central processing unit (CPU) and graphics processing unit (GPU). It is also often used in comprehensive design chips such as microcontroller unit (MCU) and field programmable gate array (FPGA).

[0003] In the related art, when a 33-bit adder calculates the sum of each bit, it is usually necessary to first obtain the carry output of the adjacent previous bit. For example, when calculating the sum of the second bit, it is necessary to first obtain the carry output of the first bit, and when calculating the sum of the third bit, it is necessary to first obtain the carry output of the second bit in the carry chain. Similarly, when calculating the sum of the 32nd bit, the carry output of the 31st bit in the carry chain is first obtained. The entire calculation process takes a long time and has a low calculation speed. Summary of the invention

[0004] In view of this, the embodiments of the present application provide a 33-bit adder and its implementation method, operation circuit and chip to overcome all or part of the above-mentioned technical defects.

[0005] In a first aspect, an embodiment of the present application provides a 33-bit adder, comprising:

[0006] N carry modules, each carry module corresponds to a plurality of bits in a first addend and a second addend, wherein the nth carry module is connected to the n-1th carry module to receive an inter-stage carry parameter output by the n-1th carry module, the first addend and the second addend are 33-bit binary numbers, N is an integer greater than 1 and less than 32, and n is an integer greater than 1 and less than or equal to N; each carry module includes a preprocessing unit and a plurality of carry calculation units, and one carry calculation unit corresponds to one bit of the first addend and the second addend;

[0007] The preprocessing unit included in the n-th carry module is used to preprocess a plurality of bits in the corresponding first addend and second addend;

[0008] The n-th carry module comprises a plurality of carry calculation units, which are used to perform calculations according to the preprocessing result and the inter-stage carry parameter of the n-1-th carry module to generate the carry output of each bit corresponding to the n-th carry module and the inter-stage carry parameter of the n-th carry module;

[0009] A summation module is electrically connected to the N carry modules to perform calculations according to each bit of the first addend and the second addend, and the corresponding carry outputs to obtain a corresponding summation result.

[0010] In a second aspect, the present application provides a method for implementing a 33-bit adder, which includes:

[0011] Receive a first addend and a second addend, wherein the first addend and the second addend are divided into N data groups in order of bits from low to high, each data group includes a plurality of bits in the first addend and the second addend, and N is an integer greater than 1 and less than 32;

[0012] Preprocessing a plurality of bits contained in each data group;

[0013] Calculating the carry output of multiple bits contained in each data group, wherein for the nth data group among the N data groups, performing calculations according to the preprocessing result of the nth data group and the inter-stage carry parameter of the n-1th data group, generating the carry output of each bit corresponding to the nth data group and the inter-stage carry parameter of the nth carry module, where n is an integer greater than 1 and less than or equal to N;

[0014] An operation is performed according to each bit of the first addend and the second addend, and the corresponding carry output, to obtain a corresponding sum result.

[0015] In a third aspect, the present application provides an operation circuit, which includes an adder provided according to any embodiment of the first aspect.

[0016] In a fourth aspect, the present application provides a chip, comprising an operation circuit provided according to any embodiment of the second aspect.

[0017] The embodiment of the present application provides a 33-bit adder and its implementation method, operation circuit and chip. Since the adder includes N carry modules, each carry module corresponds to multiple bits in the first addend and the second addend, and each carry module includes a preprocessing unit and multiple carry calculation units, the preprocessing unit included in the nth carry module is used to preprocess the multiple bits in the corresponding first addend and the second addend, and the multiple carry calculation units included in the nth carry module are used to perform operations based on the preprocessing results and the inter-stage carry parameters of the n-1th carry module to generate The carry output of each bit corresponding to the n-th carry module and the inter-stage carry parameter of the n-th carry module, when the inter-stage carry parameter output by the n-1-th carry module is obtained, each carry calculation unit in the n-th carry module can directly use the preprocessing result and the inter-stage carry parameter output by the n-1-th carry module to parallelly calculate the carry output of each corresponding bit, thereby basically realizing the parallel calculation of the carry output of each bit in the 33-bit binary data for the sum operation, thereby shortening the duration of the entire calculation process and improving the calculation speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Hereinafter, some specific embodiments of the present application will be described in detail in an exemplary and non-limiting manner with reference to the accompanying drawings. The same reference numerals in the accompanying drawings indicate the same or similar components or parts. It should be understood by those skilled in the art that these drawings are not necessarily drawn to scale. In the accompanying drawings:

[0019] Figure 1 A schematic diagram of the structure of a 33-bit adder provided in an embodiment of the present application;

[0020] Figure 2 A circuit diagram of a first preprocessing unit in a carry module of a 33-bit adder provided in an embodiment of the present application;

[0021] Figure 3 A circuit diagram of a second preprocessing unit in a carry module of a 33-bit adder provided in an embodiment of the present application;

[0022] Figure 4 A circuit diagram of an exemplary carry module of a 33-bit adder provided in an embodiment of the present application;

[0023] Figure 5 A schematic diagram of a carry chain of a 33-bit adder is provided for an embodiment of the present application;

[0024] Figure 6 A schematic flowchart of a method for implementing a 33-bit adder provided in an embodiment of the present application. DETAILED DESCRIPTION

[0025] The specific implementation of the embodiment of the present invention is further described below in conjunction with the accompanying drawings of the embodiment of the present invention.

[0026] Embodiment 1

[0027] Figure 1 The schematic diagram of the structure of an adder provided in an embodiment of the present application. The adder in this embodiment can be an independent hardware circuit structure, or a basic circuit unit structure of other devices such as a chip or a microprocessor. Figure 1 As shown, the 33-bit adder provided in the embodiment of the present application includes N carry modules 10, where N is an integer greater than 1 and less than 32. Each carry module corresponds to a plurality of bits in the first addend and the second addend, wherein the first addend and the second addend are 33-bit binary numbers. For example, a carry module may correspond to 2 bits, 3 bits or more bits in the first addend and the second addend, etc. It should be understood that the number of bits in the first addend and the second addend corresponding to each carry module in the N carry modules 10 may be the same or different.

[0028] The nth carry module is connected to the n-1th carry module to receive the inter-stage carry parameter output by the n-1th carry module, thereby calculating the inter-stage carry parameter of the nth carry module and the carry output of each bit corresponding to the nth carry module based on the inter-stage carry parameter output by the n-1th carry module. Where n is an integer greater than 1 and less than or equal to N.

[0029] Each carry module includes a preprocessing unit and a plurality of carry calculation units, and one carry calculation unit corresponds to one bit of the first addend and the second addend.

[0030] In this embodiment, the preprocessing unit included in the n-th carry module is used to preprocess multiple bits in the corresponding first addend and second addend.

[0031] Optionally, in an implementation of the present application, the preprocessing result includes: an intra-group carry generation signal and an intra-group carry propagation signal. The preprocessing unit included in the nth carry module is specifically used to: operate on each bit in the corresponding first addend and second addend to generate a carry generation signal and a carry propagation signal corresponding to each bit; and generate an intra-group carry generation signal and an intra-group carry propagation signal for each bit based on the carry generation signal and carry propagation signal of at least one corresponding bit.

[0032] Specifically, a logical AND operation is performed on each bit of the corresponding first addend and second addend to generate a carry generation signal for each bit, and the carry generation signal is the result of the logical AND value operation of the corresponding bit in the first addend and the second addend. A logical OR operation is performed on each bit of the corresponding first addend and the second addend to generate a carry propagation signal for each bit, and the carry propagation signal is the result of the logical OR value operation of the corresponding bit in the first addend and the second addend. In order to facilitate the overall layout during circuit implementation, in the embodiments of the present application, the result of the logical NOT operation of the carry generation signal for each bit is sometimes referred to as the carry generation signal. Similarly, the result of the logical NOT operation of the carry propagation signal for each bit is referred to as the carry propagation signal.

[0033] After obtaining the carry generation signal and carry propagation signal of each bit corresponding to the nth carry module, the preprocessing unit included in the nth carry module can also perform a logical OR operation on the carry generation signals of multiple adjacent bits to generate an intra-group carry generation signal, and the preprocessing unit included in the nth carry module can also perform a logical AND operation on the carry propagation signals of multiple adjacent bits to generate an intra-group carry propagation signal. In order to facilitate the overall layout during circuit implementation, in the embodiments of the present application, the result of performing a logical NOT operation on the intra-group carry generation signal is sometimes referred to as the intra-group carry generation signal. Similarly, the result of performing a logical NOT operation on the intra-group carry propagation signal is referred to as the intra-group carry propagation signal.

[0034] For example, for the i-th bit in the first addend A and the second addend B, the carry of the i-th bit generates the signal G i =A i ·B i , the carry propagation signal P of the i-th bit i =A i +B i As mentioned above, in order to facilitate the overall layout of the circuit implementation, the carry generation signal and carry propagation signal of the i-th bit are sometimes expressed as or The carry signal G is generated from the jth bit to the ith bit. i：j =G i +G i+1 +...+G i , the intra-group carry propagation signal P from the j-th bit to the i-th bit i：j =P i ·P i+1 ·...·P i As mentioned above, in order to facilitate the overall layout of the circuit implementation, the intra-group carry generation signal and carry propagation signal from the j-th bit to the i-th bit can sometimes also be expressed as and

[0035] In addition, G i：j =G i：k +G k-1：j , and P i：j =P i：k ·P k-1：j , where k is any bit between the jth bit and the ith bit in order from low to high.

[0036] In this embodiment, the nth carry module includes multiple carry calculation units, which are used to perform operations based on the preprocessing results and the inter-stage carry parameters of the n-1th carry module to generate the carry output of each bit corresponding to the nth carry module and the inter-stage carry parameters of the nth carry module.

[0037] Optionally, in one embodiment of the present application, each carry calculation unit included in the nth carry module is specifically used to perform operations based on the intra-group carry generation signal and intra-group carry propagation signal of the corresponding bit and the inter-stage carry parameter of the n-1th carry module to generate the carry output of the corresponding bit.

[0038] For the highest bit among the multiple bits corresponding to the nth carry module, the carry calculation unit corresponding to the highest bit is also used to use the carry parameter obtained in the calculation of the carry output of the highest bit corresponding to the nth carry module as the inter-stage carry parameter of the nth carry module.

[0039] The carry parameter is an intermediate quantity obtained in the calculation process of the carry output of each bit, and there is a preset relationship between the carry parameter and the carry output. The carry output of each bit can be obtained by calculating the carry parameter of the bit and the carry propagation signal of the bit. Specifically, the carry output of each bit is the logical AND operation result of the carry parameter of the bit and the carry propagation signal of the bit. For example, if the carry output of the i-th bit is C i , the carry propagation signal of the i-th bit is P i , the carry parameter of the i-th bit is Cp i , then the default relationship is: C i =P i ·Cp i .

[0040] If the highest bit among the multiple bits corresponding to the n-1th carry module is the (k-1)th bit, then the multiple carry calculation units in the n-1th carry module calculate the carry output C of the (k-1)th bit. k-1 Get the carry parameter Cp k-1, as the n-1th inter-stage carry parameter. If the output result of the preprocessing unit of the nth carry module includes the intra-group carry generation signal G i：k and the group carry generates the signal P i-1：k , then the carry output of the i-th bit is C i =G i：k +P i：k-1 ·Cp k-1 In addition, due to P i：k-1 ·Cp k-1 =P i：k ·P k-1 ·Cp k-1 , therefore, C i =G i：k +P i：k ·C k-1 Also true.

[0041] Due to G i：k and P i：k It can be obtained by the preprocessing unit. Therefore, the carry calculation unit corresponding to the i-th bit in the n-th carry module obtains the inter-stage carry parameter C of the n-1-th carry module. k-1 When the carry output or carry parameter of the ith bit can be obtained through simple logical operations. In addition, since the preprocessing unit in the nth carry module can preprocess the multiple bits corresponding to the nth carry module to obtain the corresponding multiple intra-group carry generation signals and intra-group carry propagation signals, the multiple carry calculation units in the nth carry module can calculate the carry output of each bit in parallel based on the corresponding intra-group carry generation signals and intra-group carry propagation signals, thereby improving the efficiency of carry calculation.

[0042] It should be understood that in order to facilitate the overall layout of the circuit implementation, the carry parameter Cp k-1 and carry output C k-1 Sometimes also expressed as and

[0043] In the embodiment of the present application, since the preprocessing unit included in the nth carry module preprocesses multiple bits in the corresponding first addend and second addend, the multiple carry calculation units included in the nth carry module are used to perform operations based on the preprocessing results and the inter-level carry parameters of the n-1th carry module to generate the carry output of each bit corresponding to the nth carry module and the inter-level carry parameters of the nth carry module. This makes it possible that when the inter-level carry parameters output by the n-1th carry module are obtained, each carry calculation unit in the nth carry module can directly use the preprocessing results and the inter-level carry parameters output by the n-1th carry module to parallelly calculate the carry output of each corresponding bit, thereby basically realizing the parallel calculation of the carry output of each bit in the 33-bit binary data.

[0044] In addition, if Figure 1 As shown, the 33-bit adder also includes a summation module, which is electrically connected to N carry modules to perform operations according to each bit of the first addend and the second addend, and the corresponding carry output to obtain a corresponding summation result.

[0045] For example, for the i-th bit in the first addend A and the second addend A, the summation result of the i-th bit can be obtained according to the following summation formula. The formula is:

[0046]

[0047] Among them, C i-1 It is the carry output of the i-1th bit in the first addend A and the second addend A.

[0048] In this embodiment, since the carry output of each bit in the 33-bit binary data is calculated basically in parallel, the sum result of each bit in the 33-bit binary data can be calculated basically in parallel, thereby shortening the duration of the entire calculation process and improving the calculation speed.

[0049] Optionally, in an embodiment of the present application, the number of bits in the first addend and the second addend corresponding to the nth carry module is equal to or greater than the number of bits in the first addend and the second addend corresponding to the (n-1)th carry module.

[0050] Since the calculation of the carry output of each bit corresponding to the nth carry module depends on the inter-stage carry parameter of the n-1th carry module, the carry operation time of each carry calculation unit in the nth carry module has a certain logic delay relative to the carry operation time of each carry calculation unit in the n-1th carry module. By making the number of bits in the first addend and the second addend corresponding to the nth carry module equal to or greater than the number of bits in the first addend and the second addend corresponding to the n-1th carry module, this logic delay can be fully utilized to calculate the intra-group carry generation signal and the intra-group carry propagation signal, avoiding the situation that the nth carry module waits for the inter-stage carry parameter of the n-1th carry module during calculation, which is conducive to further reducing the time consumed by the operation.

[0051] Optionally, in an embodiment of the present application, N is equal to 5, the first carry module corresponds to the 0th to 3rd bits of the first addend and the second addend, the second carry module corresponds to the 4th to 7th bits of the first addend and the second addend, the third carry module corresponds to the 8th to 11th bits of the first addend and the second addend, the fourth carry module corresponds to the 12th to 17th bits of the first addend and the second addend, and the fifth carry module corresponds to the 18th to 32nd bits of the first addend and the second addend. Thus, the layout of the adder is more concentrated, the area is smaller, and it is conducive to the overall structural layout.

[0052] It should be understood that in this embodiment, the number N of carry modules may be 2, 4, or more, and the specific bits corresponding to each carry module may be set as needed, which is not limited in this embodiment.

[0053] Embodiment 2

[0054] Based on the 33-bit adder provided in the first embodiment, further, this embodiment provides Figure 1 A schematic diagram of the structure of a carry module in a 33-bit adder is shown. It should be understood that the carry module can be any carry module of the N carry modules in the first embodiment. For the convenience of description, the carry module is referred to as the nth carry module below. In this embodiment, the preprocessing unit included in the nth carry module includes at least one first preprocessing unit and at least one second preprocessing unit arranged alternately.

[0055] In this embodiment, the first preprocessing unit is used to perform operations on the i-th bit and the i-1-th bit in the corresponding first addend and the second addend to generate a first preprocessing result, and the first preprocessing result indicates the logical OR operation result of the carry generation signals of the i-th bit and the i-1-th bit, where i is an odd number.

[0056] Optionally, in a specific implementation of the present application, Figure 2 As shown, the first preprocessing unit includes: a first AND gate 201, a second AND gate 202 and a first NOR gate 203, the first input terminal and the second input terminal of the first AND gate 201 respectively receive the i-th bit, and the output terminal of the first AND gate 201 is connected to the first input terminal of the first NOR gate 203; the first input terminal and the second input terminal of the second AND gate 202 respectively receive the i-1-th bit, the output terminal of the second AND gate 202 is connected to the second input terminal of the first NOR gate 203, and the output terminal of the first NOR gate 203 outputs the first preprocessing result. For example, if the first addend is A and the second addend is B, the first preprocessing result is Among them, G i and G i-1 A carry signal is generated for the i-th bit position and a carry signal is generated for the i-1-th bit position.

[0057] It should be understood that the first pre-processing unit may also be directly implemented by a structure such as an AND-NOR gate, and this embodiment does not limit this.

[0058] In this embodiment, the second preprocessing unit is used to perform operations on the j-th bit and the j-1-th bit in the corresponding first addend and the second addend to generate a second preprocessing result, and the second preprocessing result indicates the logical AND operation result of the carry propagation signals of the j-th bit and the j-1-th bit, where j is an even number.

[0059] Optionally, in a specific implementation of the present application, Figure 3 As shown, the second preprocessing unit includes: a first OR gate 301, a second OR gate 302 and a first NAND gate 303, the first input terminal and the second input terminal of the first OR gate 301 respectively receive the jth bit, and the output terminal of the first OR gate 301 is connected to the first input terminal of the first NAND gate; the first input terminal and the second input terminal of the second OR gate 302 respectively receive the j-1th bit, the output terminal of the second OR gate 302 is connected to the second input terminal of the first NAND gate 303, and the output terminal of the first NAND gate 303 outputs the second preprocessing result. For example, if the first addend is A and the second addend is B, the first preprocessing result is Among them, P j and P j-1 is the carry propagation signal of the j-th bit and the carry propagation signal of the j-1-th bit.

[0060] It should be understood that the second pre-processing unit may also be directly implemented by a structure such as an OR-NAND gate, and this embodiment does not limit this.

[0061] Accordingly, the nth carry module includes a plurality of carry calculation units, which are used to obtain the carry output of the corresponding bit based on at least one first preprocessing result and at least one second preprocessing result and the inter-stage carry parameter of the n-1th carry module. Figure 4 As shown, in one example, the nth carry module corresponds to 4 to 7 bits in the first addend and the second addend, and the preprocessing unit corresponding to the nth carry module generates a total of 2 first preprocessing results (i.e., GON_5_4) and (ie, GON_7_6), and 2 second preprocessing results (i.e., PAN_4_3), (That is, PAN_6_5), the multiple carry calculation units included in the nth carry module can obtain the carry output of the bit corresponding to the nth carry module based on these first preprocessing results and the second preprocessing results combined with the inter-stage carry parameters of the n-1th carry module.

[0062] Optionally, in one embodiment of the present application, the preprocessing unit included in the nth carry module further includes a third preprocessing unit and a fourth preprocessing unit, the third preprocessing unit respectively operates on at least two adjacent first preprocessing results output by at least one first preprocessing unit and at least two adjacent second preprocessing results output by at least one second preprocessing unit to generate corresponding third preprocessing results and fourth preprocessing results, the third preprocessing result indicates a carry parameter between corresponding adjacent multiple bits, and the fourth preprocessing result indicates a logical AND operation result of carry propagation signals of corresponding adjacent multiple bits. The multiple carry calculation units included in the nth carry module are used to obtain the carry output of the corresponding bit based on the third preprocessing result and the fourth preprocessing result and the inter-stage carry parameter of the n-1th carry module.

[0063] For example, the third preprocessing unit processes the first preprocessing result and And the second preprocessing result Perform an operation to generate a carry parameter indicating the carry between the 4th bit and the 7th bit The fourth preprocessing unit performs a preprocessing operation based on the second preprocessing result. And the second preprocessing result Perform an operation to generate the logical OR result of the carry generation signal indicating the 3rd bit to the 6th bit, that is, an intra-group carry propagation signal (That is, PAN_6_3). The corresponding carry calculation unit can obtain the carry output of the 7th bit based on the third preprocessing result GON_7_4 and the fourth preprocessing result PAN_6_3 in combination with the inter-stage carry parameter of the n-1th carry module.

[0064] Optionally, in an embodiment of the present application, the multiple carry calculation units included in the nth carry module include a first carry calculation unit corresponding to the i-th bit, and the first carry calculation unit includes a third OR gate, a third AND gate, and a second NOR gate;

[0065] A first input end of the third OR gate is connected to an output end of the corresponding second preprocessing unit, a second input end of the third OR gate is connected to an inter-stage carry parameter output by the n-1th carry module, an output end of the third OR gate is connected to a first input end of a third AND gate, a second input end of the third AND gate is connected to an output end of the corresponding first preprocessing unit, and an output end of the third AND gate outputs the carry parameter of the i-th bit;

[0066] The output end of the third AND gate is connected to the first input end of the second NOR gate, the second input end of the second NOR gate receives the carry propagation signal of the i-th bit, and the output end of the second NOR gate is connected to the summing module to output the carry output of the i-th bit to the summing module.

[0067] For example, Figure 4 As shown, the n-1th carry module corresponds to 0 to 3 bits in the first addend and the second addend, and the nth carry module corresponds to 4 to 7 bits in the first addend and the second addend. For example, the preprocessing units included in the nth carry module include alternately arranged first preprocessing units and second preprocessing units 401 to 404, and alternately arranged first carry calculation units and second carry calculation units 405 to 408. For the 5th bit, the first input end of the third OR gate in the corresponding first carry calculation unit 406 is connected to the output end of the corresponding second preprocessing unit 401 to obtain (ie, PAN_4_3), the second input terminal of the third OR gate is connected to the inter-stage carry parameter output by the n-1th carry module (ie, CPN_3_0), the output end of the third OR gate is connected to the first input end of the third AND gate, and the second input end of the third AND gate is connected to the output end of the corresponding first pre-processing unit to obtain (That is, GON_5_4), the output end of the third AND gate outputs the carry parameter of the 5th bit (That is, CPN_5_0). The output of the third AND gate is connected to the first input of the second NOR gate, and the second input of the second NOR gate receives the carry propagation signal of the fifth bit. (ie, PN_5), the output terminal of the second NOR gate outputs a carry output (ie, CN_5_0), that is, the carry output of the 5th bit generates a signal G based on the carry within the 5th bit. 5：4 and the intra-group carry propagation signal P5：3 And the inter-stage carry parameter of the first carry module is obtained.

[0068] In addition, since C5=G 5：4 +P 5：3 CP3=G 5：4 +P 5：4 C3, therefore, it can also be understood that the carry output of the 5th bit generates the signal G based on the carry within the 5th bit. 5：4 and the intra-group carry propagation signal P 5：4 And the inter-stage carry output of the n-1th carry module is obtained.

[0069] For example, Figure 4 As shown, for the 7th bit, the first input terminal of the third OR gate in the corresponding first carry calculation unit 408 is connected to the output terminal of the corresponding fourth pre-processing unit 410 to obtain (ie, PAN_6_3), the second input terminal of the third OR gate is connected to the inter-stage carry parameter output by the n-1th carry module (ie, CPN_3_0), the output end of the third OR gate is connected to the first input end of the third AND gate, and the second input end of the third AND gate is connected to the output end of the corresponding fourth pre-processing unit 409 to obtain The output of the third AND gate outputs the carry parameter of the 7th bit (That is, CPN_7_0). The output of the third AND gate is connected to the first input of the second NOR gate, and the second input of the second NOR gate receives the carry propagation signal of the 7th bit. (ie, PN_7), the output terminal of the second NOR gate outputs a carry output (ie, CN_7_0), that is, the carry output of the 7th bit generates a signal G based on the carry within the 7th bit. 7：4 and the intra-group carry propagation signal P 7：3 And the inter-stage carry parameter of the first carry module is obtained.

[0070] In addition, since the 7th bit is the highest bit corresponding to the second carry module, the carry parameter obtained in the calculation of the carry output of the second bit is (ie, CP_7_0) is used as the inter-stage carry output of the second carry module and provided to the third carry module.

[0071] Optionally, in an embodiment of the present application, the multiple carry calculation units further include a second carry calculation unit corresponding to the j-th bit, and the second carry calculation unit includes a fourth OR gate and a second NAND gate.

[0072] The first input end of the fourth OR gate is connected to the output end of the corresponding second preprocessing unit, the second input end of the fourth OR gate is connected to the inter-level carry parameter output by the n-1th carry module or the carry parameter of the j-1th bit, the output end of the fourth OR gate is connected to the first input end of the second NAND gate, the second input end of the second NAND gate receives the carry generation signal corresponding to the jth bit, and the output end of the second NAND gate is connected to the summation module to output the carry output of the jth bit to the summation module.

[0073] Likewise, if Figure 4 As shown, for the 4th bit, the first input end of the fourth OR gate in the corresponding second carry calculation unit 405 is connected to the output end of the corresponding second pre-processing unit to obtain The second input terminal of the fourth OR gate is connected to the inter-stage carry parameter output by the n-1th carry module. The output end of the fourth OR gate is connected to the first input end of the second NAND gate, and the second input end of the second NAND gate receives the carry generation signal corresponding to the fourth bit. (ie, GN_4), the output terminal of the second NAND gate outputs (ie, C_4), that is, the carry output of the 4th bit is based on the intra-group carry generation signal G4 and the intra-group carry propagation signal P of the 4th bit. 4：3 In addition, since C4=G4+P4·P3·CP3=G4+P4·C3, it can also be understood that the carry output of the 5th bit is obtained based on the intra-group carry generation signal G4 and the intra-group carry propagation signal P4 of the 5th bit and the inter-stage carry output C3 of the n-1th carry module.

[0074] For example, Figure 4 As shown, for the sixth bit, the first input end of the fourth OR gate in the corresponding second carry calculation unit is connected to the output end of the corresponding second pre-processing unit to obtain (ie, PAN_6_5), the second input of the fourth OR gate is connected to the carry parameter of the 5th bit to obtain (ie, CPN_5_0), the output end of the fourth OR gate is connected to the first input end of the second NAND gate, and the second input end of the second NAND gate receives the carry generation signal corresponding to the sixth bit (ie, GN_6), the output terminal of the second NAND gate outputs That is, the carry output of the 6th bit is based on the intra-group carry generation signal G6 and the intra-group carry propagation signal P of the 6th bit. 6：5 And the carry parameter CP5 of the 5th bit is obtained.

[0075] It should be understood that Figure 4 It is only an example for illustrating the carry module of the adder provided in the embodiment of the present application. The connection relationship between the preprocessing unit and the multiple carry calculation units in each carry module of the 33-bit adder can be adjusted as needed, and this embodiment does not limit this.

[0076] In the present embodiment, since the first preprocessing unit, the second preprocessing unit, the third preprocessing unit and the fourth preprocessing unit in each carry module preprocess the multiple bits in the first addend and the second addend corresponding to each carry module, each carry module includes multiple carry calculation units, so that when each carry module obtains the inter-stage carry parameter output by the previous carry module, the multiple carry calculation units in each carry module can directly use the preprocessing result and the inter-stage carry parameter output by the previous carry module to parallelly calculate the carry output of each corresponding bit, thereby basically realizing the parallel calculation of the carry output of each bit in the 33-bit binary data.

[0077] like Figure 5 As shown, the first carry module 501 corresponds to the 0th bit to the 3rd bit of the first addend and the second addend, the second carry module 502 corresponds to the 4th bit to the 7th bit of the first addend and the second addend, the third carry module 503 corresponds to the 8th bit to the 11th bit of the first addend and the second addend, the fourth carry module corresponds to the 12th bit to the 17th bit of the first addend and the second addend, and the fifth carry module corresponds to the 18th bit to the 32nd bit of the first addend and the second addend. The preprocessing units in the first carry module 501 to the fifth carry module 505 preprocess the corresponding bits, and the carry parameter of the highest bit (i.e., the third bit) among the multiple bits corresponding to the first carry module is provided to the second carry module as an inter-stage carry parameter, so that the multiple carry calculation units in the second carry module calculate the carry output of each bit corresponding to the second carry module, and at the same time, the highest bit (i.e., the seventh bit) among the multiple bits corresponding to the second carry module is calculated based on the preprocessing result and the inter-stage carry of the first carry module. The inter-level carry parameter of the 7th bit is output and provided to the 3rd carry module, so that the multiple carry calculation units in the 3rd carry module calculate the carry output of each bit corresponding to the 3rd carry module, and so on. This basically realizes the parallel calculation of the carry output of each bit in the 33-bit binary data, so that the summation module 506 can calculate the summation result of each bit in parallel according to each bit in the first addend A and the second addend A and the corresponding carry output, thereby shortening the duration of the entire calculation process and improving the calculation speed.

[0078] In addition, by regularly arranging the first preprocessing unit, the second preprocessing unit, the third preprocessing unit, the fourth preprocessing unit, the first carry calculation unit, and the second carry calculation unit, the calculation speed of the 33-bit adder can be improved while reducing the occupied area of ​​the 33-bit adder, and the wiring can be more concentrated, which is conducive to the overall structured layout.

[0079] It should be pointed out that Figure 5 It is only a specific example used to illustrate the carry chain of the 33-bit adder provided in this embodiment. According to actual needs, the number of carry modules can be 2, 4, or more, and the specific bit corresponding to each carry module can be set as needed, which is not limited in this embodiment.

[0080] Embodiment 3

[0081] Based on the 33-bit adder provided in the above embodiment, an embodiment of the present application provides a method for implementing a 33-bit adder. Figure 6 The following is a flow chart of a method for implementing a 33-bit adder provided in an embodiment of the present application. Figure 6 As shown, the implementation method of the 33-bit adder includes:

[0082] S601, receiving a first addend and a second addend, wherein the first addend and the second addend are divided into N data groups in order of bits from low to high, each data group includes a plurality of bits in the first addend and the second addend, and N is an integer greater than 1 and less than 32;

[0083] S602, preprocessing multiple bits included in each data group;

[0084] S603, calculating the carry outputs of multiple bits contained in each data group, wherein for the nth data group among the N data groups, performing calculations according to the preprocessing result of the nth data group and the inter-stage carry parameter of the n-1th data group, generating the carry output of each bit corresponding to the nth data group and the inter-stage carry parameter of the nth carry module, where n is an integer greater than 1 and less than or equal to N;

[0085] S604: Perform an operation according to each bit of the first addend and the second addend, and the corresponding carry output, to obtain a corresponding sum result.

[0086] Optionally, in an embodiment of the present application, step S602 specifically includes:

[0087] Performing operations on each bit of the corresponding first addend and second addend to generate a carry generation signal and a carry propagation signal corresponding to each bit; generating an intra-group carry generation signal and an intra-group carry propagation signal for each bit based on the carry generation signal and the carry propagation signal of the corresponding at least one bit;

[0088] Accordingly, step S603 specifically includes:

[0089] An operation is performed based on the intra-group carry generation signal and the intra-group carry propagation signal of the bit position corresponding to each data group and the inter-stage carry parameter of the previous data group to generate a carry output of the bit position corresponding to each data group.

[0090] Optionally, in one embodiment of the present application, calculating the carry output of multiple bits contained in each data group also includes: using the carry parameter obtained from the calculation of the carry output of the highest bit among the multiple bits corresponding to each data group as the inter-level carry parameter of the data group, wherein the carry output of the highest bit is obtained by calculating the carry parameter of the highest bit and the carry propagation signal of the highest bit.

[0091] Optionally, in an embodiment of the present application, the number of bits in the first addend and the second addend corresponding to each data group is equal to or greater than the number of bits in the first addend and the second addend corresponding to the previous data group.

[0092] Optionally, in one embodiment of the present application, N is equal to 3, the first data group corresponds to the 0th to 3rd bits of the first addend and the second addend, the second data group corresponds to the 4th to 7th bits of the first addend and the second addend, the third data group corresponds to the 8th to 11th bits of the first addend and the second addend, the fourth carry module corresponds to the 12th to 17th bits of the first addend and the second addend, and the fifth carry module corresponds to the 18th to 32nd bits of the first addend and the second addend.

[0093] The implementation method of the 33-bit adder provided in the embodiment of the present application is used to implement the 33-bit adder in the aforementioned device embodiment, and has the beneficial effects of the corresponding device embodiment, which will not be repeated here.

[0094] Embodiment 4

[0095] The embodiment of the present application provides an operation circuit, which includes a 33-bit adder provided according to any one of the above-mentioned embodiments 1 and 2. The principle and effect thereof are similar and will not be described in detail here.

[0096] Embodiment 5

[0097] The embodiment of the present application provides a chip, which includes the operation circuit provided according to the above-mentioned embodiment 4. The principle and effect thereof are similar and will not be described in detail here.

[0098] Each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0099] The above is only an embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.

Claims

1. A method for implementing a 33-bit adder, characterized in that: include: Receive a first addend and a second addend, wherein the first addend and the second addend are divided into N data groups in order of bits from low to high, each data group includes a plurality of bits in the first addend and the second addend, and N is an integer greater than 1 and less than 32; Preprocessing a plurality of bits contained in each data group; Calculating the carry output of multiple bits contained in each data group, wherein for the nth data group among the N data groups, performing calculations according to the preprocessing result of the nth data group and the inter-stage carry parameter of the n-1th data group, generating the carry output of each bit corresponding to the nth data group and the inter-stage carry parameter of the nth carry module, where n is an integer greater than 1 and less than or equal to N; Performing an operation according to each bit of the first addend and the second addend, and the corresponding carry output, to obtain a corresponding sum result; Wherein, the preprocessing unit included in the nth carry module includes at least one first preprocessing unit and at least one second preprocessing unit arranged alternately; The first preprocessing unit is used to operate on the i-th bit and the i-1-th bit in the corresponding first addend and the second addend to generate a first preprocessing result, wherein the first preprocessing result indicates a logical OR operation result of the carry generation signals of the i-th bit and the i-1-th bit, and i is an odd number; The second preprocessing unit is used to operate the j-th bit and the j-1-th bit in the corresponding first addend and the second addend to generate a second preprocessing result, wherein the second preprocessing result indicates a logical AND operation result of the carry propagation signals of the j-th bit and the j-1-th bit, and j is an even number; The nth carry module comprises a plurality of carry calculation units, which are used to obtain a carry output of a corresponding bit based on the first preprocessing result, the second preprocessing result and the inter-stage carry parameter of the n-1th carry module; The multiple carry calculation units included in the n-th carry module include a first carry calculation unit corresponding to the i-th bit, and the first carry calculation unit includes a third OR gate, a third AND gate and a second NOR gate; The first input end of the third OR gate is connected to the output end of the corresponding second preprocessing unit or the fourth preprocessing unit, the second input end of the third OR gate is connected to the inter-stage carry parameter output by the n-1th carry module, the output end of the third OR gate is connected to the first input end of the third AND gate, the second input end of the third AND gate is connected to the output end of the corresponding first preprocessing unit or the third preprocessing unit, and the output end of the third AND gate outputs the carry parameter of the i-th bit; The output terminal of the third AND gate is connected to the first input terminal of the second NOR gate, the second input terminal of the second NOR gate receives the carry propagation signal of the i-th bit, and the output terminal of the second NOR gate is connected to the summing module to output the carry output of the i-th bit to the summing module; The multiple carry calculation units include a second carry calculation unit corresponding to the j-th bit, and the second carry calculation unit includes a fourth OR gate and a second NAND gate; The first input end of the fourth OR gate is connected to the output end of the corresponding second preprocessing unit, the second input end of the fourth OR gate is connected to the inter-level carry parameter output by the n-1th carry module or the carry parameter of the j-1th bit, the output end of the fourth OR gate is connected to the first input end of the second NAND gate, the second input end of the second NAND gate receives the carry generation signal corresponding to the jth bit, and the output end of the second NAND gate is connected to the summation module to output the carry output of the jth bit to the summation module.

2. A computing circuit, characterized in that: The arithmetic circuit comprises a 33-bit adder implemented according to the method of claim 1 .

3. A chip, characterized in that: The chip includes the operation circuit according to claim 2.

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