A method and circuit for automatic measurement of voltage, resistance and capacitance

Abstract

The present invention relates to electronic component measurement technology, and discloses a method and circuit for automatic measurement of voltage, resistance and capacitance; the method comprises an external signal input circuit, an internal switch network circuit, a reference signal output and current source generation circuit, a channel switching and ADC acquisition circuit and a comparator output circuit; the external signal input circuit is connected to the internal switch network circuit, the internal switch network circuit is connected to the channel switching and ADC acquisition circuit and the reference signal output and current source generation circuit, and the external signal input circuit comprises a resistor R5 and an input port A1, a resistor R6 and an input port A2, and a resistor R7 and an input port A4. The present invention simplifies the measurement circuit of a voltage, resistance and capacitance meter, and only three resistors are required to automatically measure voltage, resistance and capacitance, and there is no need to use relays and dials to switch gears, and the internal automatic range is determined for measurement; the design is safe and reliable, the volume is small, and the manufacturer's production cost is reduced and production efficiency is improved.

Description

Technical Field

[0001] The invention relates to electronic component measurement technology, and in particular to a method and circuit for automatic measurement of voltage, resistance and capacitance. Background Art

[0002] With the development of electronic industry technology and measurement and control technology, the demand for measuring instruments will become greater and greater. In different application scenarios, it is often necessary to measure the size of voltage, resistance and capacitance.

[0003] When producing and repairing circuits, the measurement of voltage, resistance and capacitance is often a crucial link. A good electronic product must be composed of qualified electronic components, among which power chips, resistors and capacitors are the most basic components. Therefore, the detection of voltage, resistance and capacitance is an inevitable link. Therefore, it is extremely necessary to design safe, reliable and convenient voltage, resistance and capacitance test instruments.

[0004] The voltage, resistance and capacitance meters currently on the market have complex circuit designs, too many gears, large size, and are complicated and troublesome to use. With the development of electronic industry technology, measurement and control technology, and the pressure of competition in the instrumentation industry, more and more measuring instruments are required to have simple circuit designs, convenient operation, small size, and low production costs.

[0005] The patent name is: A multimeter capable of automatic measurement, the application number is: CN201911119788.7, the application date: 2019-11-15, the patent application discloses a multimeter capable of automatic measurement, including: an input terminal for receiving a signal to be measured; a signal monitoring circuit for monitoring the voltage of the signal to be measured; a micro-control unit for issuing a measurement instruction according to the source of the signal to be measured; a function switching drive unit for switching the measurement gear according to the measurement instruction issued by the micro-control unit; a low-voltage switching circuit including a reed switch, when the function switching drive unit switches to a low-voltage measurement mode, the reed switch is closed; an anti-high-voltage protection device, connected to the input terminal and the low-voltage switching circuit, for preventing a high-voltage signal to be measured from entering the low-voltage switching circuit. With regard to this patent, its peripheral protection circuit is complex, and the use of a reed switch is cumbersome to operate;

[0006] For example, the patent name is: A digital multimeter, the application number is: CN200610062667.X, and the application date is: 2006-09-18. This patent requires an external auxiliary programmable voltage or current source, a voltage divider network, and an electronic switch, and its circuit design is complex. Summary of the invention

[0007] The present invention aims to solve the problems in the prior art that the peripheral protection circuit is complicated, the reed switch is used and the operation is troublesome; an auxiliary programmable voltage or current source and a voltage divider network and an electronic switch are required, and the circuit design is complicated. A method and circuit for automatic measurement of voltage, resistance and capacitance are provided.

[0008] In order to solve the above technical problems, the present invention is solved by the following technical solutions:

[0009] A circuit for automatic measurement of voltage, resistance and capacitance comprises an external signal input circuit, an internal switch network circuit, a reference signal output and current source generation circuit, a channel switching and ADC acquisition circuit and a comparator output circuit; the external signal input circuit is connected to the internal switch network circuit, and the internal switch network circuit is connected to the channel switching and ADC acquisition circuit and the reference signal output and current source generation circuit.

[0010] The external signal input circuit includes resistor R5 and input port A1, resistor R6 and input port A2, resistor R7 and input port A4; the internal switch network circuit includes resistors R1, R2, R3, R4 and switches K1, K2, K3, K4, K5, K6, K7, K8, K9, K10, K11; one end of A1 is connected to resistors R4, R3, R2 and R1 respectively through switches K1, K3, K5 and K7, resistor R1 is connected to switch K11, and the other port of K11 is connected to the COM port; one end of A2 is connected to resistors R4, R3, R2 and R1 respectively through switches K2, K4, K6 and K8, and resistor R1 is connected to switch K12; AVDDR is connected to the common end of resistors R3 and R2 through switch K9; VSS is connected to the common end of resistors R3 and R2 through switch K10.

[0011] By simplifying the measurement circuit and protection circuit of the voltage resistance and capacitance meter, only three resistors R5, R6, and R7 are needed for automatic measurement of voltage resistance and capacitance. There is no need to use relays and dials to switch gears. The internal automatic range is determined for measurement. The design is safe and reliable. The three large peripheral resistors can prevent high voltage from damaging the chip. The small size reduces the manufacturer's production cost and improves production efficiency.

[0012] Preferably, the reference signal output and current source generating circuit includes switches K12, K13, K14, K15, K16, NMOS tube Q1 and PMOS tube Q2, operational amplifier OPA and channel switch MUX1; switch K12 is connected to switch K13, and the other end of switch K13 is connected to the output end OPOUT of operational amplifier OPA; the negative input end of operational amplifier OPA is connected to the common end of switch K12, switch K13, NMOS tube Q1 and PMOS tube Q2, the positive input end of operational amplifier OPA is connected to switch K16, and the other end of switch K16 is connected to the output end of channel switch MUX1; one end of switch K14 is connected to the output end OPOUT of operational amplifier OPA, and the other end is connected to the gate of NMOS tube Q1; one end of switch K15 is connected to the output end OPOUT of operational amplifier OPA, and the other end is connected to the gate of PMOS tube Q2.

[0013] Preferably, the channel switching and ADC acquisition circuit includes a channel switch MUX2 and an analog-to-digital converter ADC; the voltages at points VA, VB, VC and VD are respectively controlled by the channel switch MUX2 to select V1P and V1N to acquire signals at the ADC input terminal.

[0014] Preferably, the comparator output circuit includes comparators CMPH, CMPL and latch LATCH; the A4 port is connected to the positive input terminal of the comparator CMPH and the negative input terminal of the comparator CMPL, the negative input port of the comparator CMPH is connected to the COM port, the output terminal CMPH_OUT of the comparator CMPH is connected to the input terminal of the latch LATCH, the positive input port of the comparator CMPL is connected to VDR22, the output terminal CMPL_OUT of the comparator CMPL is connected to the other input terminal of the latch LATCH, and the latch output terminal LATCH_OUT is connected to the capture module.

[0015] Preferably, when the CMPH comparator outputs a high level and the CMPL comparator outputs a low level, the input signal is determined to be a voltage signal; when the CMPH comparator outputs a low level and the CMPL comparator outputs a high level, the input signal is determined to be a capacitance signal; when the CMPH comparator outputs a low level and the CMPL comparator outputs a low level, the input signal is determined to be a resistance signal.

[0016] A method for automatic measurement of voltage, resistance and capacitance, including a circuit for automatic measurement of voltage, resistance and capacitance, the method comprising:

[0017] The voltage signal is measured by connecting the voltage signal to the A1 port through the resistor R5. The A1 port is connected to the internal switch network. The switch is switched according to different ranges. The R1 resistor is connected to the switch K11, and the switch K11 is connected to COM. Let Res1 = R1; Res2 = R1 + R2; Res3 = R1 + R2 + R3; Res4 = R1 + R2 + R3 + R4;

[0018]

[0019]

[0020] The resistance signal is measured by connecting the resistance signal to the A2 port through the resistor R6. The A2 port is connected to the internal switch network, and the switch is switched according to different ranges. The R1 resistor is connected to the switch K12, and the switch K12 is connected to the switch K13. The other end of the switch K13 is connected to the output end of the operational amplifier OPA. The voltage at the output end of the operational amplifier is Vop, the voltage at the COM end is Vcom, the resistance to be measured is Rx, and the internal reference resistance is Rr.

[0021]

[0022] For the measurement of capacitance signal, AVDDR is connected to resistor R2 through switch K9, the other end of resistor R2 is connected to resistor R1, resistor R1 is connected to switch K12, switch K12 is connected to the source of PMOS tube Q2, the gate of PMOS tube Q2 is connected to switch K15, the other end of switch K15 is connected to the output end OPOUT of op amp OPA; the drain of PMOS tube Q2 is connected to port A2, port A2 is connected to resistor R6 to the capacitor end to be measured.

[0023]

[0024] V OP 、V CMPH are all voltage dividers of AVDDR, and their coefficients are set to be a and b, that is: V OP =a×AVDDR; V CMPH =b×AVDDR; Rc=R1+R2

[0025] Convert to:

[0026]

[0027] The coefficients a and b are determined by the set voltage divider ratio, Δt is obtained by the calibrated clock count inside the chip, and R C Obtained by calibration.

[0028] The present invention has significant technical effects due to the adoption of the above technical solution: the present invention simplifies the measurement circuit and protection circuit of the voltage resistance and capacitance meter, and only needs three resistors R5, R6, and R7 to automatically measure the voltage resistance and capacitance, without the need to use relays and dial switching gears, and the internal automatic range is determined for measurement.

[0029] Meanwhile, the measuring circuit designed by the present invention is safe and reliable, and can prevent high voltage from damaging the chip through three large peripheral resistors. It has a small size, reduces the production cost of the manufacturer and improves the production efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 It is a circuit diagram of the present invention.

[0031] Figure 2 It is the internal switch network circuit diagram of the present invention.

[0032] Figure 3 It is a circuit diagram of reference signal output and current source generation of the present invention. DETAILED DESCRIPTION

[0033] The present invention is further described in detail below in conjunction with the accompanying drawings and embodiments.

[0034] Example 1

[0035] A circuit for automatic measurement of voltage, resistance and capacitance comprises an external signal input circuit, an internal switch network circuit, a reference signal output and current source generation circuit, a channel switching and ADC acquisition circuit and a comparator output circuit; the external signal input circuit is connected to the internal switch network circuit, and the internal switch network circuit is connected to the channel switching and ADC acquisition circuit and the reference signal output and current source generation circuit.

[0036] The external signal input circuit includes resistor R5 and input port A1, resistor R6 and input port A2, resistor R7 and input port A4; the internal switch network circuit includes resistors R1, R2, R3, R4 and switches K1, K2, K3, K4, K5, K6, K7, K8, K9, K10, K11; one end of A1 is connected to resistors R4, R3, R2 and R1 respectively through switches K1, K3, K5 and K7, resistor R1 is connected to switch K11, and the other port of K11 is connected to the COM port; one end of A2 is connected to resistors R4, R3, R2 and R1 respectively through switches K2, K4, K6 and K8, and resistor R1 is connected to switch K12; AVDDR is connected to the common end of resistors R3 and R2 through switch K9; VSS is connected to the common end of resistors R3 and R2 through switch K10.

[0037] By simplifying the measurement circuit and protection circuit of the voltage resistance and capacitance meter, only three resistors R5, R6, and R7 are needed for automatic measurement of voltage resistance and capacitance. There is no need to use relays and dials to switch gears. The internal automatic range is determined for measurement. The design is safe and reliable. The three large peripheral resistors can prevent high voltage from damaging the chip. The small size reduces the manufacturer's production cost and improves production efficiency.

[0038] The reference signal output and current source generating circuit includes switches K12, K13, K14, K15, K16, NMOS tube Q1 and PMOS tube Q2, operational amplifier OPA and channel switch MUX1; switch K12 is connected to switch K13, and the other end of switch K13 is connected to the output end OPOUT of operational amplifier OPA; the negative input end of operational amplifier OPA is connected to the common end of switch K12, switch K13, NMOS tube Q1 and PMOS tube Q2, the positive input end of operational amplifier OPA is connected to switch K16, and the other end of switch K16 is connected to the output end of channel switch MUX1; one end of switch K14 is connected to the output end OPOUT of operational amplifier OPA, and the other end is connected to the gate of NMOS tube Q1; one end of switch K15 is connected to the output end OPOUT of operational amplifier OPA, and the other end is connected to the gate of PMOS tube Q2.

[0039] The channel switching and ADC acquisition circuit includes a channel switch MUX2 and an analog-to-digital converter ADC; the voltages at points VA, VB, VC and VD are respectively controlled by the channel switch MUX2 to select V1P and V1N to acquire signals at the ADC input end.

[0040] The comparator output circuit includes comparators CMPH, CMPL and latch LATCH; the A4 port is connected to the positive input terminal of the comparator CMPH and the negative input terminal of the comparator CMPL, the negative input port of the comparator CMPH is connected to the COM port, the output terminal CMPH_OUT of the comparator CMPH is connected to the input terminal of the latch LATCH, the positive input port of the comparator CMPL is connected to VDR22, the output terminal CMPL_OUT of the comparator CMPL is connected to the other input terminal of the latch LATCH, and the latch output terminal LATCH_OUT is connected to the capture module.

[0041] If the CMPH comparator outputs a high level and the CMPL comparator outputs a low level, it is a voltage signal; if the CMPH comparator outputs a low level and the CMPL comparator outputs a high level, it is a capacitance signal; if the CMPH comparator outputs a low level and the CMPL comparator outputs a low level, it is a resistance signal.

[0042] Example 2

[0043] Based on Example 1, this embodiment implements a method for automatically measuring a voltage, resistance and capacitance circuit, and the method includes:

[0044] The voltage signal is measured by connecting the voltage signal to the A1 port through the resistor R5. The A1 port is connected to the internal switch network. The switch is switched according to different ranges. The R1 resistor is connected to the switch K11, and the switch K11 is connected to COM. And let: Res1 = R1; Res2 = R1 + R2; Res3 = R1 + R2 + R3; Res4 = R1 + R2 + R3 + R4;

[0045]

[0046]

[0047] The resistance signal is measured by connecting the resistance signal to the A2 port through the resistor R6. The A2 port is connected to the internal switch network, and the switch is switched according to different ranges. The R1 resistor is connected to the switch K12, and the switch K12 is connected to the switch K13. The other end of the switch K13 is connected to the output end of the operational amplifier OPA. The voltage at the output end of the operational amplifier is Vop, the voltage at the COM end is Vcom, the resistance to be measured is Rx, and the internal reference resistance is Rr.

[0048]

[0049] For the measurement of capacitance signal, AVDDR is connected to resistor R2 through switch K9, the other end of resistor R2 is connected to resistor R1, resistor R1 is connected to switch K12, switch K12 is connected to the source of PMOS tube Q2, the gate of PMOS tube Q2 is connected to switch K15, the other end of switch K15 is connected to the output end OPOUT of op amp OPA; the drain of PMOS tube Q2 is connected to port A2, port A2 is connected to resistor R6 to the end of the capacitor to be measured;

[0050]

[0051] V OP 、V CMPH are all voltage dividers of AVDDR, and their coefficients are set to be a and b, that is: V OP =a×AVDDR; V CMPH =b×AVDDR; Rc=R1+R2

[0052] Convert to:

[0053]

[0054] The coefficients a and b are determined by the set voltage divider ratio, Δt is obtained by the calibrated clock count inside the chip, and R C Obtained by calibration.

[0055] Example 3

[0056] Based on the above embodiment, the internal resistor strings of the chip in this embodiment are named R1, R2, R3, and R4 in order from small to large.

[0057] And let: Res1 = R1; Res2 = R1 + R2; Res3 = R1 + R2 + R3; Res4 = R1 + R2 + R3 + R4; Assume that the instrument has been calibrated;

[0058] The external voltage resistance capacitance signal is connected to the two input ports V / Ω / F and COM of the instrument. First, it is necessary to determine which signal is input. The signal to be measured passes through resistor R7 to port A4, and port A4 is connected to the input of two comparators. The COM voltage is 1.2V and the VDR22 voltage is 0.825V.

[0059] If the CMPH comparator outputs a high level and the CMPL comparator outputs a low level, it is determined to be a voltage signal. If the CMPH comparator outputs a low level and the CMPL comparator outputs a high level, it is determined to be a capacitance signal. If the CMPH comparator outputs a low level and the CMPL comparator outputs a low level, it is determined to be a resistance signal.

[0060] After the voltage signal is detected, the voltage signal is connected to the A1 port through the resistor R5. The A1 port is connected to the internal switch network. The switch is switched according to different ranges. The R1 resistor is connected to the switch K11, and the switch K11 is connected to COM. The ADC collects the signal on the internal switch resistor network. The voltage signal measurement calculation formula is as follows (Vin refers to the voltage signal to be measured):

[0061]

[0062]

[0063] After the resistance signal is detected, the resistance signal is connected to the A2 port through the resistor R6, and the A2 port is connected to the internal switch network, and the switch is switched according to different ranges. The R1 resistor is connected to the switch K12, and the switch K12 is connected to the switch K13. The other end of the switch K13 is connected to the output end OPOUT of the operational amplifier OPA; the negative input end of the operational amplifier OPA is connected to the common end of the switch K12, the switch K13, the NMOS tube Q1 and the PMOS tube Q2, and the positive input end of the operational amplifier OPA is connected to the OPIN connected to the switch K16. The other end of the switch K16 is connected to the output end of the channel switch MUX1, and MUX1 selects the reference voltage VDR20 (0.75V). The ADC collects the signal on the internal switch resistance network and the signal on the external resistance to be measured (between A4 and COM) for proportional calculation.

[0064] Assume that the voltage generated by the op amp is Vop, the voltage at the COM terminal is Vcom, the resistor to be measured is Rx, and the internal reference resistor is Rr. The output voltage Vop of the op amp in different gears may be different. One principle is to make the voltage division on Rx as large as possible. Use ADC to measure the voltage division on Rx and Rr, and the calculation formula for resistance signal measurement is as follows:

[0065] After simplification:

[0066] After the capacitor signal is detected, the capacitor is charged first. AVDDR is connected to resistor R2 through switch K9. The other end of resistor R2 is connected to resistor R1. Resistor R1 is connected to switch K12. Switch K12 is connected to the source of PMOS tube Q2. The gate of PMOS tube Q2 is connected to switch K15. The other end of switch K15 is connected to the output end OPOUT of op amp OPA. The negative input end of op amp OPA is connected to the common end of switch K12, switch K13, NMOS tube Q1 and PMOS tube Q2. The positive input end of op amp OPA is connected to OPIN and connected to switch K16. The other end of switch K16 is connected to the output end of channel switch MUX1. MUX1 selects reference voltage VDR40 (1.5V). AVDDR voltage and op amp output voltage are fixed, forming a constant current source connected to port A2 through the drain of PMOS tube Q2. Port A2 is connected to resistor R6 to the capacitor end to be measured to charge the capacitor.

[0067] VSS is connected to resistor R2 through switch K10, the other end of resistor R2 is connected to resistor R1, resistor R1 is connected to switch K12, switch K12 is connected to the source of NMOS tube Q1, the gate of NMOS tube Q1 is connected to switch K14, the other end of switch K14 is connected to the output end OPOUT of operational amplifier OPA; the drain of NMOS tube Q1 is connected to port A2, port A2 is connected to resistor R6 to the end of the capacitor to be measured to discharge the capacitor.

[0068] Use a constant current to charge the capacitor. The charging current remains constant. As charging progresses, the voltage at the capacitor terminal increases. When it reaches the threshold set by the comparator, charging stops and the time is recorded. Suppose the voltage output by the internal op amp is V OP , the comparator threshold voltage is V CMPH , the charging time is Δt, then:

[0069]

[0070] Where V OP 、V CMPH They are all divided voltages of AVDDR, and their coefficients are set to be a and b, that is:

[0071] V OP =a×AVDDR

[0072] V CMPH =b×AVDDR

[0073] Rc=R1+R2

[0074] So, it converts to:

[0075]

[0076] The coefficients a and b are determined by the set voltage divider ratio, Δt is obtained by the calibrated clock count inside the chip, and R C The accuracy is guaranteed by calibration, so theoretically the capacitance range can get the measured value without additional calibration.

[0077] By using three peripheral resistors (R5=10M, R6=390k, R7=1M), it is possible to automatically measure voltage, resistance and capacitance without using traditional relays and dial switching methods. The internal method determines which type of signal to be measured is based on the comparator result. After the signal to be measured is detected, the internal program controls the switch network to automatically determine the range for measurement.

Claims

1. A circuit for automatic measurement of voltage, resistance and capacitance, comprising an external signal input circuit, an internal switch network circuit, a reference signal output and current source generation circuit, a channel switching and ADC acquisition circuit and a comparator output circuit; the external signal input circuit is connected to the internal switch network circuit, the internal switch network circuit is connected to the channel switching and ADC acquisition circuit and the reference signal output and current source generation circuit; It is characterized in that The external signal input circuit includes resistor R5 and input port A1, resistor R6 and input port A2, resistor R7 and input port A4; the internal switch network circuit includes resistors R1, R2, R3, R4 and switches K1, K2, K3, K4, K5, K6, K7, K8, K9, K10, K11; one end of A1 is connected to resistors R4, R3, R2 and R1 respectively through switches K1, K3, K5 and K7, resistor R1 is connected to switch K11, and the other port of K11 is connected to the COM port; one end of A2 is connected to resistors R4, R3, R2 and R1 respectively through switches K2, K4, K6 and K8, and resistor R1 is connected to switch K12; AVDDR is connected to the common end of resistors R3 and R2 through switch K9; VSS is connected to the common end of resistors R3 and R2 through switch K10.

2. A circuit for automatic measurement of voltage, resistance and capacitance according to claim 1, characterized in that: The reference signal output and current source generating circuit includes switches K12, K13, K14, K15, K16, NMOS tube Q1 and PMOS tube Q2, operational amplifier OPA and channel switch MUX1; switch K12 is connected to switch K13, and the other end of switch K13 is connected to the output end OPOUT of operational amplifier OPA; the negative input end of operational amplifier OPA is connected to the common end of switch K12, switch K13, NMOS tube Q1 and PMOS tube Q2, the positive input end of operational amplifier OPA is connected to switch K16, and the other end of switch K16 is connected to the output end of channel switch MUX1; one end of switch K14 is connected to the output end OPOUT of operational amplifier OPA, and the other end is connected to the gate of NMOS tube Q1; one end of switch K15 is connected to the output end OPOUT of operational amplifier OPA, and the other end is connected to the gate of PMOS tube Q2.

3. A circuit for automatic measurement of voltage, resistance and capacitance according to claim 1, characterized in that: The channel switching and ADC acquisition circuit includes a channel switch MUX2 and an analog-to-digital converter ADC; the voltages at points VA, VB, VC and VD are respectively controlled by the channel switch MUX2 to select V1P and V1N to acquire signals at the ADC input end.

4. A circuit for automatic measurement of voltage, resistance and capacitance according to claim 1, characterized in that: The comparator output circuit includes comparators CMPH, CMPL and latch LATCH; the A4 port is connected to the positive input terminal of the comparator CMPH and the negative input terminal of the comparator CMPL, the negative input port of the comparator CMPH is connected to the COM port, the output terminal CMPH_OUT of the comparator CMPH is connected to the input terminal of the latch LATCH, the positive input port of the comparator CMPL is connected to VDR22, the output terminal CMPL_OUT of the comparator CMPL is connected to the other input terminal of the latch LATCH, and the latch output terminal LATCH_OUT is connected to the capture module.

5. The circuit for automatic voltage, resistance and capacitance measurement according to claim 1, characterized in that: When the CMPH comparator outputs a high level and the CMPL comparator outputs a low level, the input signal is determined to be a voltage signal; when the CMPH comparator outputs a low level and the CMPL comparator outputs a high level, the input signal is determined to be a capacitance signal; when the CMPH comparator outputs a low level and the CMPL comparator outputs a low level, the input signal is determined to be a resistance signal.

6. A method for automatic measurement of voltage, resistance and capacitance, characterized in that: A circuit for automatic measurement of voltage, resistance and capacitance comprising any one of claims 1 to 5, wherein the method comprises: The voltage signal is measured by connecting the voltage signal to the A1 port through the resistor R5. The A1 port is connected to the internal switch network. The switch is switched according to different ranges. The R1 resistor is connected to the switch K11, and the switch K11 is connected to COM. Let Res1 = R1; Res2 = R1 + R2; Res3 = R1 + R2 + R3; Res4 = R1 + R2 + R3 + R4; The resistance signal is measured by connecting the resistance signal to the A2 port through the resistor R6. The A2 port is connected to the internal switch network, and the switch is switched according to different ranges. The R1 resistor is connected to the switch K12, and the switch K12 is connected to the switch K13. The other end of the switch K13 is connected to the output end of the operational amplifier OPA. The voltage at the output end of the operational amplifier is Vop, the voltage at the COM end is Vcom, the resistance to be measured is Rx, and the internal reference resistance is Rr. For the measurement of capacitance signal, AVDDR is connected to resistor R2 through switch K9, the other end of resistor R2 is connected to resistor R1, resistor R1 is connected to switch K12, switch K12 is connected to the source of PMOS tube Q2, the gate of PMOS tube Q2 is connected to switch K15, the other end of switch K15 is connected to the output end OPOUT of op amp OPA; the drain of PMOS tube Q2 is connected to port A2, port A2 is connected to resistor R6 to the end of the capacitor to be measured; V OP 、V CMPH They are all divided voltages of AVDDR, and their coefficients are set to be a and b, that is: V OP =a×AVDDR;V CMPH =b×AVDDR;Rc=R1+R2 Convert to: The coefficients a and b are determined by the set voltage divider ratio, Δt is obtained by the calibrated clock count inside the chip, and R C Obtained by calibration.

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