Semiconductor structure and method for forming the same
By etching the grooves with a depth equal to the thickness in the non-optical transmission area of the optical transmission layer, the bending problem caused by the increase in the film structure of the silicon-based optoelectronic chip is solved, the flatness and vacuum degree are improved, and the processing of semiconductor structures is ensured. quality.
Patent Information
- Application Number
- CN202010376870.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2020-05-07
- Publication Date
- 2024-12-13
- Estimated Expiration
- 2040-05-07
AI Technical Summary
The increase in the thickness of the multi-layer film structure of silicon-based optoelectronic chips leads to the bending of the wafer and the flatness decreases. When it exceeds 200nm, the vacuum degree is insufficient and the process cannot be passed.
The first groove is etched in the non-optical transmission area of the optical transmission layer, and the groove depth is at least equal to the thickness of the optical transmission layer to divide the optical transmission layer, release stress, and reduce the curvature of the semiconductor structure.
By reducing the stress of the optical transmission layer, improving the flatness of the semiconductor structure, ensuring the vacuum requirement during the processing process, avoiding machine alarms, and ensuring product overstocking.
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Figure CN113629165B_ABST
Abstract
Description
Technical Field
[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art
[0002] Silicon-based optoelectronic chips will be deployed in high-speed signal transmission systems to replace existing copper wire transmission. The performance bottleneck of high-performance computing systems has shifted from processors to communication infrastructure, and optical interconnects can provide high-bandwidth, low-latency solutions to address the challenges of bandwidth scalability in future computing systems.
[0003] However, once the thickness of the multilayer film structure of silicon-based optoelectronic chips exceeds This will cause the wafer to bend and the flatness to decrease. As the membrane structure thickens, when the wafer curvature exceeds 200nm, the flatness will decrease, leading to insufficient vacuum, which will cause the machine to alarm and make it impossible to pass goods.
[0004] In view of this, how to reduce the curvature of the semiconductor structure has become a technical problem that technical personnel in this field need to solve urgently. Summary of the invention
[0005] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, so as to reduce the curvature of the semiconductor structure.
[0006] To solve the above problems, an embodiment of the present invention further provides a method for forming a semiconductor structure, comprising:
[0007] Providing a wafer substrate;
[0008] forming a light transmission layer, wherein the light transmission layer covers the front surface of the wafer substrate;
[0009] The non-light path transmission area of the light transmission layer is etched to form a first groove, wherein the depth of the first groove is at least equal to the thickness of the light transmission layer.
[0010] Accordingly, an embodiment of the present invention provides a semiconductor structure, including:
[0011] Wafer substrate;
[0012] A light transmission layer, wherein the light transmission layer covers the front surface of the wafer substrate;
[0013] A first groove is formed in the non-light path transmission area of the light transmission layer, and the depth of the first groove is at least equal to the thickness of the light transmission layer.
[0014] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:
[0015] The method for forming a semiconductor structure provided in an embodiment of the present invention first provides a wafer substrate, and then forms a light transmission layer on the front side of the wafer substrate, and forms a first groove by etching a non-light path transmission area of the light transmission layer, wherein the depth of the first groove is at least equal to the thickness of the light transmission layer. In this way, the setting of the first groove in the light transmission layer is equivalent to dividing the light transmission layer, reducing the area of the light transmission layer that is connected into one piece, thereby releasing the stress of the light transmission layer, thereby reducing the curvature of the semiconductor structure caused by the stress, improving the flatness of the semiconductor structure, and ensuring the vacuum requirement during the processing of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] Figures 1 to 8 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure according to an embodiment of the present invention;
[0017] Fig. 9 It is a structural schematic diagram of an embodiment of a semiconductor structure according to an embodiment of the present invention. DETAILED DESCRIPTION
[0018] As can be seen from the background technology, the thickness of the multilayer film structure of silicon-based optoelectronic chips> It will cause the wafer to bend and the flatness to decrease. As the membrane structure thickens, when the wafer curvature exceeds 200nm, the flatness will decrease, resulting in insufficient vacuum, which will cause the machine to alarm and make it impossible to pass goods.
[0019] In order to reduce the curvature of the semiconductor structure, an embodiment of the present invention provides a method for forming a semiconductor structure, first providing a wafer substrate, and then forming a light transmission layer on the front side of the wafer substrate, and forming a first groove by etching the non-light path transmission area of the light transmission layer, wherein the depth of the first groove is at least equal to the thickness of the light transmission layer. In this way, the provision of the first groove in the light transmission layer is equivalent to dividing the light transmission layer, reducing the area of the light transmission layer connected into one piece, thereby releasing the stress of the light transmission layer, and further reducing the curvature of the semiconductor structure caused by the stress, improving the flatness of the semiconductor structure, and ensuring the vacuum requirement during the processing of the semiconductor structure.
[0020] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present invention more obvious and easy to understand, specific embodiments of the embodiments of the present invention are described in detail below with reference to the accompanying drawings.
[0021] Please refer to Figure 1-Figure 8 , Figures 1 to 8 The semiconductor structure provided by the embodiment of the present invention will be described in detail below in conjunction with the accompanying drawings.
[0022] refer to Figure 1-Figure 3 , providing a wafer substrate 10 (shown in Figure 3 The wafer substrate 10 includes a wafer 300, a first gate structure 100 and a second gate structure 200, wherein the first gate structure 100 covers the front side of the wafer 300, and the second gate structure 200 covers the back side of the wafer 300. In this embodiment, the wafer 300 is a silicon substrate. In other embodiments, the wafer 300 may also be a substrate of other materials such as a germanium substrate, a silicon germanium substrate, a silicon carbide substrate, a gallium arsenide substrate or an indium gallium substrate.
[0023] It is understood that the front side of the wafer 300 described herein refers to Figure 1 The upper surface of the wafer 300; similarly, the back side of the wafer described in this article refers to Figure 1 The lower surface of the wafer 300 .
[0024] Specifically, refer to Figure 1-Figure 3 , the formation process of the wafer substrate 10 includes:
[0025] The first gate structure 100 is formed on the front side of the wafer 300 , and the second gate structure 200 is formed on the back side of the wafer 300 .
[0026] In a specific implementation, the first gate structure 100 may be formed by the following steps, specifically including:
[0027] like Figure 1 As shown, first, a first oxide layer 101 is formed, and the first oxide layer 101 covers the front side of the wafer 300 .
[0028] The material of the first oxide layer 101 is silicon oxide. In one embodiment, the first oxide layer 101 may be formed by a furnace tube growth process. In other embodiments, the first oxide layer may also be formed by chemical deposition.
[0029] Then, a first gate layer 111 is formed, which covers the first oxide layer 101. The material of the first gate layer 111 is polysilicon. In one embodiment, the first gate layer 111 is formed by a furnace tube growth process. In other embodiments, the first gate layer can also be formed by chemical deposition.
[0030] A second oxide layer 102 is then formed, and the second oxide layer 102 covers the first gate layer 111; the material of the second oxide layer 102 is silicon oxide. In one embodiment, the second oxide layer 102 is formed by a furnace tube growth process. In other embodiments, the second oxide layer can also be formed by chemical deposition.
[0031] Then, a second gate layer 112 is formed, and the second gate layer 112 covers the second oxide layer 102. The material of the second gate layer 112 can be polysilicon. In one embodiment, the second gate layer 112 is formed by a furnace tube growth process. In other embodiments, the second gate layer can also be formed by chemical deposition.
[0032] The second gate layer 112, the second oxide layer 102 and the first gate layer 111 provide a basis for subsequent light reflection. In this embodiment, the first gate structure 100 includes two gate layers, the first gate layer 111 and the second gate layer 112, which can improve the effect of light reflection and thus help improve the light transmission effect.
[0033] Of course, in other embodiments, the first gate structure 100 may also include only one gate layer or more gate layers.
[0034] Furthermore, if Figure 2 As shown, after the second gate layer 112 is formed, the second gate layer 112, the second oxide layer 102 and the first gate layer 111 are patterned to form an opening 113, and the opening 113 exposes the first oxide layer 101;
[0035] Finally, if Figure 3 As shown, a third oxide layer 103 is formed, and the third oxide layer 103 fills the opening 113 and covers the second gate layer 112. In this embodiment, the third oxide layer 103 can be formed by a chemical vapor deposition process. The material of the third oxide layer 103 can be silicon dioxide. In other embodiments, the third oxide layer 103 can also be other insulating materials.
[0036] It can be seen that after the above steps, the first gate structure 100 on the front side of the wafer can be obtained. By adopting the above steps, the first gate structure 100 that meets the performance requirements can be obtained conveniently and simply.
[0037] Of course, in other implementations, the first gate structure 100 may also be obtained by other methods.
[0038] Combination Figure 1 and Figure 2 In a specific implementation, in order to obtain the second gate structure 200, the following steps may be performed, specifically including:
[0039] First, a fourth oxide layer 204 is formed, and the fourth oxide layer 204 covers the back side of the wafer 300;
[0040] The material of the fourth oxide layer 204 is silicon oxide. In one embodiment, the fourth oxide layer may be formed by a furnace tube growth process. In other embodiments, the fourth oxide layer may also be formed by chemical deposition.
[0041] Then, a third gate layer 213 is formed, and the third gate layer 213 covers the fourth oxide layer 204;
[0042] The material of the third gate layer 213 is polysilicon. In one embodiment, the third gate layer 213 is formed by a furnace tube growth process. In other embodiments, the third gate layer may also be formed by chemical deposition.
[0043] Then forming a fifth oxide layer 205, wherein the fifth oxide layer 205 covers the third gate layer 213;
[0044] The material of the fifth oxide layer 205 is silicon oxide. In one embodiment, the fifth oxide layer is formed by a furnace tube growth process. In other embodiments, the fifth oxide layer may also be formed by chemical deposition.
[0045] forming a fourth gate layer 214, wherein the fourth gate layer 214 covers the fifth oxide layer 205;
[0046] The material of the fourth gate layer 214 may be polysilicon. In one embodiment, the fourth gate layer 214 is formed by a furnace tube growth process. In other embodiments, the fourth gate layer may also be formed by chemical deposition.
[0047] The fourth gate layer 214 is removed; in this embodiment, the fourth gate layer 214 may be removed by a wet etching process.
[0048] The fifth oxide layer 205 is planarized.
[0049] In this way, the second gate structure 200 on the back side of the wafer can be obtained by using a wet etching process, which has a high etching selectivity and convenient process operation.
[0050] In this embodiment, the first oxide layer 101 and the fourth oxide layer 204 can be formed at the same time, that is, the first oxide layer 101 and the fourth oxide layer 204 are grown on both sides (front and back) of the wafer 300 by using a furnace tube growth process; at the same time, the first gate layer 111 and the third gate layer 213 can also be formed at the same time by using a furnace tube growth process, covering the first oxide layer 101 and the fourth oxide layer 204 respectively; the second oxide layer 102 and the fifth oxide layer 205 are also formed at the same time by using a furnace tube growth process, covering the first gate layer 111 and the third gate layer 213 respectively for growth; the second gate layer 112 and the fourth gate layer 214 are also formed at the same time by using a furnace tube growth process, covering the first gate layer 111 and the third gate layer 213 respectively for growth. Since the furnace tube growth process is to grow thin films on the front and back of the wafer 300 at the same time, it can ensure that the compressive stress on the front of the wafer 300 and the tensile stress on the back are offset, thereby ensuring the flatness of the wafer 300.
[0051] Of course, in other embodiments, thin film deposition may also be performed independently on the front and back sides of the wafer 300 to form the above-mentioned layer structures.
[0052] In this embodiment, the material of the first oxide layer 101 or the second oxide layer 102 is silicon dioxide. In other embodiments, the first oxide layer 101 or the second oxide layer 102 may also be other insulating materials.
[0053] refer to Figure 4 After obtaining the wafer substrate 10, a light transmission layer 400 is then formed, and the light transmission layer 400 covers the front surface of the wafer substrate 10. In this embodiment, the light transmission layer is formed by chemical deposition.
[0054] The optical transmission layer 400 is used for optical signal transmission and includes an optical path transmission area and a non-optical path transmission area. The optical signal is transmitted in the optical path transmission area of the optical transmission layer 400.
[0055] In this embodiment, the material of the light transmission layer 400 is silicon nitride.
[0056] refer to Figure 5 , etching the non-light path transmission area of the light transmission layer 400 to form a first groove 401, wherein the depth of the first groove 401 is at least equal to the thickness of the light transmission layer 400.
[0057] The depth of the first groove 401 is at least equal to the thickness of the light transmission layer 400 to ensure that the first groove 401 can penetrate the light transmission layer 400 along the thickness direction of the light transmission layer 400 to achieve the effect of releasing stress, and the non-light path transmission area of the light transmission layer 400 is etched so that the formation of the first groove 401 will not affect light transmission and achieve stress release at the same time.
[0058] In the process of semiconductor structure processing, in order to ensure that the first groove 401 can completely penetrate the light transmission layer 400 along the thickness direction of the light transmission layer 400, in a specific embodiment, the depth of the first groove 401 can exceed the thickness of the light transmission layer 400. Considering that if the specific value exceeding the thickness of the light transmission layer 400 is less than When the first groove is processed, it is difficult to control the processing. Therefore, in a specific embodiment, the specific thickness range of the excess thickness can be greater than or equal to Thus, the machining accuracy of the first groove 401 can be reduced while ensuring that the first groove 401 completely penetrates the light transmission layer. Figure 5 As shown, the size of H is greater than or equal to
[0059] Specifically, the shape of the first groove 401 is not limited. In one embodiment, the cross-sectional shape of the first groove 401 perpendicular to the depth direction may be an inverted trapezoid, and the side wall of the first groove 401 forms an acute angle with the vertical plane. In other embodiments, the first groove 401 may also be a rectangle, V-shape or other shapes, as long as the first groove 401 can completely penetrate the light transmission layer 400 along the thickness direction of the light transmission layer 400.
[0060] In order to further release the stress, the first groove 401 can extend from the first end of the light transmission layer 400 to the other end opposite to the first end. In this way, the first groove 401 divides the light transmission layer 400 into multiple pieces, thereby reducing the area of the light transmission layer connected into one piece, further releasing the stress of the light transmission layer, and further reducing the curvature of the semiconductor structure caused by the stress.
[0061] Specifically, please refer to Figure 6 , Figure 6 yes Figure 5 It can be seen that the first groove 401 extends through the first end and the other end opposite to the first end. The first groove 401 can be as follows Figure 6 The straight extension is shown in the figure. In other embodiments, the first groove 401 may also be a curved extension, as long as the first groove 401 passes through the first end and the other end opposite to the first end in the extension direction.
[0062] In one embodiment, in order to improve the effect of releasing stress, the opening size of the first groove 401 is greater than or equal to 500nm. For example, the opening size may be 550nm, 600nm or greater than or equal to 650nm. As the opening size increases, the stress release effect of the light transmission layer becomes more obvious, thereby further improving the flatness of the wafer. Figure 6 W represents the opening size.
[0063] It should be noted that the first groove 401 can be opened in any area of the non-light path transmission area of the light transmission layer 400, so the number of the first grooves 401 can be at least 2, such as 3, 4 or 5. When multiple first grooves 401 are opened, the stress of the light transmission layer 400 can be further released and the curvature of the semiconductor structure can be reduced.
[0064] Next reference Figure 7 After forming the first groove 401, in order to ensure the subsequent processing of the semiconductor structure, the following steps are further included:
[0065] An insulating layer 500 is formed on the light transmission layer 400 , and the insulating layer 500 fills the first groove 401 and covers the light transmission layer 400 .
[0066] The insulating layer 500 can isolate and protect the light transmission layer 400. According to the process requirements, the thickness of the insulating layer 500 is relatively thick. If the light transmission layer 400 does not have the first groove 401, after the insulating layer 500 is deposited on the light transmission layer 400, the compressive stress will be further increased, thereby causing the curvature of the wafer 300 to be too large.
[0067] In the present embodiment, since the first groove 401 is opened in the light transmission layer 400, after the insulating layer 500 is deposited, the material of the insulating layer 500 is silicon dioxide, and the material of the light transmission layer 400 is silicon nitride. The stress of silicon nitride is greater than the stress of silicon oxide, so the stress of the light transmission layer 400 is greater than the stress of the insulating layer 500. By filling the first groove 401 with the insulating layer 500, the stress of the wafer 300 can be further reduced.
[0068] In order to further reduce the stress of the semiconductor structure, refer to Figure 8 In another specific implementation, the method for forming a semiconductor structure provided by the embodiment of the present invention may further include:
[0069] A stress layer 600 is formed, and the stress layer 600 covers the back side of the wafer substrate 10 .
[0070] The stress layer 600 covers the back side of the wafer substrate 10 . For the wafer 300 , the stress of the stress layer 600 is tensile stress. By forming the stress layer 600 on the back side of the wafer substrate 10 , a part of the compressive stress on the front side of the wafer 300 can be offset, thereby further reducing the curvature of the wafer 300 .
[0071] In this embodiment, the material of the stress layer is silicon nitride. Silicon nitride has a high stress, which can not only reduce the stress of the wafer, but also ensure that the height of the entire semiconductor structure is not too high, thereby reducing the size of the semiconductor structure. Taking compressive stress as positive and tensile stress as negative, in one embodiment, the stress value of the stress layer is less than -1500Mpa. By selecting high-stress silicon nitride as the stress layer, the thickness of the stress layer can be reduced, further reducing the overall height of the semiconductor structure.
[0072] Of course, in other embodiments, the material of the stress layer may also be silicon oxynitride or silicon dioxide.
[0073] The order of forming the stress layer and the insulating layer is not limited. The stress layer may be formed first and then the insulating layer, or the stress layer may be formed after the insulating layer is deposited.
[0074] The present invention also provides a semiconductor structure. Fig. 9 , Fig. 9 It is a structural schematic diagram of an embodiment of a semiconductor structure according to an embodiment of the present invention.
[0075] like Fig. 9 As shown, the semiconductor structure provided by the embodiment of the present invention includes:
[0076] Wafer substrate (not shown in the figure);
[0077] A light transmission layer 40, wherein the light transmission layer 40 covers the front surface of the wafer substrate;
[0078] A first groove 41 is formed in the non-light path transmission area of the light transmission layer 40 . The depth of the first groove 41 is at least equal to the thickness of the light transmission layer 40 .
[0079] In the semiconductor structure provided by the embodiment of the present invention, the setting of the first groove in the light transmission layer is equivalent to dividing the light transmission layer, reducing the area of the light transmission layer that is connected as a whole, thereby releasing the stress of the light transmission layer, thereby reducing the curvature of the semiconductor structure caused by the stress, improving the flatness of the semiconductor structure, and ensuring the vacuum requirement during the processing of the semiconductor structure.
[0080] The depth of the first groove 41 is at least equal to the thickness of the light transmission layer 40, so as to ensure that the first groove 41 can penetrate the light transmission layer 40 in the thickness direction of the light transmission layer 40, so as to achieve the effect of releasing stress. By arranging the first groove 41 in the non-light path transmission area of the light transmission layer 40, the formation of the first groove 41 will not affect light transmission, and stress release is achieved at the same time.
[0081] In a specific embodiment, the depth of the first groove 41 exceeds the thickness of the light transmission layer 40 by at least On the basis of ensuring that the first groove 41 can completely penetrate the light transmission layer 40 along the thickness direction of the light transmission layer 40 , the processing accuracy of the first groove 41 is reduced.
[0082] The shape of the first groove 41 is not limited. In one embodiment, the cross-sectional shape of the first groove 41 perpendicular to the depth direction can be an inverted trapezoid, and the side wall of the first groove 41 forms an acute angle with the vertical plane. In other embodiments, the first groove 41 can also be a rectangle, V-shape or other shapes, as long as the first groove 41 can completely penetrate the light transmission layer 40 along the thickness direction of the light transmission layer 40.
[0083] In order to further release the stress, the first groove 41 extends from the first end of the light transmission layer 40 to the other end opposite to the first end. In this way, the first groove 41 divides the light transmission layer 40 into multiple pieces, thereby reducing the area of the light transmission layer connected into one piece, further releasing the stress of the light transmission layer, and further reducing the curvature of the semiconductor structure caused by the stress.
[0084] The first groove 41 may be a straight extension or a curved extension, as long as the first groove 41 passes through the first end and the other end opposite to the first end in the extension direction.
[0085] In one embodiment, in order to improve the effect of releasing stress, the opening size of the first groove 41 is greater than or equal to 500nm. For example, the opening size may be 550nm, 600nm or greater than or equal to 650nm. As the opening size increases, the stress release effect of the light transmission layer becomes more obvious, thereby further improving the flatness of the wafer.
[0086] It should be noted that the first groove 41 can be opened in any area of the non-light path transmission area of the light transmission layer 40, so the number of the first grooves 41 can be at least 2, such as 3, 4 or 5. When multiple first grooves 41 are opened, the stress of the light transmission layer 400 can be further released and the curvature of the semiconductor structure can be reduced.
[0087] The wafer substrate 10 includes a wafer 300, a first gate structure 100 and a second gate structure 200, wherein the first gate structure 100 covers the front side of the wafer 300, and the second gate structure 200 covers the back side of the wafer 300. In this embodiment, the wafer 300 is a silicon substrate. In other embodiments, the wafer 300 may also be a substrate of other materials such as a germanium substrate, a silicon germanium substrate, a silicon carbide substrate, a gallium arsenide substrate or an indium gallium substrate.
[0088] The first gate structure 70 includes:
[0089] A first oxide layer 701, wherein the first oxide layer 701 covers the front side of the wafer 30;
[0090] A first gate layer 711, wherein the first gate layer 711 covers a portion of the first oxide layer 701;
[0091] A second oxide layer 702, wherein the second oxide layer 702 covers the first gate layer 711 and the first oxide layer 701;
[0092] A second gate layer 712, wherein the second gate layer 712 covers a portion of the second oxide layer 702;
[0093] The third oxide layer 703 covers the second gate layer 712 and the second oxide layer 702 .
[0094] The first gate structure 70 provides a basis for the subsequent growth of the light transmission layer. The second gate layer 712, the second oxide layer 702 and the first gate layer 711 provide a basis for the subsequent light reflection. In this embodiment, the first gate structure 70 includes two gate layers, the first gate layer 711 and the second gate layer, which can improve the effect of light reflection and thus help improve the light transmission effect. Of course, in other embodiments, the first gate structure 70 may also include only one gate layer or more gate layers.
[0095] In this embodiment, the material of the first oxide layer 701, the second oxide layer 702 or the third oxide layer 703 is silicon dioxide. In other embodiments, the first oxide layer 701, the second oxide layer 702 or the third oxide layer 703 may also be other insulating materials. The material of the first gate layer and the second gate layer is polysilicon.
[0096] The wafer substrate also includes:
[0097] The second gate structure 80 covers the back side of the wafer 30 , and the stress layer 60 covers the second gate structure 80 .
[0098] The second gate structure 80 includes:
[0099] A fourth oxide layer 804 , wherein the fourth oxide layer 804 covers the back side of the wafer 30 ;
[0100] A third gate layer 813, wherein the third gate layer 813 covers the fourth oxide layer 804;
[0101] The fifth oxide layer 805 covers the third gate layer 813 .
[0102] In this embodiment, the material of the fourth oxide layer 804 or the fifth oxide layer 805 is silicon dioxide. In other embodiments, the material of the fourth oxide layer 804 or the fifth oxide layer 805 may also be other insulating materials. The material of the third gate layer 813 is polysilicon.
[0103] In this embodiment, the first gate structure 70 is located on the front side of the wafer 300, the second gate structure 80 is located on the back side of the wafer, the first oxide layer 701 and the fourth oxide layer 804 have the same thickness and material, and the first gate layer 711 and the third gate layer 813 have the same thickness and material, which can ensure that the compressive stress on the front side of the wafer 300 and the tensile stress on the back side are partially offset, thereby ensuring the flatness of the wafer 300.
[0104] like Fig. 9 As shown, the semiconductor structure provided by the embodiment of the present invention further includes an insulating layer 50 , and the insulating layer 50 fills the first groove 41 and covers the light transmission layer 40 .
[0105] The insulating layer 50 is used to isolate and protect the light transmission layer 40. According to the process requirements, the thickness of the insulating layer 50 is relatively thick. If the light transmission layer 40 does not have the first groove 41, after the insulating layer 50 is deposited on the light transmission layer 40, it will further lead to an increase in compressive stress, thereby causing the curvature of the wafer 30 to be too large. In this embodiment, because the first groove 41 is opened in the light transmission layer 40, after the insulating layer 50 is deposited, the material of the insulating layer 50 is silicon dioxide, and the material of the light transmission layer 40 is silicon nitride. The stress of silicon nitride is greater than the stress of silicon oxide, so that the stress of the light transmission layer 40 is greater than the stress of the insulating layer 50. By filling the first groove 41 with the insulating layer 50, the stress of the wafer 30 can be further reduced.
[0106] Continue to refer Fig. 9 , the semiconductor structure further comprises:
[0107] The stress layer 60 covers the back side of the wafer substrate.
[0108] The stress layer 60 covers the back side of the wafer substrate. For the wafer 30 , the stress of the stress layer 60 is tensile stress. By forming the stress layer 60 on the back side of the wafer substrate, part of the compressive stress on the front side of the wafer 30 can be offset, thereby further reducing the curvature of the wafer 30 .
[0109] In this embodiment, the material of the stress layer 60 is silicon nitride. Silicon nitride has a relatively high stress, which can not only reduce the stress of the wafer 30, but also ensure that the height of the entire semiconductor structure is not too high, thereby reducing the size of the semiconductor structure. With compressive stress as positive and tensile stress as negative, in one embodiment, the stress value of the stress layer 60 is less than -1500Mpa. By selecting high-stress silicon nitride as the stress layer, the thickness of the stress layer can be reduced, further reducing the overall height of the semiconductor structure.
[0110] Of course, in other embodiments, the material of the stress layer may also be silicon oxynitride or silicon dioxide.
[0111] Although the embodiments of the present invention are disclosed above, the embodiments of the present invention are not limited thereto. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the embodiments of the present invention. Therefore, the protection scope of the embodiments of the present invention shall be subject to the scope defined by the claims.
Claims
1. A method for forming a semiconductor structure, It is characterized in that include: Providing a wafer substrate, the wafer substrate comprising a wafer; the step of providing the wafer substrate comprises forming a third oxide layer on the wafer, the wafer substrate further comprising a first gate structure, the first gate structure covering the front side of the wafer; forming a light transmission layer, wherein the light transmission layer covers the front surface of the wafer substrate; A non-light path transmission area of the light transmission layer is etched, wherein the non-light path transmission area is an area that does not overlap with the first gate structure in a direction perpendicular to the wafer substrate, to form a first groove, wherein the depth of the first groove exceeds the thickness of the light transmission layer, and a third oxide layer of a partial thickness is etched in the step of forming the first groove.
2. The method for forming a semiconductor structure according to claim 1, It is characterized in that In a direction parallel to the wafer substrate, the first groove extends in an extending direction from a first end of the light transmission layer to another end opposite to the first end.
3. The method for forming a semiconductor structure according to claim 1, It is characterized in that The opening size of the first groove is greater than or equal to 500 nm.
4. The method for forming a semiconductor structure according to claim 1, It is characterized in that The depth of the first groove is at least 5. The method for forming a semiconductor structure according to claim 1, It is characterized in that The number of the first grooves is at least 2.
6. The method for forming a semiconductor structure according to any one of claims 1 to 5, It is characterized in that Also includes: A stress layer is formed, wherein the stress layer covers the back side of the wafer substrate.
7. The method for forming a semiconductor structure according to any one of claims 1 to 5, It is characterized in that After forming the first groove, the method further includes: An insulating layer is formed on the light transmission layer, wherein the insulating layer fills the first groove and covers the light transmission layer.
8. The method for forming a semiconductor structure according to claim 1, It is characterized in that The step of forming the first gate structure includes: forming a first oxide layer, wherein the first oxide layer covers the front side of the wafer; forming a first gate layer, wherein the first gate layer covers the first oxide layer; forming a second oxide layer, wherein the second oxide layer covers the first gate layer; forming a second gate layer, wherein the second gate layer covers the second oxide layer; Patterning the second gate layer, the second oxide layer, and the first gate layer to form an opening, wherein the opening exposes the first oxide layer; The third oxide layer fills the opening and covers the second gate layer.
9. The method for forming a semiconductor structure according to claim 8, It is characterized in that The wafer substrate further includes a second gate structure, and the second gate structure covers the back side of the wafer.
10. The method for forming a semiconductor structure according to claim 9, It is characterized in that The step of forming the second gate structure comprises: forming a fourth oxide layer, wherein the fourth oxide layer covers the back side of the wafer; forming a third gate layer, wherein the third gate layer covers the fourth oxide layer; forming a fifth oxide layer, wherein the fifth oxide layer covers the third gate layer; forming a fourth gate layer, wherein the fourth gate layer covers the fifth oxide layer; removing the fourth gate layer; The fifth oxide layer is planarized.
11. The method for forming a semiconductor structure according to claim 10, It is characterized in that The process of removing the fourth gate layer is a wet etching process.
12. The method for forming a semiconductor structure according to claim 10, It is characterized in that The process of forming the first gate layer and the process of forming the third gate layer is a furnace tube growth process.
13. A semiconductor structure, It is characterized in that include: A wafer substrate, the wafer substrate comprising a wafer and a third oxide layer located on the wafer, the wafer substrate further comprising a first gate structure, the first gate structure covering the front side of the wafer; A light transmission layer, wherein the light transmission layer covers the front surface of the wafer substrate; A first groove is provided in the non-optical path transmission area of the light transmission layer, and the non-optical path transmission area is an area that does not overlap with the first gate structure in a direction perpendicular to the wafer substrate. The depth of the first groove exceeds the thickness of the light transmission layer, and a third oxide layer of a partial thickness is etched in the step of forming the first groove.
14. The semiconductor structure according to claim 13, It is characterized in that Also includes: A stress layer covers the back side of the wafer substrate.
15. The semiconductor structure according to claim 14, It is characterized in that The material of the stress layer is silicon nitride.
16. The semiconductor structure according to claim 15, It is characterized in that The stress value of the stress layer is less than -1500Mpa.
17. The semiconductor structure according to any one of claims 13 to 16, It is characterized in that Also includes: An insulating layer fills the first groove and covers the light transmission layer.
18. The semiconductor structure according to any one of claims 13 to 16, It is characterized in that The light transmission layer covers the first gate structure.
19. The semiconductor structure according to any one of claims 14 to 16, It is characterized in that The wafer substrate also includes: A second gate structure is provided, wherein the second gate structure covers the back side of the wafer, and the stress layer covers the second gate structure.