A clock frequency division module, a digital-to-analog conversion circuit and a method for controlling audio playback and stopping

Abstract

The present invention discloses a clock frequency division module, a digital-to-analog conversion circuit and a method with controllable audio playback and pause. The present invention adopts a new audio DAC architecture, optimizes a large number of multiplication and addition operations, combinational logic and registers in the traditional architecture, and greatly reduces the hardware area and design complexity; at the same time, it solves the limitation of strict requirements on the working clock frequency of the audio DAC circuit, and can support audio with different sampling rates, which is more flexible in application and design; in addition, the present invention also has the function of delaying the closing of the work enable, so that when the circuit is closed and reopened, the CIC filter can correctly interpolate to avoid the phenomenon of popping sound. If no delay is performed, the pause and play of the audio cannot be normally controlled.

Description

Technical Field

[0001] The present invention relates to the field of DAC digital circuits, and in particular to a clock frequency division module, a digital-to-analog conversion circuit and a method for controllable audio playback and stop. Background Art

[0002] Generally, there is little need to pause the DAC (digital-to-analog converter) broadcast in simple audio playback applications such as sweepers. However, if the function of pausing the DAC broadcast and then reopening it to continue broadcasting is implemented, it will make the DAC more flexible in various devices and different scenarios, making it more widely used. For this type of DAC, if the DAC is directly turned off and on, it will appear that during the period from the DAC enable to the DAC enable, due to the lack of judgment means, it is impossible to know how many data the CIC filter (integral-cascade-comb filter) has interpolated, and after it is turned on, it will be re-interpolated, resulting in data calculation overflow errors and popping sounds, making it impossible to pause and restart the DAC broadcast in the application. Summary of the invention

[0003] To solve the above problems, the present invention provides a clock frequency division module, a digital-to-analog conversion circuit and method with controllable audio playback and pause, which can avoid the popping sound phenomenon, realize the pause and restart of DAC playback, and also support multiple working clocks and audio sampling rates. The specific technical solutions of the present invention are as follows:

[0004] A clock frequency division module, the module comprising: a divider, used to receive a first frequency division parameter and perform a division operation to obtain a second frequency division parameter; wherein the dividend is a preset value; a first counter, connected to the divider, used to count a working clock according to the second frequency division parameter to obtain a first counting sequence; a first register, connected to the first counter, used to divide the working clock according to the first counting sequence to obtain a data processing enable signal of a CIC filter and its frequency value; a second counter, connected to the first register, used to count the data processing enable signal of the CIC filter according to the preset value to obtain a second counting sequence; a second register, connected to the first register, used to delay the data processing enable signal of the CIC filter to obtain a delayed enable signal; a third register, respectively connected to the second counter and the second register, used to divide the working clock according to the second counting sequence The working clock is divided by the delay enable signal to obtain the read enable signal of the asynchronous FIFO module and its frequency value; the fourth register is connected to the second counter and is used to delay the second counting sequence to obtain the delay sequence; the AND gate is connected to the fourth register and is used to perform an AND operation on the delay sequence and the audio digital-to-analog conversion circuit enable signal; the enable data selector is connected to the AND gate and selects the audio digital-to-analog conversion circuit enable signal or the preset level signal as the working enable according to the AND operation result; wherein, when the value of the delay sequence is the difference between the preset value and 1, the enable data selector selects the audio digital-to-analog conversion circuit enable signal as the working enable, otherwise selects the preset level signal as the working enable; wherein the preset level signal can enable the module to work normally; wherein the data processing enable signal of the CIC filter and the read enable signal of the asynchronous FIFO module are phase synchronized.

[0005] Compared with the prior art, the technical solution can correctly generate the sampling rate of the original audio data by dividing the working clock, and thus supports audio data sources with various sampling rates; the third register divides the working clock according to the second counting sequence and the delay enable signal, so that the data processing enable signal of the CIC filter and the read enable signal of the asynchronous FIFO module can be kept synchronized without generating phase deviation, thereby ensuring the accuracy of data reading; in addition, it is set that the audio digital-to-analog conversion circuit enable signal is used as the working enable only when the value of the delay sequence is the difference between the preset value and 1, and the audio digital-to-analog conversion circuit enable signal can be turned off to produce the effect of delaying the closure of the enable signal when the audio digital-to-analog conversion circuit enable signal is turned off. During the delay period, the clock division module can normally output the data processing enable signal of the CIC filter and the read enable signal of the asynchronous FIFO module.

[0006] Furthermore, the first counter counts the rising edges of the working clock, and resets to zero every time the counted number reaches the value of the second frequency division parameter.

[0007] Furthermore, the first register sets the data processing enable signal of the CIC filter to a high level at each value before zero in the first counting sequence, and sets it to a low level in other cases, and its frequency value is the quotient of the working clock and the second frequency division parameter. The data processing enable signal of the CIC filter is generated to oversample the data and improve the quality of the data.

[0008] Furthermore, the second counter counts the rising edges of the data processing enable signal of the CIC filter, and resets to zero whenever the counted number reaches a preset value.

[0009] Furthermore, the delay time of the second register to the data processing enable signal of the CIC filter, and the delay time of the fourth register to the second counting sequence are both preset number of working clock cycles, which can ensure that the data processing enable signal of the CIC filter and the read enable signal of the asynchronous FIFO module are kept synchronous without generating phase deviation; and the delay of the second counting sequence can ensure that it is aligned with the data of the subsequent CIC filter.

[0010] Furthermore, the third register sets the read enable signal of the asynchronous FIFO module to a high level at each zero return in the second counting sequence and when the delay enable signal is at a high level, and sets it to a low level in other cases, and its frequency value is the quotient of the working clock and the first frequency division parameter. The read enable signal of the asynchronous FIFO module is generated to ensure that data interaction processing is correctly performed between two different clock domains, the clock for writing data and the clock for reading data.

[0011] Furthermore, when the value of the delay sequence is the difference between the preset value and 1, the AND gate outputs a first AND operation result, and enables the enable data selector to select the audio digital-to-analog conversion circuit enable signal as the work enable; when the value of the delay sequence is not the difference between the preset value and 1, the AND gate outputs a second AND operation result, and enables the enable data selector to select the preset level signal as the work enable. The audio digital-to-analog conversion circuit enable signal is set to be used as the work enable only when the value of the delay sequence is the difference between the preset value and 1. When the audio digital-to-analog conversion circuit enable signal is turned off, the effect of delaying the turning off of the enable signal can be produced. During the delay period, the clock frequency division module can normally output the data processing enable signal of the CIC filter and the read enable signal of the asynchronous FIFO module.

[0012] A digital-to-analog conversion circuit with controllable audio playback and stop, the circuit includes the clock frequency division module, and the circuit also includes: a read-write control module, connected to the clock frequency division module, used to receive an APB bus signal, output a write enable signal to an asynchronous FIFO module, and output an audio digital-to-analog conversion circuit enable signal and a first frequency division parameter to the clock frequency division module; an asynchronous FIFO module, respectively connected to the read-write control module and the clock frequency division module, used to perform data interaction processing between two different clock domains, a clock for writing data and a clock for reading data; a CIC filter, respectively connected to the clock frequency division module and the asynchronous FIFO module The block is connected to read data from the asynchronous FIFO module and filter it according to the read enable signal of the phase-synchronized asynchronous FIFO module and the data processing enable signal of the CIC filter; wherein, when the read-write control module turns off the audio digital-to-analog conversion circuit enable signal, if the value of the delay sequence is not the difference between the preset value and 1, the preset level signal is used as a work enable to enable the circuit to work normally; if the value of the delay sequence is the difference between the preset value and 1, the audio digital-to-analog conversion circuit enable signal is used as a work enable to suspend the circuit; wherein, the preset level signal can enable the circuit to work normally.

[0013] Compared with the prior art, the present technical solution adopts a new audio DAC architecture, optimizes a large number of multiplication and addition operations, combinational logic and registers in the traditional architecture, and greatly reduces the hardware area and design complexity; at the same time, it solves the limitation of strict requirements on the working clock frequency of the audio DAC circuit, and can support audio with different sampling rates, which is more flexible in application and design; in addition, the present technical solution also has the function of delaying the shutdown of the working enable, so that when the circuit is closed and reopened, the CIC filter can be correctly interpolated to avoid the phenomenon of popping sound. If no delay is performed, the circuit cannot normally control the pause and play of the audio.

[0014] Furthermore, the circuit also includes a data transmission module and a digital-to-analog conversion module, wherein the data transmission module is used to transmit data to the asynchronous FIFO module, and the digital-to-analog conversion module is used to receive the data filtered by the CIC filter and convert it into an analog signal.

[0015] Furthermore, the data transmission module includes a CPU controller, a DMA controller and a data selector; wherein the CPU controller and the DMA controller are respectively connected to the data selector, and the data selector selects the data of the CPU controller or the DMA controller to the asynchronous FIFO module through the data selection signal provided by the read-write control module.

[0016] Furthermore, the data selection signal provided by the read-write control module is an interrupt signal or a request signal of the audio digital-to-analog conversion circuit; wherein, when the selection signal is an interrupt signal, the data of the CPU controller is selected to be given to the asynchronous FIFO module, and when the selection signal is a request signal, the data of the DMA controller is selected to be given to the asynchronous FIFO module.

[0017] A method for digital-to-analog conversion with controllable audio playback and pause, the method is implemented by the digital-to-analog conversion circuit with controllable audio playback and pause, the method comprising: before the circuit turns off the audio digital-to-analog conversion circuit enable signal, real-time judgment is performed on the delay sequence, if the value of the delay sequence is not the difference between the preset value and 1, the preset level signal is used as a work enable to enable the circuit to work normally, if the value of the delay sequence is the difference between the preset value and 1, the audio digital-to-analog conversion circuit enable signal is turned off and used as a work enable to enable the circuit to suspend operation; wherein the preset level signal can enable the circuit to work normally.

[0018] Compared with the prior art, the technical solution has the function of delaying the shutdown operation to enable the CIC filter to correctly interpolate when the circuit is closed and reopened to avoid popping. If no delay is performed, the circuit cannot normally control the pause and play of the audio.

[0019] Further, when the value of the delay sequence is the difference between the preset value and 1, the AND gate outputs the first AND operation result, so that the enable data selector selects the audio digital-to-analog conversion circuit enable signal as the work enable; when the value of the delay sequence is not the difference between the preset value and 1, the AND gate outputs the second AND operation result, so that the enable data selector selects the preset level signal as the work enable. It is set that the audio digital-to-analog conversion circuit enable signal is used as the work enable only when the value of the delay sequence is the difference between the preset value and 1, and the effect of delaying the closure of the enable signal can be produced when the audio digital-to-analog conversion circuit enable signal is turned off. During the delay period, the clock frequency division module can normally output the data processing enable signal of the CIC filter and the read enable signal of the asynchronous FIFO module, so that the CIC filter can complete the current interpolation. In this way, when the audio digital-to-analog conversion circuit enable signal is reopened, the CIC filter will not generate an interpolation exception, thereby causing data calculation overflow errors and popping sound phenomena. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 This is a typical audio DAC circuit diagram.

[0021] Figure 2 A schematic diagram of a clock frequency division module according to an embodiment of the present invention.

[0022] Figure 3A schematic diagram of a digital-to-analog conversion circuit with controllable audio playback and pause according to an embodiment of the present invention. DETAILED DESCRIPTION

[0023] The technical scheme in the embodiment of the present invention will be described in detail below in conjunction with the accompanying drawings in the embodiment of the present invention. It should be understood that the specific embodiments described below are only used to explain the present invention and are not used to limit the present invention. It should be noted by those skilled in the art that the modules, submodules, controllers, systems and other circuits disclosed in the present invention can be designed using hardware description languages ​​such as VHDL or Verilog, if there is no contradiction, and mapped to form a netlist information that can be produced into an integrated circuit.

[0024] In the following description, specific details are given to provide a thorough understanding of the embodiments. However, one of ordinary skill in the art will appreciate that the embodiments may be practiced without these specific details. For example, circuits may be shown in block diagrams so as not to obscure the embodiments in unnecessary detail. In other cases, well-known circuits, structures, and techniques may not be shown in detail in order not to obscure the embodiments.

[0025] like Figure 1 The typical audio DAC circuit shown in the figure is not only large in area and power consumption, but also only supports sampling rates based on three base frequencies (32k, 44.1k, and 48k), and cannot support other sampling rates well. Due to this specific sampling rate, the working clock of this typical design must be a clock source that can separate these three base frequencies or their power of 2 frequency values, such as the typical values ​​of 24.576M (for separating 48K and 32K) and 22.5792MHz (for separating 44.1K) clock sources. The requirements of the typical audio DAC circuit on the clock source are too strict and the compatibility is not good. In addition, this audio DAC circuit cannot achieve broadcast pause, because if the DAC enable is turned off and on directly, it will appear that during the period from the DAC enable is turned off to the open, due to the lack of judgment means, it is impossible to know how many data the CIC filter (integral-cascade-comb filter) interpolated, which leads to re-interpolation after opening, resulting in data calculation overflow error and popping sound phenomenon.

[0026] Therefore, the embodiment of the present invention proposes a clock frequency division module, such as Figure 2 As shown, the module includes:

[0027] The divider is used to receive the first frequency division parameter and perform a division operation to obtain the second frequency division parameter. The dividend is a preset value, specifically referring to the oversampling rate of the post-stage CIC filter. Preferably, the oversampling rate is set to 8.

[0028] The first counter is connected to the divider and is used to count the working clock according to the second frequency division parameter to obtain a first counting sequence. The first counter starts counting from 0, and increases by 1 at each rising edge of the working clock, and returns to zero and counts again whenever the counted number reaches the value of the second frequency division parameter.

[0029] The first register is connected to the first counter and is used to divide the working clock according to the first counting sequence to obtain the data processing enable signal of the CIC filter and its frequency value. At each previous value of zero in the first counting sequence, the data processing enable signal of the CIC filter is set to a high level 1, and in other cases it is set to a low level 0, and its frequency value is the quotient of the working clock and the second frequency division parameter. It should be noted that when the reset signal is 0, or the audio digital-to-analog conversion circuit enable signal is 0, the data processing enable signal of the CIC filter is also 0. The reset signal is 0, indicating that the audio digital-to-analog conversion circuit is reset, and the audio digital-to-analog conversion circuit enable signal is 0, indicating that the audio digital-to-analog conversion circuit is not in working state. The reset signal and the audio digital-to-analog conversion circuit enable signal are transmitted to the first counter, the first register, the second counter and the third register as the outputs of the front-stage read-write control module.

[0030] The second counter is connected to the first register and is used to count the data processing enable signal of the CIC filter according to the preset value to obtain a second counting sequence. The second counter starts counting from 0, adds 1 at the rising edge of the working clock, and returns to zero and counts again whenever the count number reaches the preset value.

[0031] The second register is connected to the first register and is used to delay the data processing enable signal of the CIC filter to obtain a delayed enable signal. The delay time of the data processing enable signal of the CIC filter by the second register is a preset number of working clock cycles. Preferably, the data processing enable signal of the CIC filter is delayed by one working clock cycle, so that the read enable signal of the asynchronous FIFO module output by the third register can be aligned with the rising edge of the data processing enable signal of the CIC filter.

[0032] The third register is connected to the second counter and the second register respectively, and is used to divide the working clock according to the second counting sequence and the delay enable signal to obtain the read enable signal of the asynchronous FIFO module and its frequency value. At each zero return in the second counting sequence, and when the delay enable signal is at a high level, the read enable signal of the asynchronous FIFO module is set to a high level 1, and in other cases it is set to a low level 0, and its frequency value is the quotient of the working clock and the first frequency division parameter. Similarly, when the reset signal is 0, or the audio digital-to-analog conversion circuit enable signal is 0, the read enable signal of the asynchronous FIFO module is also 0. It should be noted that the frequency value of the read enable signal of the asynchronous FIFO module is equal to the sampling rate of the audio data, so that the asynchronous FIFO module can accurately read the audio data under two different clock domains.

[0033] It should be noted that the design of the clock frequency division module also makes the data processing enable signal of the CIC filter and the read enable signal of the asynchronous FIFO module synchronized without phase deviation, otherwise the CIC filter will fail to collect data from the asynchronous FIFO module. The design of the clock frequency division module ensures the synchronization of the two signals while supporting data processing under a small range of sampling rate errors.

[0034] The fourth register is connected to the second counter and is used to delay the second counting sequence to obtain a delayed sequence. The delay time of the second counting sequence by the fourth register is a preset number of working clock cycles. Preferably, the second counting sequence is delayed by one working clock cycle, so that the second counting sequence can be aligned with the data of the subsequent CIC filter.

[0035] The AND gate is connected to the fourth register and is used to perform an AND operation on the delay sequence and the audio digital-to-analog conversion circuit enable signal. When the value of the delay sequence is the difference between the preset value and 1 (as can be seen from the above, the preset value is preferably 8), that is, when the delay sequence takes a value of 7, the AND gate outputs the first AND operation result 0; otherwise, when the delay sequence takes a value of 0 to 6, the AND gate outputs the second AND operation result 1. It should be noted that before the front-stage read-write control module turns off the audio digital-to-analog conversion circuit enable signal (that is, before pausing the audio), the value of the delay sequence will be detected first. Only when it is detected that the delay sequence takes a value of 7, the audio digital-to-analog conversion circuit enable signal will be turned off, so that the AND gate outputs the first AND operation result 0.

[0036] The enable data selector is connected to the AND gate, and selects the audio digital-to-analog conversion circuit enable signal or the preset level signal as the work enable according to the AND operation result. When the AND gate outputs the first AND operation result 0, the enable data selector selects the audio digital-to-analog conversion circuit enable signal as the work enable. If the audio digital-to-analog conversion circuit enable signal is 0 at this time (low level means off), then the work enable is also 0, and the clock frequency division module stops outputting the read enable signal of the asynchronous FIFO module and the data processing enable signal of the CIC filter, and the audio is paused. When the AND gate outputs the second AND operation result 1, the enable data selector selects the preset level signal as the work enable, so that the clock frequency division module works normally.

[0037] Compared with the prior art, the frequency division of the working clock in the embodiment of the present invention can correctly generate the sampling rate of the original audio data, thereby supporting audio data sources with various sampling rates; the third register divides the working clock according to the second counting sequence and the delay enable signal, so that the data processing enable signal of the CIC filter and the read enable signal of the asynchronous FIFO module can be kept synchronized without generating phase deviation, thereby ensuring the accuracy of data reading; in addition, it is set that the audio digital-to-analog conversion circuit enable signal is used as the working enable only when the value of the delay sequence is the difference between the preset value and 1, and the audio digital-to-analog conversion circuit enable signal can be turned off to produce the effect of delaying the turning off of the enable signal when the audio digital-to-analog conversion circuit enable signal is turned off. During the delay period, the clock frequency division module can normally output the data processing enable signal of the CIC filter and the read enable signal of the asynchronous FIFO module.

[0038] like Figure 3 As shown, an embodiment of the present invention provides a digital-to-analog conversion circuit with controllable audio playback and pause, the circuit comprising: Figure 2 A clock frequency division module as shown further includes:

[0039] The read-write control module is connected to the clock frequency division module and is used to receive the APB bus signal. The APB bus is used to connect peripheral devices, and then output a write enable signal to the asynchronous FIFO module, and output an audio digital-to-analog conversion circuit enable signal and a first frequency division parameter to the clock frequency division module. The first frequency division parameter is configured by the peripheral device. After obtaining the working clock of the audio digital-to-analog conversion circuit and the sampling rate of the audio data, the peripheral device obtains the first frequency division parameter by quotient. The working clock and the sampling rate of the audio data are both known parameters. The read-write control module is a module built by register read-write modules with different addresses, and the register value of each address is configured by operating the APB bus signal. APB bus is one of the AMBA bus protocols and is a commonly used bus protocol. Its usage is as follows: APB bus has several signals such as PCLK / PSEL / PENABLE / PWRITE / PADDR / PRDATA / PWDATA / PRESET. When PENABLE, PSEL, and PWRITE are all 1 at the same time, when the rising edge of PCLK arrives, the PWDATA value is written to PADDR, that is, the WDATA value is written to the register read-write module with the address ADDR; on the contrary, when PENABLE, PSEL, and PWRITE are all 0 at the same time, when the rising edge of PCLK arrives, the PRDATA value in PADDR is read, that is, the value in the register read-write module with the address ADDR is read out. The data input and output in the read-write control module are all realized in this way.

[0040] The asynchronous FIFO module is connected to the read / write control module and the clock frequency division module respectively, and is used for data interaction processing between two different clock domains, the clock for writing data and the clock for reading data. This module is a common module and will not be described in detail.

[0041] The CIC filter is connected to the clock frequency division module and the asynchronous FIFO module respectively, and is used to read out data from the asynchronous FIFO module and filter it according to the read enable signal of the phase-synchronized asynchronous FIFO module and the data processing enable signal of the CIC filter. The CIC filter is also called the integral-cascade-comb filter, which is the best one among FIR filters, and uses the integral and comb filter cascade method. In the interpolation CIC filter, the input signal passes through the comb filter, oversampling, and the same integral link as the number of combs in sequence. The oversampling rate can be 8, 16, 32, 64, etc. Preferably, the oversampling rate is set to 8. The CIC filter interpolates and integrates the data read out from the asynchronous FIFO module, so the final output data is smoother in the time domain waveform, and the performance such as signal-to-noise ratio and total harmonic distortion are improved.

[0042] Among them, when the read-write control module turns off the audio digital-to-analog conversion circuit enable signal, if the value of the delay sequence is not the difference between the preset value and 1, the preset level signal is used as the work enable to enable the circuit to work normally; if the value of the delay sequence is the difference between the preset value and 1, the audio digital-to-analog conversion circuit enable signal is used as the work enable to enable the circuit to suspend operation; wherein, the preset level signal can enable the circuit to work normally.

[0043] Reference Figure 3 The digital-to-analog conversion circuit with controllable audio playback and pause also includes a data transmission module and a digital-to-analog conversion module.

[0044] Wherein, the data transmission module is used to transmit data to the asynchronous FIFO module, including a CPU controller, a DMA controller and a data selector. The CPU controller and the DMA controller are respectively connected to the data selector, and the data selector selects the data of the CPU controller or the DMA controller to the asynchronous FIFO module through the data selection signal provided by the read-write control module, that is, the asynchronous FIFO module has two data sources. The data selection signal provided by the read-write control module is the interrupt signal or request signal of the circuit. When the selection signal is an interrupt signal, the data of the CPU controller is selected to the asynchronous FIFO module. When the selection signal is a request signal, the data of the DMA controller is selected to the asynchronous FIFO module. The digital-to-analog conversion module is used to receive the data filtered by the CIC filter and convert it into an analog signal. The digital-to-analog conversion circuit with controllable audio playback and pause described in the embodiment of the present invention can play the source audio data almost without loss, and supports DAC playback pause and restart.

[0045] Compared with the prior art, the embodiment of the present invention adopts a new audio DAC architecture, optimizes a large number of multiplication and addition operations, combinational logic and registers in the traditional architecture, and greatly reduces the hardware area and design complexity; at the same time, it solves the limitation of strict requirements on the working clock frequency of the audio DAC circuit, and can support audio with different sampling rates, which is more flexible in application and design; in addition, the embodiment of the present invention also has the function of delaying the shutdown of the working enable, so that when the circuit is closed and reopened, the CIC filter can correctly interpolate to avoid the occurrence of popping sound. If no delay is performed, the circuit cannot normally control the pause and play of the audio.

[0046] An embodiment of the present invention provides a digital-to-analog conversion method with controllable audio playback and pause, the method comprising:

[0047] Before the circuit turns off the audio digital-to-analog conversion circuit enable signal, the delay sequence is judged in real time. If the value of the delay sequence is not the difference between the preset value and 1, the preset level signal is used as a work enable to enable the circuit to work normally. If the value of the delay sequence is the difference between the preset value and 1, the audio digital-to-analog conversion circuit enable signal is turned off and used as a work enable to suspend the circuit from working. The preset level signal can enable the circuit to work normally.

[0048] It should be noted that the circuit pauses the audio by turning off the audio digital-to-analog conversion circuit enable signal, and enables the audio to continue playing by turning on the audio digital-to-analog conversion circuit enable signal.

[0049] The audio play / pause controllable digital-to-analog conversion circuit of the present invention is further described below with reference to specific examples.

[0050] Assume that the parameters of the original audio data received by the asynchronous FIFO module from the CPU controller or the DMA controller are Fin=1KHz, Fs=11.025K, ENOB=12bit, where Fin represents the frequency of the audio data, Fs represents the sampling rate of the audio data, and ENOB represents the effective bit width of the signal.

[0051] First, the peripheral device calculates the first frequency division parameter DAC_D2A_CLK_SCAL according to the working clock DAC_CLK and the audio data sampling rate Fs. The working clock DAC_CLK is an external clock source, and its frequency value is not limited to the typical values ​​of 24.576M and 22.5792MHz. It should be emphasized that the input clock source of the clock frequency division module can be changed, and the design of the module does not rely on a specific clock frequency to work, that is, no matter what kind of clock the external clock source is, the clock frequency division module can work normally, and the entire audio digital-to-analog conversion circuit can also work normally. Preferably, the working clock selects a clock source with a frequency greater than 20MHz. Preferably, in this embodiment, the working clock selects a clock source of 48MHz. The advantage of this more common clock frequency value is that it can share a clock with other modules in the SOC project, thereby saving the resource occupation of the clock module and not affecting the performance of the audio digital-to-analog conversion circuit. Therefore, the first frequency division parameter DAC_D2A_CLK_SCAL=DAC_CLK / Fs=48M / 11.025K=4353. After receiving the first frequency division parameter DAC_D2A_CLK_SCAL, the divider calculates the second frequency division parameter CIC_CLK_SCAL=DAC_D2A_CLK_SCAL / OSR=4353 / 8=544, where OSR represents the oversampling rate of the CIC filter.

[0052] Subsequently, the first counter counts the working clock DAC_CLK, and counts each rising edge, from 0 to 543 and then starts from 0, and so on to obtain the first counting sequence CIC_CLK_SCAL_CNT. Whenever CIC_CLK_SCAL_CNT counts to 543, the data processing enable signal CIC_DATA_EN of the CIC filter is set to a high level 1, and the data processing enable signal CIC_DATA_EN of the CIC filter is obtained as DAC_CLK / CIC_CLK_SCAL=48M / 544=88.2K.

[0053] Then, the data processing enable signal CIC_DATA_EN of the CIC filter is counted, and the second counter counts from 0 to 7 and then starts from 0, and so on to obtain the second counting sequence CNT_CIC_EN. At the same time, the second register delays the data processing enable signal CIC_DATA_EN of the CIC filter by one working clock DAC_CLK cycle to obtain the delayed enable signal CIC_DATA_EN_1T. Whenever CNT_CIC_EN=0 and CIC_DATA_EN_1T=1, the read enable signal AFIFO_REN of the asynchronous FIFO module is set to high level 1, and the read enable signal AFIFO_REN of the asynchronous FIFO module is obtained=DAC_CLK / CIC_CLK_SCAL / 8=48M / 544 / 8=11.025K. It can be seen that the read enable signal AFIFO_REN of the asynchronous FIFO module is consistent with the audio data sampling rate Fs, and the clock frequency division module restores Fs. The clock frequency division module described in this embodiment is applicable to various audio data sources and is not picky about the audio sampling rate. Preferably, it can well support audio sampling rates in the continuous range of 11.025K-1M.

[0054] It should be emphasized that counting and delaying the data processing enable signal CIC_DATA_EN can keep the data processing enable signal CIC_DATA_EN of the CIC filter and the read enable signal AFIFO_REN of the asynchronous FIFO module synchronized without phase deviation. Otherwise, the CIC filter will fail to collect data from the asynchronous FIFO module.

[0055] Finally, the CIC filter uses CIC_DATA_EN and AFIFO_REN to interpolate and integrate the data of the asynchronous FIFO module to improve the quality of the audio data, making the audio played through the digital-to-analog conversion module have higher fidelity.

[0056] During the above audio playback process, the read-write control module always outputs the DAC enable signal (i.e., the audio digital-to-analog conversion circuit enable signal), see Figure 2At this time, no matter which signal is selected by the data selector, the audio can be played normally. If the work enable is turned off directly when the audio playback needs to be paused, when the work enable is turned on again, the CIC filter cannot determine how many data have been interpolated before the pause, and re-interpolates 8 data (the number is determined by the oversampling rate). When the interpolation is greater than 8, the data calculation overflows and an error occurs, resulting in popping sound.

[0057] Therefore, it is necessary to delay turning off the working enable, and only after the CIC filter interpolation reaches 8, can the popping sound phenomenon be avoided by turning off the working enable. After the second counter obtains the second counting sequence CNT_CIC_EN, it is transmitted to the fourth register for a delay of one working clock DAC_CLK cycle to obtain the delay sequence CNT_CIC_EN_1T. The delay operation can ensure that CNT_CIC_EN_1T is aligned with the data of the subsequent CIC filter. As can be seen from the above, the values ​​of the delay sequence CNT_CIC_EN_1T include 0 to 7. Whenever the delay sequence CNT_CIC_EN_1T takes the value of 7, it means that the CIC filter interpolation has reached 8. Therefore, when the audio needs to be paused, the read-write control module will stop outputting the DAC enable signal only when it detects that the delay sequence CNT_CIC_EN_1T takes the value of 7. At this time, the AND operation result of the AND gate is 0. When 0 is used as the selection signal of the enable data selector, the DAC enable signal is selected as the working enable. The DAC enable signal is turned off, so the clock division module stops outputting the data processing enable signal CIC_DATA_EN of the CIC filter and the read enable signal of the asynchronous FIFO module, thereby pausing the audio playback.

[0058] On the other hand, when the delay sequence CNT_CIC_EN_1T takes a value of 0 to 6, it means that the CIC filter interpolation has not reached 8, and the work enable needs to be delayed until the delay sequence CNT_CIC_EN_1T takes a value of 7. At this time, the AND operation result of the AND gate is 1. When 1 is used as the selection signal of the enable data selector, the preset level signal is selected as the work enable, which continues until the number of CIC filter interpolations reaches 8. It should be noted that the preset level signal is a high level 1, which can make the clock frequency division module work normally. Then, when the delay sequence CNT_CIC_EN_1T takes a value of 7, the read-write control module stops outputting the DAC enable signal, the AND gate outputs the AND operation result 0, and selects the DAC enable signal as the work enable to pause the audio. It is not difficult to see that when the audio needs to be played again, it is only necessary to re-output the DAC enable signal. Since the number of CIC filter interpolations reaches 8, the number of interpolations will not overflow after restarting, avoiding abnormal phenomena such as popping sounds, and realizing the normal pause and restart of DAC broadcasting.

[0059] Obviously, the above-mentioned embodiments are only some embodiments of the present invention, rather than all embodiments, and the technical solutions between the various embodiments can be combined with each other. In addition, if the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inside", "outside" and the like appear in the embodiments, the orientation or position relationship indicated is based on the orientation or position relationship shown in the accompanying drawings, which is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation or be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention. If the terms "first", "second", "third" and the like appear in the embodiments, it is to facilitate the distinction of related features, and cannot be understood as indicating or implying their relative importance, order or number of technical features.

[0060] In addition, in the description of the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, and it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0061] Those skilled in the art will appreciate that all or part of the steps of implementing the above-mentioned method embodiments can be completed by hardware related to program instructions. These programs can be stored in a computer-readable storage medium (such as ROM, RAM, magnetic disk or optical disk, etc., which can store program codes). When the program is executed, the steps of the above-mentioned method embodiments are executed.

[0062] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A clock frequency division module, characterized in that: The modules include: A divider, used for receiving the first frequency division parameter and performing a division operation to obtain a second frequency division parameter; wherein the dividend is a preset value; A first counter, connected to the divider, for counting the working clock according to the second frequency division parameter to obtain a first counting sequence; A first register is connected to the first counter and is used to divide the working clock according to the first counting sequence to obtain a data processing enable signal of the CIC filter and its frequency value; A second counter, connected to the first register, for counting the data processing enable signal of the CIC filter according to the preset value to obtain a second counting sequence; A second register, connected to the first register, for delaying the data processing enable signal of the CIC filter to obtain a delayed enable signal; A third register is connected to the second counter and the second register respectively, and is used to divide the working clock according to the second counting sequence and the delay enable signal to obtain the read enable signal of the asynchronous FIFO module and its frequency value; a fourth register connected to the second counter and used for delaying the second counting sequence to obtain a delay sequence; An AND gate connected to the fourth register and used for performing an AND operation on the delay sequence and the audio digital-to-analog conversion circuit enable signal; An enable data selector is connected to the AND gate and selects an audio digital-to-analog conversion circuit enable signal or a preset level signal as a work enable according to an AND operation result; Wherein, when the value of the delay sequence is the difference between the preset value and 1, the enable data selector selects the audio digital-to-analog conversion circuit enable signal as the work enable, otherwise selects the preset level signal as the work enable; Wherein, the preset level signal can make the module work normally; The data processing enable signal of the CIC filter and the read enable signal of the asynchronous FIFO module are phase synchronized.

2. A clock frequency division module according to claim 1, characterized in that: The first counter counts the rising edges of the working clock, and resets to zero every time the counted number reaches the value of the second frequency division parameter.

3. A clock frequency division module according to claim 2, characterized in that: The first register sets the data processing enable signal of the CIC filter to a high level at each value before zero in the first counting sequence, and sets it to a low level in other cases, and its frequency value is the quotient of the working clock and the second frequency division parameter.

4. A clock frequency division module according to claim 3, characterized in that: The second counter counts the rising edges of the data processing enable signal of the CIC filter, and resets to zero every time the counted number reaches a preset value.

5. A clock frequency division module according to claim 3, characterized in that: The delay time of the second register for the data processing enable signal of the CIC filter and the delay time of the fourth register for the second counting sequence are both a preset number of working clock cycles.

6. A clock frequency division module according to claim 5, characterized in that: The third register sets the read enable signal of the asynchronous FIFO module to a high level at each zero return in the second counting sequence and when the delay enable signal is at a high level, and sets it to a low level in other cases, and its frequency value is the quotient of the working clock and the first frequency division parameter.

7. A clock frequency division module according to claim 5, characterized in that: When the value of the delay sequence is the difference between the preset value and 1, the AND gate outputs a first AND operation result, and enables the enable data selector to select the audio digital-to-analog conversion circuit enable signal as the working enable; when the value of the delay sequence is not the difference between the preset value and 1, the AND gate outputs a second AND operation result, and enables the enable data selector to select the preset level signal as the working enable.

8. A digital-to-analog conversion circuit with controllable audio playback and pause, characterized in that: The circuit comprises the clock frequency division module according to any one of claims 1 to 7, and the circuit further comprises: A read / write control module connected to the clock frequency division module, configured to receive an APB bus signal, output a write enable signal to the asynchronous FIFO module, and output an audio digital-to-analog conversion circuit enable signal and a first frequency division parameter to the clock frequency division module; The asynchronous FIFO module is connected to the read / write control module and the clock frequency division module respectively, and is used for performing data interaction processing between two different clock domains, the clock for writing data and the clock for reading data; A CIC filter is connected to the clock frequency division module and the asynchronous FIFO module respectively, and is used to read data from the asynchronous FIFO module and filter it according to a read enable signal of the phase-synchronized asynchronous FIFO module and a data processing enable signal of the CIC filter; Wherein, when the read-write control module turns off the audio digital-to-analog conversion circuit enable signal, if the value of the delay sequence is not the difference between the preset value and 1, the preset level signal is used as a work enable to enable the circuit to work normally; if the value of the delay sequence is the difference between the preset value and 1, the audio digital-to-analog conversion circuit enable signal is used as a work enable to enable the circuit to suspend operation; The preset level signal can make the circuit work normally.

9. The digital-to-analog conversion circuit with controllable audio playback and stop according to claim 8, characterized in that: The circuit also includes a data transmission module and a digital-to-analog conversion module. The data transmission module is used to transmit data to the asynchronous FIFO module, and the digital-to-analog conversion module is used to receive the data filtered by the CIC filter and convert it into an analog signal.

10. The digital-to-analog conversion circuit with controllable audio playback and stop according to claim 9, characterized in that: The data transmission module includes a CPU controller, a DMA controller and a data selector; wherein the CPU controller and the DMA controller are respectively connected to the data selector, and the data selector selects the data of the CPU controller or the DMA controller to the asynchronous FIFO module through the data selection signal provided by the read-write control module.

11. The digital-to-analog conversion circuit with controllable audio playback and stop according to claim 10, characterized in that: The data selection signal provided by the read-write control module is an interrupt signal or a request signal of the audio digital-to-analog conversion circuit; wherein, when the selection signal is an interrupt signal, the data of the CPU controller is selected to be given to the asynchronous FIFO module, and when the selection signal is a request signal, the data of the DMA controller is selected to be given to the asynchronous FIFO module.

12. A method for digital-to-analog conversion with controllable audio playback and pause, characterized in that: The method is implemented by a digital-to-analog conversion circuit with controllable audio playback and pause as described in any one of claims 8 to 11, and the method comprises: Before the circuit turns off the audio digital-to-analog conversion circuit enable signal, the delay sequence is judged in real time. If the value of the delay sequence is not the difference between the preset value and 1, the preset level signal is used as a work enable to enable the circuit to work normally. If the value of the delay sequence is the difference between the preset value and 1, the audio digital-to-analog conversion circuit enable signal is turned off and used as a work enable to suspend the circuit from working. The preset level signal can enable the circuit to work normally.

13. The method for digital-to-analog conversion of audio with controllable play and stop according to claim 12, characterized in that: When the value of the delay sequence is the difference between the preset value and 1, the AND gate outputs a first AND operation result, so that the enable data selector selects the audio digital-to-analog conversion circuit enable signal as the working enable; when the value of the delay sequence is not the difference between the preset value and 1, the AND gate outputs a second AND operation result, so that the enable data selector selects the preset level signal as the working enable.

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