Display device driving control circuit assembly and display device

Abstract

The present application provides a display device driving control circuit component and a display device. The present application makes the frequency of a first timing control clock of a first timing controller and the frequency of a second timing control clock of a second timing controller different, so that the radiation intensity generated by the first timing controller and the second timing controller during operation is greatly reduced, thereby greatly reducing the intensity of electromagnetic compatibility, thereby solving the electromagnetic compatibility problem caused by the high-speed clock signals of the same clock frequency of the two timing controllers of the display device in the prior art.

Description

Technical Field

[0001] The present application relates to the technical field of display panels, and in particular to a display device driving control circuit component and a display device. Background Art

[0002] With the development of high-resolution and high-refresh rate liquid crystal display (LCD), a higher-speed transmission protocol is needed, and the high-speed transmission signal needs to be matched with a high-speed clock signal, which will lead to serious electromagnetic interference (EMI) problems. The display device of the prior art includes a display panel, twelve driver chips connected to the display panel (such as chip-on-film (COF) driver chips), and two timing controllers (TCON) connected to the twelve driver chips respectively. When the display panel is operating, the two timing controllers transmit signals to the driver chip, and the driver chip decodes to obtain the clock signal. However, the high-speed clock signal of the two timing controllers and the twelve driver chips have the same clock, resulting in energy superposition and the problem of excessively high clock frequency EMI.

[0003] Therefore, there is an urgent need to solve the EMC problem of the above display panel caused by the high-speed timing controller and the driving chip of the same frequency. Summary of the invention

[0004] An embodiment of the present application provides a display device driving control circuit component and a display device to solve the problem that two timing controllers of the display device in the prior art have high-speed clock signals with the same clock frequency and that multiple driving chips have the same clock, resulting in energy superposition and excessive electromagnetic interference (EMI) at the clock frequency.

[0005] The embodiment of the present application provides a display device driving control circuit assembly, characterized in that the display device driving control circuit assembly includes:

[0006] A timing control module, comprising a first timing controller and a second timing controller, wherein the first timing controller is used to transmit a first timing control signal according to a first timing control clock, and the second timing controller is used to transmit a second timing control signal according to a second timing control clock, and the frequency of the second timing control clock is different from the frequency of the first timing control clock;

[0007] A first drive control module, comprising a plurality of first drive control chips electrically connected to the first timing controller, wherein each of the first drive control chips is used to receive the first timing control signal and generate a first drive signal according to the first timing control signal, so as to further transmit the first drive signal to the display panel, wherein the first drive signal is embedded with a first drive control clock; and

[0008] A second drive control module includes multiple second drive control chips electrically connected to the second timing controller, wherein each of the second drive control chips is used to receive the second timing control signal and generate a second drive signal according to the second timing control signal, so as to further transmit the second drive signal to the display panel, wherein the second drive signal is embedded with a second drive control clock, and the frequency of the second drive control clock is different from the frequency of the first drive control clock.

[0009] In some embodiments of the present application, the first timing controller includes:

[0010] a spread spectrum crystal oscillator frequency multiplication unit, configured to provide the first timing control clock; and

[0011] a point-to-point transmission unit, configured to embed the first timing control clock into the first timing control signal and transmit the first timing control signal;

[0012] The constituent units of the second timing controller are the same as those of the first timing controller, and the frequency range of the first timing control clock does not overlap with the frequency range of the second timing control clock.

[0013] In some embodiments of the present application, the spread spectrum crystal oscillator frequency multiplication unit of the first timing controller is used to provide the first timing control clock according to the first center frequency f1 and the first spread spectrum ratio value r1, and the frequency range of the first timing control clock is f1(1-r1) to f1(1+r1); the spread spectrum crystal oscillator frequency multiplication unit of the second timing controller is used to provide the second timing control clock according to the second center frequency f2 and the second spread spectrum ratio value r2, and the frequency range of the second timing control clock is f2(1-r2) to f2(1+r2).

[0014] In some embodiments of the present application, the first timing controller is a master timing controller, and the second timing controller is a slave timing controller, and the second center frequency f2 of the second timing control clock in the second timing controller is set by offsetting the first center frequency f1 of the first timing control clock in the first timing controller, and satisfies f1>f2, and f1(1-r1)>f2(1+r2).

[0015] In some embodiments of the present application, a frequency difference (f1-f2) / f1 between the second center frequency f2 of the second timing control clock and the first center frequency f1 of the first timing control clock is 2% to 10%.

[0016] In another aspect, an embodiment of the present application provides a display device, including:

[0017] A display panel including a plurality of pixel units; and

[0018] A display device driving control circuit assembly is connected to the display panel and includes:

[0019] A timing control module, comprising a first timing controller and a second timing controller, wherein the first timing controller is used to transmit a first timing control signal according to a first timing control clock, and the second timing controller is used to transmit a second timing control signal according to a second timing control clock, and the frequency of the second timing control clock is different from the frequency of the first timing control clock;

[0020] A first drive control module, comprising a plurality of first drive control chips electrically connected to the first timing controller, wherein each of the first drive control chips is used to receive the first timing control signal and generate a first drive signal according to the first timing control signal, so as to further transmit the first drive signal to the display panel, wherein the first drive signal is embedded with a first drive control clock; and

[0021] a second drive control module, comprising a plurality of second drive control chips electrically connected to the second timing controller, wherein each of the second drive control chips is used to receive the second timing control signal and generate a second drive signal according to the second timing control signal, so as to further transmit the second drive signal to the display panel, wherein the second drive signal is embedded with a second drive control clock, and the frequency of the second drive control clock is different from the frequency of the first drive control clock;

[0022] The first timing controller and the first driving control module are used to drive a part of the plurality of pixel units, and the second timing controller and the second driving control module are used to drive the rest of the plurality of pixel units.

[0023] In some embodiments of the present application, the first timing controller includes:

[0024] a spread spectrum crystal oscillator frequency multiplication unit, configured to provide the first timing control clock; and

[0025] a point-to-point transmission unit, configured to embed the timing control clock into the first timing control signal and transmit the first timing control signal;

[0026] The constituent units of the second timing controller are the same as those of the first timing controller, and the frequency range of the first timing control clock does not overlap with the frequency range of the second timing control clock.

[0027] In some embodiments of the present application, the spread spectrum crystal oscillator frequency multiplication unit of the first timing controller is used to provide the first timing control clock according to the first center frequency f1 and the first spread spectrum ratio value r1, and the frequency range of the first timing control clock is f1(1-r1) to f1(1+r1); the spread spectrum crystal oscillator frequency multiplication unit of the second timing controller is used to provide the second timing control clock according to the second center frequency f2 and the second spread spectrum ratio value r2, and the frequency range of the second timing control clock is f2(1-r2) to f2(1+r2).

[0028] In some embodiments of the present application, the first timing controller is a master timing controller, and the second timing controller is a slave timing controller, and the second center frequency f2 of the second timing control clock in the second timing controller is set by offsetting the first center frequency f1 of the first timing control clock in the first timing controller, and satisfies f1>f2, and f1(1-r1)>f2(1+r2).

[0029] In some embodiments of the present application, a frequency difference between the frequency of the second chip clock and the frequency of the first chip clock is 2% to 10%.

[0030] This application has at least the following advantages:

[0031] The display device driving control circuit component and the display device provided in the present application make the frequency of the first timing control clock of the first timing controller and the frequency of the second timing control clock of the second timing controller different, so that the radiation intensity is greatly reduced compared with the display device of the prior art, thereby greatly reducing the intensity of electromagnetic interference, thereby solving the problem of excessive electromagnetic interference caused by multiple driving chips of the display device of the prior art having the same clock frequency. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0033] Figure 1 is a plan view of a display device provided in an embodiment of the present application, wherein the display device comprises a display panel and a display device driving control circuit assembly;

[0034] Figure 2 1 is a schematic diagram of the architecture of a timing control module of a display device drive control circuit assembly provided in an embodiment of the present application;

[0035] Figure 3 is a schematic diagram of the architecture of a first drive control module and a second drive control module of a display device drive control circuit assembly provided in an embodiment of the present application; and

[0036] Figure 4 This is a frequency and radiation intensity chart of the first driving control chip and the second driving control chip of the display device driving control circuit assembly provided in an embodiment of the present application when they are in operation. DETAILED DESCRIPTION

[0037] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of this application.

[0038] Please refer to Figure 1 The embodiment of the present application provides a display device 1 driving control circuit component, including: a timing control module T, a first driving control module C1, and a second driving control module C2.

[0039] Please refer to Figure 2 The timing control module T includes a first timing controller T1 and a second timing controller T2, wherein the first timing controller T1 is used to transmit a first timing control signal according to a first timing control clock, and the second timing controller T2 is used to transmit a second timing control signal according to a second timing control clock, and the frequency of the second timing control clock is different from the frequency of the first timing control clock.

[0040] Specifically, the first timing controller includes: a spread spectrum crystal oscillator frequency multiplication unit SSC, used to provide the first timing control clock; and a point-to-point transmission unit P2P, used to embed the first timing control clock into the first timing control signal, and transmit the first timing control signal;

[0041] The constituent units of the second timing controller T2 are the same as the constituent units of the first timing controller T1 , and the frequency range of the first timing control clock does not overlap with the frequency range of the second timing control clock.

[0042] The spread spectrum crystal oscillator frequency multiplication unit SSC of the first timing controller T1 is used to provide the first timing control clock according to the first center frequency f1 and the first spread spectrum ratio value r1, and the frequency range of the first timing control clock is f1(1-r1) to f1(1+r1). The spread spectrum crystal oscillator frequency multiplication unit SSC of the second timing controller T2 is used to provide the second timing control clock according to the second center frequency f2 and the second spread spectrum ratio value r2, and the frequency range of the second timing control clock is f2(1-r2) to f2(1+r2).

[0043] For example, the first center frequency f1 of the first timing control clock is 640 MHz, and the second center frequency f2 of the second timing control clock is 610 MHz. The frequencies of the first timing control clock and the second timing control clock are obtained by modifying the clock register TR in the timing control module T, respectively.

[0044] The first timing controller T1 is a master timing controller, and the second timing controller T2 is a slave timing controller. The second center frequency f2 of the second timing control clock in the second timing controller T2 is set by offsetting the first center frequency f1 of the first timing control clock in the first timing controller T1, and meets the conditions of f1>f2, and f1(1-r1)>f2(1+r2).

[0045] For example, the first spread spectrum ratio value r1 is 1%, the second spread spectrum ratio value r2 is 1%, the first center frequency f1 of the first timing control clock is 640MHz, and the second center frequency f2 of the second timing control clock is 610MHz, which meets the condition that 640MHz>610MHz.

[0046] f1(1-r1)=640(1-0.01)=633.6, and f2(1+r2)=610(1+0.01)=616.1, so 633.6>616.1, which also satisfies the condition that f1(1-r1)>f2(1+r2).

[0047] The above design prevents the frequency range of the first timing control clock and the frequency range of the second timing control clock from overlapping after spectrum spreading, thereby preventing the superposition of signal strength and causing the problem of excessive electromagnetic interference.

[0048] A frequency difference (f1-f2) / f1 between the second center frequency f2 of the second timing control clock and the first center frequency f1 of the first timing control clock is 2% to 10%.

[0049] For example, the first center frequency f1 of the first timing control clock is 640 MHz, and the second center frequency f2 of the second timing control clock is 610 MHz, and the frequency difference (f1-f2) / f1 is (640-610) / 640=4.68%, which is within 2% to 10%.

[0050] Since a frequency difference that is too small will cause the frequency range to overlap and lead to excessive electromagnetic interference, and a frequency difference that is too large will cause abnormal screen splitting of the display, the frequency difference is preferably selected to be 2% to 10%.

[0051] Please refer to Figure 3 , the first drive control module C1 includes a plurality of first drive control chips C11-C16 electrically connected to the first timing controller T1, wherein each first drive control chip C11-C16 is used to receive different first timing control signals respectively, and generate a first drive signal based on the first timing control signal, so as to further transmit the first drive signal to the display panel 10, wherein the first drive signal is embedded with a first drive control clock. In detail, the first drive control chips C11-C16 can be chip-on-film (COF) drive chips.

[0052] The second drive control module C2 includes a plurality of second drive control chips C21-C26 electrically connected to the second timing controller T2, wherein each second drive control chip C21-C26 is used to receive the second timing control signal and generate a second drive signal according to the second timing control signal, so as to further transmit the second drive signal to the display panel 10, wherein the first drive signal is embedded with a first drive control clock, and the frequency of the second drive control clock is different from the frequency of the first drive control clock. For example, the first drive control clock is Figure 3 The marked frequency is 0.27MHz (taking a panel with a split-screen frame rate of 120Hz and a resolution of 4740*2250 as an example, in one frame, each data line has 2250 scan lines to complete scanning, so the signal frequency on each data line needs to be at least 2250*120=0.27MHz. Since each driver control chip provides data in the form of parallel signals, the operating frequency in the driver control chip does not need to be increased and can be maintained at 0.27MHz). The second driver control clock is Figure 3The frequency indicated in the figure is 0.26 MHz (taking a panel with a split-screen frame frequency of 114 Hz and a resolution of 4740*2250 as an example). In detail, the second driving control chips C21-C26 may be chip-on-film (COF) driving chips.

[0053] In some embodiments of the present application, the timing control module T includes a processor unit P, the processor unit P is electrically connected to the first timing controller T1 and the second timing controller T2, and is used to transmit a differential signal to the first timing controller T1 and the second timing controller T2. Each of the first timing controller T1 and the second timing controller T2 includes: a spread spectrum crystal oscillator frequency multiplication unit SSC, a differential signal receiving unit VB, an algorithm unit AL, a timing generation unit TG, and a point-to-point transmission unit P2P.

[0054] The spread spectrum crystal oscillator frequency multiplication unit SSC is used to provide the first timing control clock.

[0055] The differential signal receiving unit VB is used to receive the differential signal from the processor unit P.

[0056] The video capture unit VI is connected to the differential signal receiving unit VB and is used to obtain video data in the differential signal.

[0057] The algorithm unit AL is connected to the video capture unit VI and is used to process the video data.

[0058] The timing generation unit TG is connected to the algorithm unit AL and is used to generate a control timing, that is, to generate a panel row and column scanning timing.

[0059] The point-to-point transmission unit P2P is connected to the timing generation unit TG, and is used to embed the first timing control clock into the first timing control signal, and transmit the first timing control signal to a second timing control signal, wherein the first timing control clock is generated by a crystal oscillator multiplication unit in the first timing controller.

[0060] The constituent units of the second timing controller are the same as those of the first timing controller. The point-to-point transmission unit P2P of the first timing controller T1 provides first timing control signals of different frequencies to different first drive control chips C11-C16 according to the frequency range after the spread spectrum crystal oscillator frequency multiplication unit SSC is spread. The point-to-point transmission unit P2P of the second timing controller T2 provides second timing control signals of different frequencies to different second drive control chips C21-C26 according to the frequency range after the spread spectrum crystal oscillator frequency multiplication unit SSC is spread. For example, taking the first timing controller T1 as an example, the first center frequency f1 of the first timing control clock is 640MHz, which is provided in parallel to the six first drive control chips C11-C16, and the bus of each first drive control chip only needs to work at 640MHz / 6=106.67MHz. Generally, the point-to-point transmission unit P2P provides three signal lines of red, blue and green for each first drive control chip.

[0061] In some embodiments of the present application, the first driving control chip C11-C16 includes: a data recovery unit RC, a digital logic register transfer unit DRT, a buffer unit BU, and a data bus unit DB.

[0062] The data recovery unit RC is used to receive and process the first timing control signal sent by the point-to-point transmission unit P2P of the first timing controller T1, and convert the first timing control signal from a serial signal to a parallel signal to obtain an internal data signal. Specifically, a panel with a split screen frame rate of 120Hz and a resolution of 4740*2250 is taken as an example. There are a total of 3*4740 data lines for red, blue and green, which are evenly divided into 12 drive control chips (6 first drive control chips and 6 second drive control chips). Each drive control chip needs to provide 3*4740 / 12=1185 channels to correspond to the data lines. Taking 256 grayscale levels as an example, the data of each color requires 8 bits, plus one reserved bit, a total of 9 bits. The data processing speed required for a drive control chip is as high as 1185*2250*120*9=2880Mbps. And a component with a data unit of 9 bits has an operating frequency of 2280 / 9=320MHz. This will generate serious electromagnetic radiation. The point-to-point transmission unit P2P provides three signal lines, red, blue and green, for each first driving control chip, which can reduce the operating frequency to 320 / 3=106.67MHz.

[0063] According to the above, taking the first center frequency f1 as 640MHz as an example, the bus of each first driving control chip operates at 640MHz / 6=106.67MHz, and the data recovery unit RC also needs to operate at 106.67MHz in order to receive the first timing control signal. However, after the data recovery unit RC converts the first timing control signal from a serial signal to a parallel signal to obtain an internal data signal, the subsequent parallel signal only needs to operate at 106.67 / (1185 / 3)MHz=0.27MHz in terms of processing the serial signal to a parallel signal by the signal line of each color of the three colors of red, blue and green.

[0064] The digital logic register transfer unit DRT is connected to the data recovery unit RC and is used to receive and process the internal data signal and generate a first driving control clock.

[0065] Specifically, the digital logic register transfer unit DRT includes a shift register, a sampling latch, a holding latch, a digital-to-analog converter, etc., which are used to convert the internal data signal into the first driving signal or the second driving signal.

[0066] The buffer unit BU is connected to the digital logic register transfer unit DRT and is used for buffering output input impedance and providing a stable first driving signal.

[0067] The data bus unit DB is connected to the buffer unit BU and is used to transmit the first drive signal to the display panel 10. Specifically, take a panel with a resolution of 4740*2250 as an example. There are 3*4740 data lines for red, blue and green, which are evenly divided into 12 drive control chips (6 first drive control chips and 6 second drive control chips). The data bus unit DB of each drive control chip needs to provide 3*4740 / 12=1185 data lines.

[0068] The constituent units of the second drive control chip are the same as the constituent units of the first drive control chip.

[0069] Please refer to Figure 4 , Figure 4The frequency and radiation intensity diagram of the first driving control chip C11-C16 and the second driving control chip C21-C26 of the driving control circuit assembly of the display device 1 provided in the embodiment of the present application when they are running, wherein the working frequency of the data recovery unit RC of the first driving control chip C11-C16, i.e., the Configurable Serial Periphery Interface (CSPI) Clock-data recovery, is, for example, 160Mhz, and the working frequency of the data recovery unit RC of the second driving control chip C21-C26, i.e., the Configurable Serial Periphery Interface (CSPI) Clock-data recovery, is, for example, 152.5Mhz. The first driving control module C1 and the second driving control module C2 operate at different clock frequencies, resulting in a 3dB decrease in radiation intensity compared to the driving control chip of the prior art.

[0070] Please refer to Figure 1 On the other hand, the present application provides a display device 1 including: a display panel 10 and the display device driving control circuit component in the above embodiment.

[0071] The display panel 10 includes a plurality of pixel units.

[0072] Please refer to Figure 2 and Figure 3 The display device driving control circuit component is connected to the display panel 10, the first timing controller T1 and the first driving control module C1 are used to drive a part of the multiple pixel units in a split-screen driving manner, such as the multiple pixel units in the left half of the display area of ​​the display panel 10, and the second timing controller T2 and the second driving control module C2 are used to drive the rest of the multiple pixel units, such as the multiple pixel units in the right half of the display area of ​​the display panel 10.

[0073] In some embodiments of the present application, the timing control module T includes a processor unit P, the processor unit P is electrically connected to the first timing controller T1 and the second timing controller T2, and is used to transmit a differential signal to the first timing controller T1 and the second timing controller T2. The first timing controller T1 includes: a spread spectrum crystal oscillator frequency multiplication unit SSC, a differential signal receiving unit VB, an algorithm unit AL, a timing generation unit TG, and a point-to-point transmission unit P2P.

[0074] The spread spectrum crystal oscillator frequency multiplication unit SSC is used to provide the first timing control clock.

[0075] The differential signal receiving unit VB is used to receive a differential signal from the processor unit.

[0076] The video capture unit VI is connected to the differential signal receiving unit VB and is used to convert the differential signal into video data.

[0077] The algorithm unit AL is connected to the video capture unit VI and is used to process the video data.

[0078] The timing generation unit TG is connected to the algorithm unit AL and is used to generate the first timing control clock.

[0079] The point-to-point transmission unit P2P is connected to the timing generation unit TG and is used to transmit the first timing control signal or the second timing control signal.

[0080] The constituent units of the second timing controller T2 are the same as the constituent units of the first timing controller T1 .

[0081] The constituent units of the second timing controller are the same as those of the first timing controller. The point-to-point transmission unit P2P of the first timing controller T1 provides first timing control signals of different frequencies to different first drive control chips C11-C16 according to the frequency range after the spread spectrum crystal oscillator frequency multiplication unit SSC is spread. The point-to-point transmission unit P2P of the second timing controller T2 provides second timing control signals of different frequencies to different second drive control chips C21-C26 according to the frequency range after the spread spectrum crystal oscillator frequency multiplication unit SSC is spread. For example, taking the first timing controller T1 as an example, the first center frequency f1 of the first timing control clock is 640MHz, which is provided in parallel to the six first drive control chips C11-C16, and the bus of each first drive control chip only needs to work at 640MHz / 6=106.67MHz. Generally, the point-to-point transmission unit P2P provides three signal lines of red, blue and green for each first drive control chip.

[0082] In some embodiments of the present application, the first driving control chip C11-C16 includes: a data recovery unit RC, a digital logic register transfer unit DRT, a buffer unit BU, and a data bus unit DB.

[0083] The data recovery unit RC is used to receive and process the first timing control signal sent by the point-to-point transmission unit P2P of the first timing controller T1, and convert the first timing control signal from a serial signal to a parallel signal to obtain an internal data signal. Specifically, a panel with a split screen frame rate of 120Hz and a resolution of 4740*2250 is taken as an example. There are a total of 3*4740 data lines for red, blue and green, which are evenly divided into 12 drive control chips (6 first drive control chips and 6 second drive control chips). Each drive control chip needs to provide 3*4740 / 12=1185 channels to correspond to the data lines. Taking 256 grayscale levels as an example, the data of each color requires 8 bits, plus one reserved bit, a total of 9 bits. The data processing speed required for a drive control chip is as high as 1185*2250*120*9=2880Mbps. And a component with a data unit of 9 bits has an operating frequency of 2280 / 9=320MHz. This will generate serious electromagnetic radiation. The point-to-point transmission unit P2P provides three signal lines, red, blue and green, for each first driving control chip, which can reduce the operating frequency to 320 / 3=106.67MHz.

[0084] According to the above, taking the first center frequency f1 as 640MHz as an example, the bus of each first driving control chip operates at 640MHz / 6=106.67MHz, and the data recovery unit RC also needs to operate at 106.67MHz in order to receive the first timing control signal. However, after the data recovery unit RC converts the first timing control signal from a serial signal to a parallel signal to obtain an internal data signal, the subsequent parallel signal only needs to operate at 106.67 / (1185 / 3)MHz=0.27MHz in terms of processing the serial signal to a parallel signal by the signal line of each color of the three colors of red, blue and green.

[0085] The digital logic register transfer unit DRT is connected to the data recovery unit RC and is used to receive and process the internal data signal and generate a first driving control clock.

[0086] Specifically, the digital logic register transfer unit DRT includes a shift register, a sampling latch, a holding latch, a digital-to-analog converter, etc., which are used to convert the internal data signal into the first driving signal or the second driving signal.

[0087] The buffer unit BU is connected to the digital logic register transfer unit DRT and is used for buffering output input impedance and providing a stable first driving signal.

[0088] The data bus unit DB is connected to the buffer unit BU and is used to transmit the first drive signal to the display panel 10. Specifically, take a panel with a resolution of 4740*2250 as an example. There are 3*4740 data lines for red, blue and green, which are evenly divided into 12 drive control chips (6 first drive control chips and 6 second drive control chips). The data bus unit DB of each drive control chip needs to provide 3*4740 / 12=1185 data lines.

[0089] The data bus unit DB is connected to the buffer unit BU, and is used to convert the internal data signal into the first driving signal or the second driving signal, and is used to transmit the first driving signal or the second driving signal to the display panel 10 .

[0090] The constituent units of the second driving control chips C21 - C26 are the same as the constituent units of the first driving control chips C11 - C16.

[0091] This application has at least the following advantages:

[0092] The display device 1 driving control circuit component and the display device 1 provided in the present application make the frequency of the first timing control clock of the first timing controller T1 and the frequency of the second timing control clock of the second timing controller T2 different, so that the radiation intensity generated during operation is greatly reduced compared with the display device of the prior art, thereby greatly reducing the intensity of electromagnetic interference, thereby solving the problem that the multiple driving chips of the display device 1 of the prior art have the same clock frequency and cause excessive electromagnetic interference.

[0093] The display device driving control circuit assembly and the display device provided in the embodiments of the present application are introduced in detail above.

[0094] Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and core idea of ​​the present application. At the same time, for technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A display device driving control circuit assembly, characterized in that: The display device driving control circuit assembly comprises: A timing control module, comprising a first timing controller and a second timing controller, wherein the first timing controller comprises a first clock register, and the second timing controller comprises a second clock register, wherein the first timing controller is used to transmit a first timing control signal according to a first timing control clock, and the second timing controller is used to transmit a second timing control signal according to a second timing control clock, and the frequency of the second timing control clock is different from the frequency of the first timing control clock, and the frequencies of the first timing control clock and the second timing control clock are obtained by modifying the first clock register and the second clock register respectively; A first drive control module, comprising a plurality of first drive control chips electrically connected to the first timing controller, wherein each of the first drive control chips is used to receive the first timing control signal and generate a first drive signal according to the first timing control signal, so as to further transmit the first drive signal to the display panel, wherein the first drive signal is embedded with a first drive control clock; and a second drive control module, comprising a plurality of second drive control chips electrically connected to the second timing controller, wherein each of the second drive control chips is used to receive the second timing control signal and generate a second drive signal according to the second timing control signal, so as to further transmit the second drive signal to the display panel, wherein the second drive signal is embedded with a second drive control clock, and the frequency of the second drive control clock is different from the frequency of the first drive control clock; The first drive control chip includes: a data recovery unit, a digital logic register transmission unit, a buffer unit and a data bus unit; The data recovery unit of the first driving control module is used to receive and process the first timing control signal sent by the first timing controller, and convert the first timing control signal from a serial signal to a parallel signal to obtain an internal data signal; The digital logic register transmission unit of the first drive control module is connected to the data reply unit and is used to receive and process the internal data signal and generate a first drive control clock; The buffer unit of the first drive control module is connected to the digital logic register transmission unit and is used to buffer the output input impedance and provide a stable first drive signal; The data bus unit of the first driving control module is connected to the buffer unit and is used to transmit the first driving signal to the display panel; The component units of the second drive control chip are the same as the component units of the first drive control chip; The first driving control module is used to determine the operating frequency of the bus of each of the first driving control chips according to the first center frequency and the number of the first driving control chips, to determine the number of channels of each of the first driving control chips according to the sum of the number of the first driving control chips and the second driving control chips, the number of sub-pixel color types, and the resolution of the panel, and to determine the first driving signal with a reduced frequency according to the operating frequency of the bus of the first driving control chip, the number of channels of each of the first driving control chips, and the number of signal lines of each of the first driving control chips, wherein the first center frequency is used to determine the frequency range of the first timing control clock; The second drive control module is used to determine the bus operating frequency of each of the second drive control chips according to the second center frequency and the number of the second drive control chips, to determine the number of channels of each of the second drive control chips according to the sum of the number of the first drive control chips and the second drive control chips, the number of sub-pixel color types, and the resolution of the panel, and to determine the second drive signal with a reduced frequency according to the bus operating frequency of the second drive control chip, the number of channels of each of the second drive control chips, and the number of signal lines of each of the second drive control chips. The second center frequency is used to determine the frequency range of the second timing control clock.

2. The display device driving control circuit assembly according to claim 1, characterized in that: The first timing controller comprises: a spread spectrum crystal oscillator frequency multiplication unit, configured to provide the first timing control clock; and a point-to-point transmission unit, configured to embed the first timing control clock into the first timing control signal and transmit the first timing control signal; The constituent units of the second timing controller are the same as those of the first timing controller, and the frequency range of the first timing control clock does not overlap with the frequency range of the second timing control clock.

3. The display device driving control circuit assembly according to claim 2, characterized in that: The spread spectrum crystal oscillator frequency multiplication unit of the first timing controller is used to provide the first timing control clock according to the first center frequency f1 and the first spread spectrum ratio value r1, and the frequency range of the first timing control clock is f1(1-r1) to f1(1+r1). The spread spectrum crystal oscillator frequency multiplication unit of the second timing controller is used to provide the second timing control clock according to the second center frequency f2 and the second spread spectrum ratio value r2, and the frequency range of the second timing control clock is f2(1-r2) to f2(1+r2).

4. The display device driving control circuit assembly according to claim 3, characterized in that: The first timing controller is a master timing controller, and the second timing controller is a slave timing controller. The second center frequency f2 of the second timing control clock in the second timing controller is set by offsetting the first center frequency f1 of the first timing control clock in the first timing controller, and meets the conditions of f1>f2, and f1(1-r1)>f2(1+r2).

5. The display device driving control circuit assembly according to claim 4, characterized in that: A frequency difference (f1-f2) / f1 between the second center frequency f2 of the second timing control clock and the first center frequency f1 of the first timing control clock is 2% to 10%.

6. A display device, characterized in that: The display device comprises: A display panel including a plurality of pixel units; and A display device driving control circuit assembly is connected to the display panel and includes: A timing control module, comprising a first timing controller and a second timing controller, wherein the first timing controller comprises a first clock register, and the second timing controller comprises a second clock register, wherein the first timing controller is used to transmit a first timing control signal according to a first timing control clock, and the second timing controller is used to transmit a second timing control signal according to a second timing control clock, and the frequency of the second timing control clock is different from the frequency of the first timing control clock, and the frequencies of the first timing control clock and the second timing control clock are obtained by modifying the first clock register and the second clock register respectively; A first drive control module, comprising a plurality of first drive control chips electrically connected to the first timing controller, wherein each of the first drive control chips is used to receive the first timing control signal and generate a first drive signal according to the first timing control signal, so as to further transmit the first drive signal to the display panel, wherein the first drive signal is embedded with a first drive control clock; and a second drive control module, comprising a plurality of second drive control chips electrically connected to the second timing controller, wherein each of the second drive control chips is used to receive the second timing control signal and generate a second drive signal according to the second timing control signal, so as to further transmit the second drive signal to the display panel, wherein the second drive signal is embedded with a second drive control clock, and the frequency of the second drive control clock is different from the frequency of the first drive control clock; Wherein, the first timing controller and the first driving control module are used to drive a part of the plurality of pixel units, and the second timing controller and the second driving control module are used to drive the rest of the plurality of pixel units; The first drive control chip includes: a data recovery unit, a digital logic register transmission unit, a buffer unit and a data bus unit; The data recovery unit of the first driving control module is used to receive and process the first timing control signal sent by the first timing controller, and convert the first timing control signal from a serial signal to a parallel signal to obtain an internal data signal; The digital logic register transmission unit of the first drive control module is connected to the data reply unit and is used to receive and process the internal data signal and generate a first drive control clock; The buffer unit of the first drive control module is connected to the digital logic register transmission unit and is used to buffer the output input impedance and provide a stable first drive signal; The data bus unit of the first driving control module is connected to the buffer unit and is used to transmit the first driving signal to the display panel; The component units of the second drive control chip are the same as the component units of the first drive control chip; The first driving control module is used to determine the operating frequency of the bus of each of the first driving control chips according to the first center frequency and the number of the first driving control chips, to determine the number of channels of each of the first driving control chips according to the sum of the number of the first driving control chips and the second driving control chips, the number of sub-pixel color types, and the resolution of the panel, and to determine the first driving signal with a reduced frequency according to the operating frequency of the bus of the first driving control chip, the number of channels of each of the first driving control chips, and the number of signal lines of each of the first driving control chips, wherein the first center frequency is used to determine the frequency range of the first timing control clock; The second drive control module is used to determine the bus operating frequency of each of the second drive control chips according to the second center frequency and the number of the second drive control chips, to determine the number of channels of each of the second drive control chips according to the sum of the number of the first drive control chips and the second drive control chips, the number of sub-pixel color types, and the resolution of the panel, and to determine the second drive signal with a reduced frequency according to the bus operating frequency of the second drive control chip, the number of channels of each of the second drive control chips, and the number of signal lines of each of the second drive control chips. The second center frequency is used to determine the frequency range of the second timing control clock.

7. The display device according to claim 6, characterized in that: The first timing controller comprises: a spread spectrum crystal oscillator frequency multiplication unit, configured to provide the first timing control clock; and a point-to-point transmission unit, configured to embed the timing control clock into the first timing control signal and transmit the first timing control signal; The constituent units of the second timing controller are the same as those of the first timing controller, and the frequency range of the first timing control clock does not overlap with the frequency range of the second timing control clock.

8. The display device according to claim 7, characterized in that: The spread spectrum crystal oscillator frequency multiplication unit of the first timing controller is used to provide the first timing control clock according to the first center frequency f1 and the first spread spectrum ratio value r1, and the frequency range of the first timing control clock is f1(1-r1) to f1(1+r1). The spread spectrum crystal oscillator frequency multiplication unit of the second timing controller is used to provide the second timing control clock according to the second center frequency f2 and the second spread spectrum ratio value r2, and the frequency range of the second timing control clock is f2(1-r2) to f2(1+r2).

9. The display device according to claim 8, characterized in that: The first timing controller is a master timing controller, and the second timing controller is a slave timing controller. The second center frequency f2 of the second timing control clock in the second timing controller is set by offsetting the first center frequency f1 of the first timing control clock in the first timing controller, and meets the conditions of f1>f2, and f1(1-r1)>f2(1+r2).

10. The display device according to claim 9, characterized in that: A frequency difference (f1-f2) / f1 between the second center frequency f2 of the second timing control clock and the first center frequency f1 of the first timing control clock is 2% to 10%.

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