Simulation verification method, device and computing equipment

Abstract

The embodiment of the present application provides a simulation verification method, apparatus and computing device. The method includes: obtaining the system code of the system-level chip, the system code corresponding to multiple modules; determining at least one target module from the multiple modules according to the simulation requirements; calling the hardware accelerator to perform simulation verification on the at least one target module; and obtaining the first simulation verification result returned by the hardware accelerator. The present application determines at least one target module that needs to be simulated and verified from the multiple modules corresponding to the system code, and only performs simulation verification on at least one target module, thereby reducing unnecessary modules occupying hardware accelerator resources and effectively improving the simulation verification efficiency for at least one target module.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of chips, and in particular to a simulation verification method, device and computing equipment. Background Art

[0002] As the number of gates in large-scale integrated circuits increases, the speed of simulating and verifying system-on-chip (SOC) using simulators is getting slower and slower. In order to solve this problem, hardware accelerators are usually used to simulate and verify the system-on-chip to increase the speed of simulation and verification.

[0003] The system-level chip implements the functions corresponding to multiple systems by running the system codes corresponding to multiple systems. The system codes correspond to multiple functional modules, and different functional modules are used to implement different functions of the system, such as algorithm modules, clock modules, power consumption control modules, etc. The simulation verification of the system-level chip is mainly for the simulation verification of multiple functional modules, that is, to determine whether there are problems with multiple functional modules.

[0004] Currently, when performing interaction between algorithms in a SOC chip or simulating and verifying a certain algorithm of a system, there will be a shortage of hardware accelerator resources, which will also lead to low efficiency of the simulation and verification process. Summary of the invention

[0005] The embodiments of the present application provide a simulation verification method, apparatus and computing device to solve the problems of tight hardware accelerator resources and low efficiency of the simulation verification process in the prior art.

[0006] In a first aspect, an embodiment of the present application provides a simulation verification method, the method comprising:

[0007] Acquire a system code of a system-on-chip, wherein the system code corresponds to a plurality of modules;

[0008] According to the simulation requirements, determining at least one target module from the multiple modules;

[0009] Calling a hardware accelerator to perform simulation verification on the at least one target module;

[0010] Obtain a first simulation verification result returned by the hardware accelerator.

[0011] In a second aspect, an embodiment of the present application provides a simulation verification method, which is applied to a hardware accelerator, and the method includes:

[0012] Receiving a call instruction of an electronic device; the call instruction includes at least one target module determined from a system code of a system-level chip;

[0013] Acquire test data corresponding to the at least one target module;

[0014] Performing simulation verification on the at least one target module based on the test data to obtain a simulation verification result;

[0015] The simulation verification result is sent to the electronic device.

[0016] In a third aspect, an embodiment of the present application provides a simulation verification device, the device comprising:

[0017] An acquisition unit is used to acquire a system code of a system-level chip, wherein the system code corresponds to a plurality of modules; and acquire a first simulation verification result returned by the hardware accelerator;

[0018] A determination unit, configured to determine at least one target module from among the plurality of modules according to a simulation requirement;

[0019] The calling unit is used to call the hardware accelerator to perform simulation verification on the at least one target module.

[0020] In a fourth aspect, an embodiment of the present application provides a simulation verification device, which is applied to a hardware accelerator, and the device includes:

[0021] A receiving unit, configured to receive a calling instruction of an electronic device; the calling instruction includes at least one target module determined from a system code of a system-level chip;

[0022] An acquisition unit, configured to acquire test data corresponding to the at least one target module;

[0023] A simulation verification unit, configured to perform simulation verification on the at least one target module based on the test data to obtain a simulation verification result;

[0024] A sending unit is used to send the simulation verification result to the electronic device.

[0025] In a fifth aspect, an embodiment of the present application provides a computing device, including a processing component and a storage component; the storage component stores one or more computer instructions; the one or more computer instructions are used to be called and executed by the processing component; the processing component is used to:

[0026] Acquire a system code of a system-on-chip, wherein the system code corresponds to a plurality of modules;

[0027] According to the simulation requirements, determining at least one target module from the multiple modules;

[0028] Calling a hardware accelerator to perform simulation verification on the at least one target module;

[0029] Obtain a first simulation verification result returned by the hardware accelerator.

[0030] In a sixth aspect, an embodiment of the present application provides a computing device, including a processing component and a storage component;

[0031] The storage component stores one or more computer instructions; the one or more computer instructions are used to be called and executed by the processing component;

[0032] The processing component is used to:

[0033] Receiving a call instruction of an electronic device; the call instruction includes at least one target module determined from a system code of a system-level chip;

[0034] Acquire test data corresponding to the at least one target module;

[0035] Performing simulation verification on the at least one target module based on the test data to obtain a simulation verification result;

[0036] The simulation verification result is sent to the electronic device.

[0037] In the seventh aspect, an embodiment of the present invention provides a non-temporary machine-readable storage medium, on which executable code is stored. When the executable code is executed by a processor of an electronic device, the processor can at least implement the simulation verification method described in the first aspect.

[0038] In an eighth aspect, an embodiment of the present invention provides a non-temporary machine-readable storage medium having executable code stored thereon. When the executable code is executed by a processor of an electronic device, the processor can at least implement the simulation verification method described in the second aspect.

[0039] The embodiment of the present application provides a simulation verification method, apparatus and computing device. The method includes: obtaining the system code of the system-level chip, the system code corresponding to multiple modules; determining at least one target module from the multiple modules according to the simulation requirements; calling the hardware accelerator to perform simulation verification on the at least one target module; and obtaining the first simulation verification result returned by the hardware accelerator. The present application determines at least one target module that needs to be simulated and verified from the multiple modules corresponding to the system code, and only performs simulation verification on at least one target module, thereby reducing unnecessary modules occupying hardware accelerator resources and effectively improving the simulation verification efficiency for at least one target module.

[0040] These and other aspects of the present application will become more clearly understood in the description of the following embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, a brief introduction will be given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0042] Figure 1 A schematic diagram showing a flow chart of an embodiment of a simulation verification method provided by the present application;

[0043] Figure 2 A schematic diagram showing a flow chart of another embodiment of the simulation verification method provided by the present application;

[0044] Figure 3 A schematic diagram showing the structure of an embodiment of a simulation verification device provided by the present application is shown;

[0045] Figure 4 A schematic diagram showing the structure of another embodiment of the simulation verification device provided by the present application is shown;

[0046] Figure 5 Shown with Figure 3 A schematic diagram of the structure of the corresponding computing device;

[0047] Figure 6 Shown with Figure 4 Schematic diagram of the structure of the corresponding computing device. DETAILED DESCRIPTION

[0048] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application.

[0049] In some of the processes described in the specification and claims of this application and the above-mentioned figures, multiple operations that appear in a specific order are included, but it should be clearly understood that these operations may not be executed in the order in which they appear in this article or executed in parallel. The serial numbers of the operations, such as 101, 102, etc., are only used to distinguish between different operations, and the serial numbers themselves do not represent any execution order. In addition, these processes may include more or fewer operations, and these operations may be executed in sequence or in parallel. It should be noted that the descriptions of "first", "second", etc. in this article are used to distinguish different messages, devices, modules, etc., do not represent the order of precedence, and do not limit the "first" and "second" to be different types.

[0050] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of this application.

[0051] At present, when simulating the algorithms of some systems in SOC chips, after obtaining the system codes of these systems, simulation testers will simulate and verify the system codes. Since the system codes involve many integrated gate circuits, the simulation speed of the simulator is relatively slow. However, due to the rapid development of chips, the requirements for simulation speed are relatively strict. Therefore, simulation testers generally use hardware accelerators to simulate the system. However, the system code corresponds to multiple functional modules, such as the algorithm module corresponding to the system and many modules included in the real operating environment, such as the power control module, clock module and bus module, etc.

[0052] Hardware accelerators are generally divided into several hardware accelerator blocks for use by simulation testers. Simulation testers call corresponding hardware accelerator blocks to simulate the integrated gate circuit corresponding to the system. However, since the integrated gate circuit corresponding to the system includes power consumption control modules, clock modules, bus modules and other modules that are not related to the algorithm corresponding to the system, these modules will occupy the resources of the hardware accelerator during simulation testing, resulting in insufficient hardware accelerator resources. Alternatively, during the simulation test, it is found that these modules have operating errors or the module version in the system is low, and these modules need to be debugged or upgraded, resulting in reduced simulation efficiency.

[0053] In order to solve the above technical problems, the embodiments of the present application provide a simulation verification method, device and computing equipment. The method includes: obtaining the system code of the system-level chip, the system code corresponds to multiple modules; according to the simulation requirements, determining at least one target module in the multiple modules; calling the hardware accelerator to perform simulation verification on the at least one target module; obtaining the first simulation verification result returned by the hardware accelerator. The present application determines at least one target module that needs to be simulated and verified in the multiple modules corresponding to the system code, and only performs simulation verification on at least one target module, which can reduce unnecessary modules occupying hardware accelerator resources and effectively improve the simulation verification efficiency for at least one target module.

[0054] Figure 1The flowchart of an embodiment of the simulation verification method provided by the present application is shown, wherein the execution subject of the embodiment of the present application can be an electronic device installed with a third-party application, and the third-party application is used to execute the above simulation verification method based on the instructions of the electronic device. Figure 1 As shown, the method includes:

[0055] 101. Obtain the system code of the system-on-chip.

[0056] The system code corresponds to multiple modules. Among them, the system code can be pre-edited and can be sent to the electronic device by the editor of the system code. Generally, in the system-level simulation and verification process of the SOC chip, different hardware accelerator blocks will be called to simulate and verify the corresponding system codes of different systems of the SOC chip. At this time, the system code corresponds to multiple modules. Taking the NPU system as an example, the system code corresponding to the NPU system corresponds to the algorithm module for implementing AI functions included in the NPU system, the power consumption control module and clock module inside the system, and the bus module for data transmission with other systems.

[0057] If there are multiple target systems, the number of modules unrelated to the algorithm module, such as the power consumption control module, the clock module, and the bus module for data transmission with other systems, will also increase.

[0058] 102. According to simulation requirements, determine at least one target module from multiple modules.

[0059] In general, since the algorithm module in the system is relatively complex, if the algorithm module is simulated using ordinary simulation, it is necessary to use a hardware accelerator to simulate the algorithm module so as to quickly obtain the simulation result. The at least one target module corresponding to the simulation requirement can be at least one algorithm module. For example, if at least one target system is an NPU system, the target module can be an algorithm module for implementing AI functions. If at least one target system is an NPU system and an ISP system, the target module can be an algorithm module for image processing and an algorithm module for implementing AI functions.

[0060] As mentioned above, the number of modules unrelated to the algorithm will increase as the number of target systems increases. If these algorithm-unrelated modules are processed together with the algorithm modules, the efficiency of simulation verification of the algorithm modules will be affected. Therefore, it is necessary to determine at least one target module among multiple modules, that is, to determine at least one algorithm module, and then only perform verification simulation on at least one algorithm module.

[0061] Among them, in the system code, the identifiers corresponding to the multiple modules are inconsistent, so at least one target module can be determined based on the identifiers corresponding to the multiple modules.

[0062] Optionally, determining at least one target module from a plurality of modules may be implemented as: searching for at least one target module corresponding to the at least one module identifier from a plurality of modules according to at least one module identifier included in the simulation requirement.

[0063] The identifier may be a module name, for example, the name of the target module is generally mode 1.

[0064] 103. Call a hardware accelerator to perform simulation verification on at least one target module.

[0065] Optionally, the hardware accelerator may be a Paladin hardware accelerator, etc., and at least one target module may be simulated by calling an interface of the hardware accelerator.

[0066] Optionally, after determining at least one target module from multiple modules according to simulation requirements, it also includes: generating a logic circuit according to the code logic of the at least one target module; calling a hardware accelerator to perform simulation verification on the at least one target module, including: calling a hardware accelerator to perform simulation verification on the logic circuit.

[0067] After the algorithm module is determined, the code included in the algorithm module is input into a conversion tool so that the conversion tool generates a logic circuit according to the code logic of at least one target module.

[0068] Alternatively, the conversion tool may be any open source tool that converts code into logic circuits.

[0069] Optionally, the conversion tool may also have a visual interface, which can display the logic circuit on the visual interface so that the user can view the logic circuit, so that the user can determine the logic problem based on the logic circuit, so as to reduce the logic problems of the target circuit before calling the simulator to simulate and verify the target circuit, which can effectively improve the simulation efficiency of the target circuit afterwards.

[0070] Optionally, calling a hardware accelerator to perform simulation verification on a target circuit may be implemented by: establishing a network connection with the hardware accelerator; and sending the logic circuit to the hardware accelerator based on the network connection.

[0071] The network connection may be a local area network connection, a wide area network connection, and the like.

[0072] Generally speaking, chip companies will purchase hardware accelerators for chip simulation and verification, and allocate the hardware accelerators to the corresponding network. Electronic devices running third-party programs can connect to the corresponding network and the hardware accelerator, so that the logic circuit can be sent to the hardware accelerator so that the hardware accelerator can simulate and verify the target circuit.

[0073] 104. Obtain a first simulation verification result returned by the hardware accelerator.

[0074] The first simulation verification result includes whether the execution logic of at least one target module is incorrect, and if so, the incorrect field and the error type.

[0075] After the electronic device obtains the first simulation verification result, if the execution logic of at least one target module is incorrect, the code of the at least one target module is debugged based on the first simulation verification result.

[0076] Optionally, after calling the hardware accelerator to perform simulation verification on at least one target module, the method further includes: calling a simulator to simulate other modules among the multiple modules except the at least one target module.

[0077] Among them, the other modules except at least one target module among the multiple modules are multiple modules unrelated to the simulation module, and these modules occupy less resources. Therefore, the simulation results can be determined in a shorter time using ordinary simulation.

[0078] Furthermore, the electronic device obtains a second simulation verification result returned by the simulator.

[0079] The second simulation authentication result includes whether the execution logic corresponding to other modules is incorrect, and whether there is a problem with the interconnectivity between the modules.

[0080] Optionally, if the first simulation verification result and the second simulation verification result are correct, calling a hardware accelerator to perform simulation verification on the system code;

[0081] Receive a third simulation verification result returned by the hardware accelerator.

[0082] If the first simulation verification result and the second simulation verification result are correct, it means that the execution logic of at least one target module is correct and there is no problem with the connectivity between other modules. At this time, the multiple modules corresponding to the system code can be converted into corresponding logic circuits through the above-mentioned conversion tool, and the logic circuits are sent to the hardware accelerator so that the hardware accelerator returns the third simulation verification result.

[0083] The third simulation verification result includes whether there is a problem with the connectivity between at least one target module and other modules, and the problem field and problem type if there is a problem, so that the system code can be debugged based on the problem field and problem type.

[0084] The embodiment of the present application provides a simulation verification method, which includes: the method includes: obtaining a system code of a system-level chip, the system code corresponding to multiple modules; determining at least one target module from the multiple modules according to simulation requirements; calling a hardware accelerator to perform simulation verification on the at least one target module; and obtaining a first simulation verification result returned by the hardware accelerator. The present application determines at least one target module that needs to be simulated and verified from the multiple modules corresponding to the system code, and only performs simulation verification on the at least one target module, thereby reducing unnecessary modules occupying hardware accelerator resources and effectively improving the simulation verification efficiency for at least one target module.

[0085] Figure 2 A flow chart of another embodiment of the simulation verification method provided by the present application is shown. The execution subject of the embodiment of the present application may be a hardware accelerator. The method includes:

[0086] 201. Receive a calling instruction from an electronic device.

[0087] The calling instruction includes at least one target module determined from the system code of the system-on-chip.

[0088] 202. Obtain test data corresponding to at least one target module.

[0089] Optionally, at least one target module only includes the execution logic of the algorithm, but does not include test data corresponding to the algorithm. Therefore, the verification process of at least one target module can be implemented as follows: determine the corresponding algorithm in at least one target module, send a data acquisition request to the memory based on the algorithm, so that the memory returns the corresponding data, and verify and simulate the algorithm module based on the data.

[0090] The memory may be a double data rate synchronous dynamic random access (DDR) memory, which is used to store test data corresponding to the algorithm included in the target module, and the test data is used to test whether the execution logic of the algorithm in at least one target module is incorrect.

[0091] 203. Perform simulation verification on at least one target module based on the test data to obtain a simulation verification result.

[0092] 204. Send the simulation verification result to the electronic device.

[0093] In order to further illustrate the simulation verification method provided in the embodiment of the present application, generally, there are many interactions between the NPU system and the ISP system algorithm. The embodiment of the present application takes the interaction between the NPU system and the ISP system algorithm as an example.

[0094] The electronic device receives the system codes corresponding to the NPU system and the ISP system sent by the user, and determines the NPU algorithm module and the ISP algorithm module from the multiple modules corresponding to the system codes based on the identifiers corresponding to the respective algorithm modules of the NPU system and the ISP system.

[0095] Furthermore, the code conversion tool is used to convert the NPU algorithm module and the ISP algorithm module into their corresponding logic circuits, the electronic device is connected to the network where the accelerator is located, and the logic circuits corresponding to the NPU algorithm module and the ISP algorithm module are sent to the accelerator. If the test result needs to simulate the delay information of the actual interaction, a delay module is added between the logic circuits corresponding to the NPU algorithm module and the ISP algorithm module to simulate the delay information in the actual operation of the chip.

[0096] The accelerator requests test data from the DDR memory based on the received logic circuit, so that the DDR memory sends the test data to the accelerator, and the accelerator performs simulation verification on the logic circuit based on the test data.

[0097] Furthermore, the user can send the modules other than the NPU algorithm module and the ISP algorithm module among the multiple modules to a common simulator, so that the common simulator can simulate and verify the interconnection of these modules and their ability to assist in work.

[0098] Finally, when the simulation verification results of the NPU algorithm module, ISP algorithm module and the verification results of other modules are correct, the electronic device calls the hardware accelerator to simulate the system code, thereby receiving the hardware accelerator's connectivity with the NPU algorithm module, ISP algorithm module and other modules.

[0099] Figure 3 A schematic diagram of the structure of an embodiment of the simulation verification device provided by the present application is shown in FIG. Figure 3 The device comprises: an acquisition unit 31, a determination unit 32, and a calling unit 33.

[0100] The acquisition unit 31 is used to acquire the system code of the system-on-chip, where the system code corresponds to multiple modules; and acquire the first simulation verification result returned by the hardware accelerator.

[0101] The determination unit 32 is used to determine at least one target module from the multiple modules according to simulation requirements.

[0102] The calling unit 33 is used to call the hardware accelerator to perform simulation verification on the at least one target module.

[0103] Optionally, the determining unit 32 is specifically configured to: search, according to the at least one module identifier included in the simulation requirement, for at least one target module corresponding to the at least one module identifier in the plurality of modules;

[0104] Optionally, the above-mentioned device also includes a generation unit, which is used to generate a logic circuit according to the code logic of the at least one target module.

[0105] Optionally, the calling unit 33 is specifically used to: call a hardware accelerator to perform simulation verification on the logic circuit.

[0106] Optionally, the above-mentioned device further includes: an establishing unit, used to establish a network connection with the hardware accelerator; and a sending unit, used to send the logic circuit to the hardware accelerator based on the network connection.

[0107] Optionally, the calling unit 33 is further used to: call a simulator to simulate other modules among the multiple modules except the at least one target module.

[0108] Optionally, the above-mentioned device also includes: a receiving unit, used to receive a second simulation verification result returned by the simulator.

[0109] Optionally, the calling unit 33 is further configured to: if the first simulation verification result and the second simulation verification result are correct, call the hardware accelerator to perform simulation verification on the system code.

[0110] Optionally, the receiving unit is further used to receive a third simulation verification result returned by the hardware accelerator.

[0111] Figure 3 The simulation verification device can execute Figure 1 The implementation principle and technical effect of the simulation verification method described in the embodiment are not described in detail. The specific way in which each module and unit performs operations in the simulation verification device in the above embodiment has been described in detail in the embodiment of the method, and will not be described in detail here.

[0112] Figure 4 FIG. 1 shows a schematic diagram of the structure of another embodiment of the simulation verification device provided by the present application. Figure 4 The device comprises: a receiving unit 41 , an acquiring unit 42 , a simulation verification unit 43 , and a sending unit 44 .

[0113] The receiving unit 41 is used to receive a calling instruction of an electronic device; the calling instruction includes at least one target module determined from the system code of the system-level chip;

[0114] An acquisition unit 42, configured to acquire test data corresponding to the at least one target module;

[0115] A simulation verification unit 43, configured to perform simulation verification on the at least one target module based on the test data to obtain a simulation verification result;

[0116] The sending unit 44 is used to send the simulation verification result to the electronic device.

[0117] Figure 4 The simulation verification device can execute Figure 2 The implementation principle and technical effect of the simulation verification method described in the embodiment are not described in detail. The specific way in which each module and unit performs operations in the simulation verification device in the above embodiment has been described in detail in the embodiment of the method, and will not be described in detail here.

[0118] In one possible design, Figure 3 The simulation verification apparatus of the embodiment shown can be implemented as a computing device, such as Figure 5 As shown, the computing device may include a storage component 501 and a processing component 502;

[0119] The storage component 501 stores one or more computer instructions, wherein the one or more computer instructions are called and executed by the processing component 502 .

[0120] The processing component 502 is used to:

[0121] Acquire a system code of a system-on-chip, wherein the system code corresponds to a plurality of modules;

[0122] According to the simulation requirements, determining at least one target module from the multiple modules;

[0123] Calling a hardware accelerator to perform simulation verification on the at least one target module;

[0124] Obtain a first simulation verification result returned by the hardware accelerator.

[0125] In one possible design, Figure 4 The simulation verification apparatus of the embodiment shown can be implemented as a computing device, such as Figure 6 As shown, the computing device may include a storage component 601 and a processing component 602;

[0126] The storage component 601 stores one or more computer instructions, wherein the one or more computer instructions are called and executed by the processing component 602 .

[0127] The processing component 602 is used to:

[0128] Receiving a call instruction of an electronic device, wherein the call instruction includes at least one target module determined from a system code of a system-level chip;

[0129] Acquire test data corresponding to the at least one target module;

[0130] Performing simulation verification on the at least one target module based on the test data to obtain a simulation verification result;

[0131] The simulation verification result is sent to the electronic device.

[0132] In addition, an embodiment of the present invention provides a non-transitory machine-readable storage medium, wherein an executable code is stored on the non-transitory machine-readable storage medium. When the executable code is executed by a processor of an electronic device, the processor can at least implement the above-mentioned Figure 1 The page display method provided in the illustrated embodiment.

[0133] An embodiment of the present invention provides a non-transitory machine-readable storage medium, wherein an executable code is stored on the non-transitory machine-readable storage medium. When the executable code is executed by a processor of an electronic device, the processor can at least implement the above-mentioned Figure 2 The page display method provided in the illustrated embodiment.

[0134] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0135] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Those of ordinary skill in the art may understand and implement it without creative effort.

[0136] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0137] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A simulation verification method, characterized in that: include: Acquire a system code of a system-on-chip, wherein the system code corresponds to a plurality of modules; According to the simulation requirements, determining at least one target module from the multiple modules; Performing simulation verification on the at least one target module by calling an interface of the hardware accelerator; Obtaining a first simulation verification result returned by the hardware accelerator; Wherein, determining at least one target module from the multiple modules includes: According to at least one module identifier included in the simulation requirement, at least one target module corresponding to the at least one module identifier is searched among the multiple modules.

2. The method according to claim 1, characterized in that After determining at least one target module from the plurality of modules according to the simulation requirements, the method further includes: generating a logic circuit according to the code logic of the at least one target module; The calling of the hardware accelerator to perform simulation verification on the at least one target module includes: A hardware accelerator is called to perform simulation verification on the logic circuit.

3. The method according to claim 2, characterized in that The method further comprises: Establishing a network connection with the hardware accelerator; The logic circuit is sent to the hardware accelerator based on the network connection.

4. The method according to claim 1, characterized in that: After calling the hardware accelerator to perform simulation verification on the at least one target module, the method further includes: Invoking a simulator to simulate other modules among the plurality of modules except the at least one target module; Receive a second simulation verification result returned by the simulator.

5. The method according to claim 4, characterized in that The method further comprises: If the first simulation verification result and the second simulation verification result are correct, calling the hardware accelerator to perform simulation verification on the system code; Receive a third simulation verification result returned by the hardware accelerator.

6. A simulation verification method, characterized in that: Applied to a hardware accelerator, the method comprises: Receiving a call instruction of an electronic device, the call instruction comprising at least one target module determined from a system code of the system-level chip, the at least one target module being found in a plurality of modules corresponding to the system code of the system-level chip according to at least one module identifier included in the simulation requirement; Acquire test data corresponding to the at least one target module; Performing simulation verification on the at least one target module based on the test data to obtain a simulation verification result; The simulation verification result is sent to the electronic device.

7. A simulation verification device, characterized in that: The device comprises: An acquisition unit is used to acquire a system code of a system-level chip, wherein the system code corresponds to a plurality of modules; and acquire a first simulation verification result returned by a hardware accelerator; A determination unit, configured to determine at least one target module from the plurality of modules according to the simulation requirement; wherein the determining at least one target module from the plurality of modules comprises: searching for at least one target module corresponding to the at least one module identifier from the plurality of modules according to at least one module identifier included in the simulation requirement; The calling unit is used to perform simulation verification on the at least one target module by calling the interface of the hardware accelerator.

8. A simulation verification device, characterized in that: Applied to a hardware accelerator, the device comprises: A receiving unit, configured to receive a calling instruction of an electronic device; the calling instruction includes at least one target module determined from a system code of the system-level chip, wherein the at least one target module is found in a plurality of modules corresponding to the system code of the system-level chip according to at least one module identifier included in the simulation requirement; An acquisition unit, configured to acquire test data corresponding to the at least one target module; A simulation verification unit, configured to perform simulation verification on the at least one target module based on the test data to obtain a simulation verification result; A sending unit is used to send the simulation verification result to the electronic device.

9. A computing device, characterized in that including a processing component and a storage component; The storage component stores one or more computer instructions; the one or more computer instructions are used to be called and executed by the processing component; The processing component is used to: Acquire a system code of a system-on-chip, wherein the system code corresponds to a plurality of modules; According to the simulation requirements, determining at least one target module from the multiple modules; Performing simulation verification on the at least one target module by calling an interface of the hardware accelerator; Obtaining a first simulation verification result returned by the hardware accelerator; Wherein, determining at least one target module from the multiple modules includes: According to at least one module identifier included in the simulation requirement, at least one target module corresponding to the at least one module identifier is searched among the multiple modules.

10. A computing device, characterized in that: including a processing component and a storage component; The storage component stores one or more computer instructions; the one or more computer instructions are used to be called and executed by the processing component; The processing component is used to: Receiving a call instruction of an electronic device; the call instruction includes at least one target module determined from the system code of the system-level chip, and the at least one target module is found in multiple modules corresponding to the system code of the system-level chip according to at least one module identifier included in the simulation requirement; Acquire test data corresponding to the at least one target module; Performing simulation verification on the at least one target module based on the test data to obtain a simulation verification result; The simulation verification result is sent to the electronic device.

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