3D Flash Memory Components

Abstract

The present invention provides a variety of three-dimensional flash memory elements. A three-dimensional flash memory element includes a gate stack structure, a plurality of separated arc-shaped channel columns, a plurality of source / drain columns, and a charge storage structure. The gate stack structure is disposed on a substrate and includes a plurality of gate layers electrically insulated from each other. A plurality of separated arc-shaped channel columns are disposed on the substrate and are located in the gate stack structure. A plurality of source / drain columns are disposed on the substrate and penetrate the gate stack structure, wherein two source / drain columns are respectively disposed at both ends of each of the plurality of arc-shaped channel columns. The charge storage structure is disposed between each of the plurality of gate layers and the corresponding arc-shaped channel column.

Description

Technical Field

[0001] The invention relates to a semiconductor element, and in particular to a three-dimensional flash memory element. Background Art

[0002] Non-volatile memory (eg, flash memory) is widely used in personal computers and other electronic devices because it has the advantage that stored data will not disappear even after power is turned off.

[0003] The three-dimensional flash memory commonly used in the industry at present includes NOR flash memory and NAND flash memory. In addition, another three-dimensional flash memory is AND flash memory, which can be used in multi-dimensional flash memory arrays and has the advantages of high integration and high area utilization, and fast operation speed. Therefore, the development of three-dimensional flash memory components has gradually become the current trend. Summary of the invention

[0004] The invention provides a three-dimensional flash memory element, in which the channel column of the storage unit is designed to be arc-shaped or semicircular, which can provide a longer channel length and better element performance.

[0005] The three-dimensional flash memory element of the present invention includes a gate stack structure, a plurality of separated arc-shaped channel columns, a plurality of source / drain columns, and a charge storage structure. The gate stack structure is disposed on a substrate and includes a plurality of gate layers electrically insulated from each other. A plurality of separated arc-shaped channel columns are disposed on the substrate and in the gate stack structure. A plurality of source / drain columns are disposed on the substrate and penetrate the gate stack structure, wherein two source / drain columns are respectively disposed at both ends of each of the plurality of arc-shaped channel columns. The charge storage structure is disposed between each of the plurality of gate layers and the corresponding arc-shaped channel column.

[0006] In one embodiment of the present invention, two adjacent arc-shaped channel columns are arranged in mirror-symmetric configuration.

[0007] In one embodiment of the present invention, two adjacent arc-shaped channel columns are arranged in a non-mirror symmetric manner.

[0008] In one embodiment of the present invention, an insulating column is disposed between two adjacent ones of the arc-shaped channel columns.

[0009] In one embodiment of the present invention, a plurality of insulating pillars in different rows are arranged in a staggered manner.

[0010] In one embodiment of the present invention, a plurality of insulating pillars in different rows are aligned.

[0011] In one embodiment of the present invention, the source / drain columns at the corresponding ends adjacent to two of the plurality of arc-shaped channel columns are separated from each other.

[0012] In one embodiment of the present invention, a contact plug is electrically connected to the source / drain pillars at the corresponding ends adjacent to two of the plurality of arc-shaped channel pillars.

[0013] In an embodiment of the present invention, the contact plug is electrically connected to a conductive line on the gate stack structure.

[0014] In one embodiment of the present invention, the conductive line includes a source line or a bit line.

[0015] In one embodiment of the present invention, the source / drain columns at the corresponding ends of two adjacent arc-shaped channel columns that are arranged in a mirror-symmetrical manner are connected to each other.

[0016] In one embodiment of the present invention, a contact plug is electrically connected to the connected source / drain pillars.

[0017] In one embodiment of the present invention, the sidewall of each of the charge storage structures has a substantially smooth profile.

[0018] In one embodiment of the present invention, a sidewall of each of the charge storage structures has a wavy cross-section.

[0019] In one embodiment of the present invention, each of the arc-shaped channel columns is continuous in its extension direction.

[0020] In an embodiment of the present invention, each of the plurality of arc-shaped channel columns is discontinuous in its extension direction, and a plurality of channel portions of the arc-shaped channel columns only correspond to the plurality of gate layers.

[0021] In one embodiment of the present invention, two ends of each of the plurality of arc-shaped channel pillars are equidistant from the corresponding gate layer.

[0022] In one embodiment of the present invention, the distances between two ends of each of the plurality of arc-shaped channel pillars and the corresponding gate layer are unequal.

[0023] In one embodiment of the present invention, the material of the plurality of arc-shaped channel pillars includes non-doped polysilicon, and the material of the plurality of source / drain pillars includes doped polysilicon.

[0024] In one embodiment of the present invention, from a top view, each of the plurality of source / drain pillars has an L-shape, an I-shape, a polygon, a circle, an arc, a ring or a combination thereof.

[0025] Based on the above, in the three-dimensional flash memory device of the present invention, the memory cell has an arc-shaped channel column, which produces a curvature effect to enhance the operation of programming / erasing the memory cell, and can provide a longer channel length and better device performance. In addition, the three-dimensional flash memory device of the present invention can have a high integration and high area utilization, and meet the requirements of fast operation speed.

[0026] In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below with reference to the accompanying drawings for detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] FIG. 1A to FIG. 1I The manufacturing process of the three-dimensional flash memory device according to the first embodiment of the present invention is shown, wherein Figures 1A to 1F is a three-dimensional schematic diagram, and Figure 1G to Figure 1I It is a schematic diagram viewed from above.

[0028] FIG. 2A to FIG. 2F It is a top view schematically illustrating a manufacturing process of a three-dimensional flash memory device according to a second embodiment of the present invention.

[0029] FIG. 3A to FIG. 3F It is a top view schematically illustrating a manufacturing process of a three-dimensional flash memory device according to a third embodiment of the present invention.

[0030] Figure 4 FIG. 4 is a top view of a three-dimensional flash memory device according to a fourth embodiment of the present invention.

[0031] Figure 5 FIG. 4 is a top view of a three-dimensional flash memory device according to a fifth embodiment of the present invention.

[0032] Figure 6 FIG. 4 is a top view of a three-dimensional flash memory device according to a sixth embodiment of the present invention.

[0033] Fig. 7A FIG. 4 is a schematic cross-sectional view of a partial three-dimensional flash memory element according to an embodiment of the present invention.

[0034] Figure 7B FIG. 4 is a schematic cross-sectional view of a partial three-dimensional flash memory element according to another embodiment of the present invention.

[0035]

Explanation of symbols

[0036] 10, 20, 30, 40, 50, 60: Three-dimensional flash memory components

[0037] MC1, MC2, MC3: Storage unit

[0038] 100: Base

[0039] 102: Stacked structure

[0040] 103, 107, 120: Isolation layer

[0041] 104: First film layer

[0042] 105, 113, 114: Insulation columns

[0043] 106: Second film layer

[0044] 107: Rectangular opening

[0045] 108, H1, Ha, Hb: Columnar opening

[0046] 110: Charge storage structure

[0047] 110a, 110c: silicon oxide layer

[0048] 110b: Silicon nitride layer

[0049] 112: Channel Column

[0050] 112a, 112b, 112c, 112d: channel part

[0051] 118, 218, 318: Source / drain posts

[0052] 122, 222, 320: Contact plug

[0053] 124: Conductive layer

[0054] 126: Gate layer

[0055] 219: Extension

[0056] 317: Source / drain material layer

[0057] H2: Opening

[0058] T, T1, T2, Ta: Channel

[0059] W, W1, W2: Conductive wire DETAILED DESCRIPTION

[0060] FIG. 1A to FIG. 1I The manufacturing process of the three-dimensional flash memory device according to the first embodiment of the present invention is shown, wherein Figures 1A to 1F is a three-dimensional schematic diagram, and Figure 1G to Figure 1I It is a schematic diagram viewed from above.

[0061] Please refer to Figure 1A, a stacked structure 102 is formed on a substrate 100. The substrate 100 may be a semiconductor substrate, such as a silicon-containing substrate. In one embodiment, a doped region may be formed in the substrate 100 according to design requirements. In one embodiment, a dielectric layer, such as a silicon oxide layer, is formed on the substrate 100. In the present embodiment, the stacked structure 102 includes a plurality of first film layers 104 and a plurality of second film layers 106 alternately stacked on the substrate 100. In one embodiment, the first film layer 104 is an insulating layer (such as a silicon oxide layer), and the second film layer 106 is a sacrificial layer (such as a silicon nitride layer). However, the present invention is not limited thereto. In another embodiment, the first film layer 104 is an insulating layer (such as a silicon oxide layer), and the second film layer 106 is a gate layer (such as a doped polysilicon layer).

[0062] Next, a patterning process is performed to form a plurality of trenches T that penetrate the stacked structure 102. In one embodiment, during the patterning process, a portion of the substrate 100 is also removed at the same time, so that the trench T extends into the substrate 100. In one embodiment, the sidewalls of the trench T are wavy, and this shape is defined by a mask. More specifically, the trench T includes a plurality of rectangular openings 107 and a plurality of columnar openings 108 that are alternately arranged. In one embodiment, the columnar openings 108 are configured to set a subsequently formed memory cell therein, and the rectangular openings 107 are configured to set an insulating layer therein that electrically insulates adjacent memory cells from each other. In the present embodiment, from the perspective of the top view, the columnar openings 108 have an elliptical profile, but the present invention is not limited thereto. In other embodiments, the columnar openings 108 may have profiles of other shapes, such as quasi-circular, circular, quasi-elliptical, or polygonal.

[0063] In one embodiment, the columnar openings 108 of adjacent channels T are configured to be staggered with each other. More specifically, the columnar openings 108 of the channels T in the (N)th column and the (N+2)th column are aligned with each other, the columnar openings 108 of the channels T in the (N+1)th column and the (N+3)th column are aligned with each other, and the columnar openings 108 of the channels T in the (N)th column and the (N+1)th column are staggered with each other, where N is a positive integer. However, the present invention is not limited thereto. In another embodiment, the columnar openings 108 of adjacent channels T may be configured to be aligned with each other.

[0064] Please refer to Figure 1B, a charge storage structure 110 is formed on the surface of the stacked structure 102 and the trench T. In one embodiment, the charge storage structure 110 is an oxide-nitride-oxide (ONO) composite layer. For example, the charge storage structure 110 includes a silicon oxide layer 110a, a silicon nitride layer 110b, and a silicon oxide layer 110c stacked in sequence on the surface of the trench T. In one embodiment, the charge storage structure 110 is blanket-formed on the sidewalls and bottom surface of the trench T. From another perspective, a plurality of charge storage structures 110 are respectively formed on the sidewalls and bottom surface of the trench T and are connected to each other. However, the present invention is not limited thereto. In another embodiment, a plurality of charge storage structures 110 are formed on the opposite sidewalls of each trench T in the form of spacers.

[0065] Please refer to Figure 1C , a channel column 112 is formed on the charge storage structure 110 in the trench T. More specifically, the channel column 112 is conformally formed along the sidewall of the trench T and does not fill the trench T. In one embodiment, the material of the channel column 112 includes non-doped polysilicon. In one embodiment, two channel columns 112 are formed on opposite sidewalls of each trench T in the form of spacers, and the charge storage structure 110 at the bottom of the trench T is exposed.

[0066] Please refer to Figure 1D , an insulating column 114 is filled in the lower part of each trench T. In one embodiment, the material of the insulating column 114 includes silicon oxide. In one embodiment, the top surface of the insulating column 114 is lower than the uppermost first film layer 104 and higher than the uppermost second film layer 106.

[0067] Next, a semiconductor plug 116 is filled in the upper portion of each trench T. In one embodiment, the material of the semiconductor plug 116 includes non-doped polysilicon. In one embodiment, the top surface of the semiconductor plug 116 is substantially flush with the top surface of the stack structure 102 .

[0068] Please refer to Figure 1E , remove the film layer in the rectangular opening 107 of the trench T, leaving the film layer in the columnar opening 108 of the trench T. In one embodiment, photolithography and etching processes are performed to remove the charge storage structure 110, the insulating column 114 and the semiconductor plug 116 in each rectangular opening 107 of the trench T. In one embodiment, Figure 1E After the removal step, the remaining channel pillars 112 are arc-shaped or semicircular, and the channel pillars 112 facing each other are arranged in a mirror-symmetrical manner.

[0069] In the present invention, the channel pillars 112 may be described as arc-shaped channel pillars or semi-cylindrical channel layers, and the channel pillars 112 are continuous in their extension direction (between the top and the bottom of the pillar-shaped opening 108). More specifically, each channel pillar 112 is integral in its extension direction and is not divided into a plurality of disconnected parts.

[0070] Please refer to Figure 1F , two source / drain columns 118 are formed at both ends of each arc-shaped channel column 112. In the present invention, the source / drain column is also called a buried diffusion region. In one embodiment, a sidewall plasma doping process is performed to implant dopants into the portion of the channel column 112 exposed by the rectangular opening 107 to form the source / drain column 118. In one embodiment, the sidewall plasma doping process also implants dopants into the portion of the semiconductor plug 116 exposed by the rectangular opening 107.

[0071] For the sake of convenience, the following Figure 1G to Figure 1I Only the top schematic diagram of the second film layer 106 which is the uppermost layer in the stack structure 102 is shown to clearly understand the corresponding relationship between the various components.

[0072] Please refer to Figure 1G , an isolation layer 120 is formed in the rectangular opening 107 of the trench T. In one embodiment, the material of the isolation layer 120 includes silicon oxide. In one embodiment, the top surface of the isolation layer 120 is substantially flush with the top surface of the stack structure 102 .

[0073] Please refer to Figure 1H , the second film layer 106 of the stacked structure 102 is replaced with a gate layer 126. In one embodiment, the second film layer 106 in the stacked structure 102 is removed to form a plurality of horizontal openings between adjacent first film layers 104. Thereafter, a gate layer 126 is formed in the formed horizontal openings. The material of the gate layer 126 includes tungsten (W), cobalt (Co), aluminum (Al), tungsten silicide (WSix) or cobalt silicide (CoSix). In addition, in other embodiments, before forming the gate layer 126, a buffer layer and a barrier layer may be sequentially formed in the horizontal openings. The material of the buffer layer includes a high dielectric constant material having a dielectric constant greater than 7, such as aluminum oxide (Al2O3), hafnium oxide (HfO2), lanthanum oxide (La2O5), transition metal oxides, lanthanide oxides or combinations thereof. The material of the barrier layer includes titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN) or combinations thereof.

[0074] In one embodiment, when the second film layer 106 is a sacrificial layer (e.g., a silicon nitride layer), this replacement step is performed. After the replacement step, the stacked structure 102 may include a plurality of first film layers 104 (e.g., an insulating layer) and a plurality of gate layers 126 (e.g., a tungsten layer) stacked alternately. In one embodiment, the stacked structure 102 is also referred to as a gate stack structure. However, the present invention is not limited thereto. In another embodiment, when the second film layer 106 is a gate layer (e.g., a doped polysilicon layer), this replacement step may be omitted. At this point, the fabrication of a plurality of memory cells MC1 of the present invention is completed.

[0075] In one embodiment, each memory cell MC1 includes a gate layer 126 arranged horizontally, an arc-shaped channel column 112 arranged vertically, a charge storage structure 110 located between the gate layer 126 and the arc-shaped channel column 112, and two source / drain columns 118 located at both ends of the arc-shaped channel column 112. In this embodiment, the source / drain columns 118 at the corresponding ends of two adjacent ones of the plurality of arc-shaped channel columns 112 are separated from each other. In this embodiment, the face-to-face memory cells MC1 are arranged in a mirror-symmetrical manner and can be operated separately or together according to design requirements. The memory cell MC1 of the present invention has an arc-shaped channel column, which produces a curvature effect to enhance the operating margin of programming / erasing the memory cell, and can provide a longer channel length and better device performance.

[0076] In one embodiment, the three-dimensional flash memory device of the present invention may further include a conductive layer 124 as a heater to heat the gate stack structure. Figure 1H As shown. In one embodiment, a conductive layer 124 can be formed simultaneously in the above-mentioned replacement step. The conductive layer 124 is disposed on the substrate 100, and is adjacent to the sidewall of the gate stack structure and extends along the sidewall of the gate stack structure. In addition, in the present embodiment, the conductive layer 124 is disposed along two opposite sidewalls of the gate stack structure, but the present invention is not limited thereto. In other embodiments, the conductive layer 124 can be disposed only beside one sidewall of the gate stack structure, or the conductive layer 124 can be disposed around the gate stack structure, depending on actual needs. In one embodiment, the method of using the conductive layer 124 as a heater is to apply a relatively high voltage and a relatively low voltage to the electrical connection points at the two opposite ends of the conductive layer 124 to form a voltage difference. In this way, an electric current can be generated. When the current passes through the conductive layer 124, the conductive layer 124 generates heat, which can heat the adjacent gate stack structure.

[0077] Please refer to Fig. 1I, a plurality of conductive lines W1 and W2 are formed on the stack structure 102 to electrically connect the plurality of memory cells MC1. More specifically, the conductive line W1 electrically connects the memory cells MC1 in the (N)th column and the (N+2)th column, and the conductive line W2 electrically connects the memory cells MC1 in the (N+1)th column and the (N+3)th column, where N is a positive integer. In one embodiment, each of the conductive lines W1 and W2 is a source line or a bit line according to design requirements. In one embodiment, the plurality of conductive lines W1 and W2 are electrically connected to the plurality of memory cells MC1 through contact plugs 122, respectively. More specifically, the contact plugs 122 are electrically connected to the source / drain columns 118 at the corresponding ends adjacent to two of the plurality of arc-shaped channel columns 112. In one embodiment, from a top view, the contact plugs 122 partially overlap with the adjacent source / drain columns 118. At this point, the fabrication of the three-dimensional flash memory element 10 of the present invention is completed.

[0078] FIG. 2A to FIG. 2F FIG. 1 is a top view schematic diagram of a manufacturing process of a three-dimensional flash memory device according to a second embodiment of the present invention. FIG. 2A to FIG. 2F Only the top view of the second film layer 106 in the stacked structure is shown to clearly understand the corresponding relationship between the components. In addition, in the second embodiment, components with similar materials or functions as those in the first embodiment are marked with similar reference numerals.

[0079] Please refer to Figure 2A , forming a stacked structure on the substrate. In one embodiment, the stacked structure includes a plurality of first film layers and a plurality of second film layers 106 alternately stacked on the substrate. In one embodiment, the first film layer is an insulating layer (e.g., a silicon oxide layer), and the second film layer is a sacrificial layer (e.g., a silicon nitride layer). However, the present invention is not limited thereto. In another embodiment, the first film layer is an insulating layer (e.g., a silicon oxide layer), and the second film layer is a gate layer (e.g., a doped polysilicon layer).

[0080] Next, a patterning process is performed to form a plurality of trenches Ta penetrating the stacked structure. In one embodiment, during the patterning process, a portion of the substrate is also removed simultaneously, so that the trenches Ta extend into the substrate. In one embodiment, the sidewalls of the trenches Ta are substantially vertical.

[0081] Then, an isolation layer 103 is formed in the trench Ta. In one embodiment, the material of the isolation layer 103 includes silicon oxide. In one embodiment, the top surface of the isolation layer 103 is substantially flush with the top surface of the stack structure.

[0082] Please refer to Figure 2B, a patterning process is performed to form a plurality of columnar openings Ha penetrating the stacked structure and the isolation layer 103. In this embodiment, the columnar opening Ha has an elliptical profile from the top view, but the present invention is not limited thereto. In other embodiments, the columnar opening Ha may have a profile of other shapes, such as a circle, a quasi-ellipse, or a polygon.

[0083] In one embodiment, adjacent columnar openings Ha are configured to be aligned with each other. More specifically, the columnar openings Ha of the (N)th column and the (N+1)th column are aligned with each other, where N is a positive integer. However, the present invention is not limited thereto. In another embodiment, adjacent columnar openings Ha are configured to be staggered with each other.

[0084] Then, a charge storage structure 110 is formed on the sidewall of the columnar opening Ha. In the present embodiment, each of the charge storage structures 110 has a ring-shaped profile when viewed from above. In one embodiment, the charge storage structure 110 is an oxide-nitride-oxide (ONO) composite layer. For example, the charge storage structure 110 includes a silicon oxide layer 110a, a silicon nitride layer 110b, and a silicon oxide layer 110c stacked in sequence on the sidewall of the columnar opening Ha. In one embodiment, the charge storage structure 110 is formed on the sidewall and bottom surface of the columnar opening Ha. However, the present invention is not limited thereto. In another embodiment, the charge storage structure 110 is formed only on the sidewall of the columnar opening Ha.

[0085] Then, a channel column 112 is formed on the charge storage structure 110 in the columnar opening Ha. In the present embodiment, each of the channel columns 112 has a ring-shaped profile when viewed from above. In one embodiment, the material of the channel column 112 includes non-doped polysilicon. In one embodiment, the channel column 112 is formed only on the sidewall of each columnar opening Ha, while exposing the charge storage structure 110 at the bottom of the columnar opening Ha.

[0086] Next, the columnar opening Ha is filled with an insulating column 113. In one embodiment, the material of the insulating column 113 includes silicon oxide. In one embodiment, the top surface of the insulating column 113 is substantially flush with the top surface of the stacked structure.

[0087] Please refer to Figure 2C, a patterning process is performed to form a plurality of columnar openings Hb that penetrate the charge storage structure 110 and the channel column 112. In one embodiment, the patterning process also removes a portion of the insulating column 113 and a portion of the isolation layer 103. In one embodiment, two columnar openings Hb are formed on opposite sides of each annular channel column 112 and the corresponding annular charge storage structure 110. In this embodiment, from the above viewing angle, the columnar opening Hb has a circular profile, but the present invention is not limited thereto. In other embodiments, the columnar opening Hb may have a profile of other shapes, such as an ellipse, a quasi-ellipse, or a polygon.

[0088] Next, the columnar opening Hb is filled with source / drain pillars 218. In one embodiment, the material of the source / drain pillars 218 includes doped polysilicon.

[0089] Please refer to Figure 2D , an annealing process is performed to diffuse the dopants in the source / drain column 218 outward. In one embodiment, the dopants in each source / drain column 218 diffuse toward both sides along the corresponding annular channel column 112 to form a source / drain column 218 having two extensions 219 .

[0090] Please refer to Figure 2E , replacing the second film layer 106 of the stacked structure with a gate layer 126. In one embodiment, the material of the gate layer 126 includes tungsten (W), cobalt (Co), aluminum (Al), tungsten silicide (WSix) or cobalt silicide (CoSix). In addition, in other embodiments, a buffer layer and a barrier layer may also be formed between the gate layer 126 and the charge storage structure 110. The material of the buffer layer is, for example, a material with a high dielectric constant greater than 7, such as aluminum oxide (Al2O3), hafnium oxide (HfO2), lanthanum oxide (La2O5), transition metal oxides, lanthanide oxides or combinations thereof. The material of the barrier layer is, for example, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN) or combinations thereof.

[0091] In one embodiment, when the second film layer 106 is a sacrificial layer (e.g., a silicon nitride layer), the replacement step is performed. However, the present invention is not limited thereto. In another embodiment, when the second film layer 106 is a gate layer (e.g., a doped polysilicon layer), the replacement step can be omitted. Thus, the fabrication of a plurality of memory cells MC2 of the present invention is completed.

[0092] In the present embodiment, each memory cell MC2 includes a gate layer 126 arranged horizontally, an arc-shaped channel column 112 arranged vertically, a charge storage structure 110 located between the gate layer 126 and the arc-shaped channel column 112, and two source / drain columns 218 located at both ends of the arc-shaped channel column 112. In the present embodiment, the source / drain columns 218 at the corresponding ends of two adjacent arc-shaped channel columns 112 are connected to each other. In the present embodiment, the face-to-face memory cells MC2 are mirror-symmetrically arranged and share the source / drain column 218. Such shared and larger area source / drain column 218 helps to reduce resistance, and the contact plug formed subsequently has a larger landing area. The memory cell MC2 of the present invention has an arc-shaped channel column, which produces a curvature effect to enhance the operability of programming / erasing the memory cell, and can provide a longer channel length and better device performance.

[0093] In one embodiment, the three-dimensional flash memory device of the present invention may further include a conductive layer 124 as a heater to heat the gate stack structure. Figure 2E In one embodiment, a conductive layer 124 may be formed simultaneously in the above replacement step. The conductive layer 124 is disposed on the substrate and is adjacent to and extends along the sidewall of the gate stack structure.

[0094] Please refer to Figure 2F , a plurality of conductive wires W are formed on the stacked structure to electrically connect the plurality of memory cells MC2. More specifically, the conductive wires W electrically connect the memory cells MC2 in the (N)th column and the (N+1)th column, where N is a positive integer. In one embodiment, each of the conductive wires W is a source line or a bit line according to design requirements. In one embodiment, the plurality of conductive wires W are electrically connected to the plurality of memory cells MC2 through contact plugs 222, respectively. More specifically, the contact plugs 222 are electrically connected to the source / drain columns 218 at the corresponding ends of two adjacent ones of the plurality of arc-shaped channel columns 112. In one embodiment, from a top view, the contact plugs 222 partially overlap with the adjacent source / drain columns 218. At this point, the fabrication of the three-dimensional flash memory element 20 of the present invention is completed.

[0095] FIG. 3A to FIG. 3F FIG. 1 is a top view schematic diagram of a manufacturing process of a three-dimensional flash memory element according to a third embodiment of the present invention. FIG. 3A to FIG. 3F Only the top view of the second film layer 106 in the stacked structure is shown to clearly understand the corresponding relationship between the components. In addition, in the third embodiment, components with similar materials or functions to those in the first or second embodiment are marked with similar reference numerals.

[0096] Please refer to Figure 3A , forming a stacked structure on the substrate. In one embodiment, the stacked structure includes a plurality of first film layers and a plurality of second film layers 106 alternately stacked on the substrate. In one embodiment, the first film layer is an insulating layer (e.g., a silicon oxide layer), and the second film layer is a sacrificial layer (e.g., a silicon nitride layer). However, the present invention is not limited thereto. In another embodiment, the first film layer is an insulating layer (e.g., a silicon oxide layer), and the second film layer is a gate layer (e.g., a doped polysilicon layer).

[0097] Next, a patterning process is performed to form a plurality of columnar openings H1 that penetrate the stacked structure. In the present embodiment, the columnar openings H1 have an elliptical profile when viewed from above, but the present invention is not limited thereto. In other embodiments, the columnar openings H1 may have profiles of other shapes, such as a circle, a quasi-ellipse, or a polygon. In one embodiment, the columnar openings H1 of adjacent columns are configured to be aligned with each other. In another embodiment, the columnar openings H1 of adjacent columns are configured to be staggered with each other.

[0098] Then, a charge storage structure 110 is formed on the sidewall of the columnar opening H1. In the present embodiment, each of the charge storage structures 110 has a ring-shaped profile when viewed from above. In one embodiment, the charge storage structure 110 is an oxide-nitride-oxide (ONO) composite layer. For example, the charge storage structure 110 includes a silicon oxide layer 110a, a silicon nitride layer 110b, and a silicon oxide layer 110c stacked in sequence on the sidewall of the columnar opening Ha. In one embodiment, the charge storage structure 110 is formed on the sidewall and bottom surface of the columnar opening H1. However, the present invention is not limited thereto. In another embodiment, the charge storage structure 110 is formed only on the sidewall of the columnar opening H1.

[0099] Then, a channel column 112 is formed on the charge storage structure 110 in the columnar opening H1. In the present embodiment, each of the channel columns 112 has a ring-shaped profile when viewed from above. In one embodiment, the material of the channel column 112 includes non-doped polysilicon. In one embodiment, the channel column 112 is formed only on the sidewall of each columnar opening H1, and the charge storage structure 110 at the bottom of the columnar opening H1 is exposed.

[0100] Next, the columnar opening H1 is filled with an insulating column 105. In one embodiment, the insulating column 105 is made of silicon oxide. In one embodiment, the top surface of the insulating column 105 is substantially flush with the top surface of the stacked structure.

[0101] Please refer to Figure 3B, a patterning process is performed to form a trench T1 penetrating the stack structure, the charge storage structure 110, the channel pillar 112, and the insulating pillar 105. In one embodiment, during the patterning process, a portion of the substrate is also removed so that the trench T1 extends into the substrate. In one embodiment, the sidewalls of the trench T1 are substantially vertical.

[0102] Please refer to Figure 3C , an etching process is performed to remove a portion of the channel column 112 exposed by the trench T1 to form an opening H2 located at the end of the remaining channel column 112. In one embodiment, two openings H2 are disposed at the end of each channel column 112.

[0103] Please refer to Figure 3D A source / drain material layer 317 is formed on the surface of the trench T1, and the source / drain material layer 317 fills the opening H2. In one embodiment, the material of the source / drain material layer 317 includes doped polysilicon.

[0104] Please refer to Figure 3E , remove part of the source / drain material layer 317 to form a plurality of source / drain pillars 318. More specifically, the source / drain material layer 317 on the surface of the channel T1 is removed, leaving the source / drain material layer 317 in the opening H2 as the source / drain pillars 318. In one embodiment, two source / drain pillars 318 are disposed at the end of each channel pillar 112.

[0105] Next, an isolation layer 107 ′ is formed in the trench T1 . In one embodiment, the material of the isolation layer 107 ′ includes silicon oxide. In one embodiment, the top surface of the isolation layer 107 ′ is substantially flush with the top surface of the stack structure.

[0106] Please refer to Figure 3F , the second film layer 106 of the stacked structure is replaced by a gate layer 126. In one embodiment, the material of the gate layer 126 includes tungsten (W), cobalt (Co), aluminum (Al), tungsten silicide (WSi x ) or cobalt silicide (CoSi x ). In addition, in other embodiments, a buffer layer and a barrier layer may also be formed between the gate layer 126 and the charge storage structure 110. The material of the buffer layer is, for example, a high dielectric constant material with a dielectric constant greater than 7, such as aluminum oxide (Al2O3), hafnium oxide (HfO2), lanthanum oxide (La2O5), transition metal oxides, lanthanide oxides, or a combination thereof. The material of the barrier layer is, for example, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or a combination thereof.

[0107] In one embodiment, when the second film layer 106 is a sacrificial layer (e.g., a silicon nitride layer), the replacement step is performed. However, the present invention is not limited thereto. In another embodiment, when the second film layer 106 is a gate layer (e.g., a doped polysilicon layer), the replacement step can be omitted. Thus, the fabrication of a plurality of memory cells MC3 of the present invention is completed.

[0108] In the present embodiment, each memory cell MC3 includes a gate layer 126 arranged horizontally, an arc-shaped channel column 112 arranged vertically, a charge storage structure 110 located between the gate layer 126 and the arc-shaped channel column 112, and two source / drain columns 318 located at both ends of the arc-shaped channel column 112. In the present embodiment, the source / drain columns 318 at the corresponding ends of two adjacent ones of the plurality of arc-shaped channel columns 112 are separated from each other. In the present embodiment, the face-to-face memory cells MC3 are arranged in a mirror-symmetrical manner and can be operated separately or together according to design requirements. The memory cell MC3 of the present invention has an arc-shaped channel column, which produces a curvature effect to enhance the operability of programming / erasing the memory cell, and can provide a longer channel length and better device performance.

[0109] In one embodiment, the three-dimensional flash memory device of the present invention may further include a conductive layer 124 as a heater to heat the gate stack structure. Figure 3F In one embodiment, a conductive layer 124 may be formed simultaneously in the above replacement step. The conductive layer 124 is disposed on the substrate and is adjacent to and extends along the sidewall of the gate stack structure.

[0110] Please continue to refer to Figure 3F , a plurality of conductive wires W are formed on the stacked structure 102 to electrically connect a plurality of memory cells MC3. More specifically, the conductive wires W electrically connect the memory cells MC3 in the (N)th column and the (N+1)th column, where N is a positive integer. In one embodiment, each of the conductive wires W is a source line or a bit line according to design requirements. In one embodiment, a plurality of conductive wires W are electrically connected to a plurality of memory cells MC3 through contact plugs 320, respectively. More specifically, the contact plugs 320 are electrically connected to the source / drain columns 318 at the corresponding ends of two adjacent ones of a plurality of arc-shaped channel columns 112. In one embodiment, from a top view, the contact plugs 320 partially overlap with the adjacent source / drain columns 318. At this point, the fabrication of the three-dimensional flash memory element 30 of the present invention is completed.

[0111] In addition, the three-dimensional flash memory element of the present invention can also be varied according to the above three structures. Several structures are listed below for illustration, but they are not intended to limit the present invention. More specifically, as long as the memory cell has an arc-shaped channel column, it will produce a curvature effect to provide a longer channel length and better device performance, and such a memory cell is considered to fall within the spirit and scope of the present invention.

[0112] Figure 4 FIG. 4 is a top view of a three-dimensional flash memory device according to a fourth embodiment of the present invention. Figure 4 The three-dimensional flash memory element 40 is similar to the three-dimensional flash memory element 20 of FIG. 2 . The differences are described below, and the similarities are not repeated. In the three-dimensional flash memory element 20 of FIG. 2 , the source / drain columns 218 at the ends of adjacent arc-shaped channel columns in the same column are arranged to be separated from each other. Figure 4 In the three-dimensional flash memory element 40, the source / drain columns 218 at the ends of adjacent arc-shaped channel columns in the same column are arranged to be connected to each other. Since adjacent memory cells in the same column share this connected source / drain column 218, such a larger area of ​​the source / drain column 218 helps to reduce the resistance value, and the contact plug formed subsequently has a larger landing area. This design can also allow for more pitch reduction.

[0113] Figure 5 FIG. 4 is a top view of a three-dimensional flash memory device according to a fifth embodiment of the present invention. Figure 5 The three-dimensional flash memory element 50 is similar to the three-dimensional flash memory element 20 of FIG. 2 . The differences are described below, and the similarities are not repeated. In the three-dimensional flash memory element 20 of FIG. 2 , the source / drain columns 218 at the ends of the arc-shaped channel columns in the same column are arranged to be aligned with each other. Figure 5 In the three-dimensional flash memory element 50, the source / drain pillars 218 at the ends of the arc-shaped channel pillars in the same column are arranged to be staggered with each other. Such staggered source / drain pillars 218 can provide more process margin for the overlying contact plugs 222. Furthermore, such asymmetrical or twisted source / drain pillars 218 help reduce gate induce drain leakage (GIDL).

[0114] Figure 6 FIG. 4 is a top view of a three-dimensional flash memory device according to a sixth embodiment of the present invention. Figure 6 The three-dimensional flash memory element 60 and Figure 5 The three-dimensional flash memory element 50 is similar to the three-dimensional flash memory element 50, and the differences are described below, and the similarities are not repeated. Figure 5In the three-dimensional flash memory element 50, the extension direction of the gate layer 126 is substantially perpendicular to the extension direction of the overlying conductive line W. More specifically, Figure 5 As shown in FIG. 1 , the angle between the extension direction of the gate layer 126 and the extension direction of the overlying conductive line W is about 90 degrees. Figure 6 In the three-dimensional flash memory element 60, the extension direction of the gate layer 126 is not perpendicular to the extension direction of the overlying conductive line W. More specifically, Figure 6 As shown, the angle between the extension direction of the gate layer 126 and the extension direction of the overlying conductive line W is less than 90 degrees. Such staggered source / drain pillars 218 can provide the overlying contact plugs 222 with more process margins and help reduce gate induced drain leakage (GIDL). Furthermore, such a tilted layout can provide greater process flexibility.

[0115] Fig. 7A FIG. 4 is a schematic cross-sectional view of a partial three-dimensional flash memory element according to an embodiment of the present invention. Figure 7B FIG. 4 is a schematic cross-sectional view of a partial three-dimensional flash memory element according to another embodiment of the present invention. Fig. 7A and Figure 7B The cross-sectional configuration diagram can be applied to any structure of the three-dimensional flash memory element 10 / 20 / 30 / 40 / 50 / 60 of the present invention.

[0116] Please refer to Fig. 7A , the side of the gate stack structure is substantially vertical, and it includes a plurality of first film layers 104 (e.g., insulating layers) and a plurality of gate layers 126 arranged alternately, wherein the ends of the first film layers 104 are substantially aligned with the ends of the gate layers 126. The charge storage structure 110 is continuous in its extension direction, and the sidewall of the charge storage structure 110 has a substantially vertical cross section. In addition, the channel column 112 is continuous in its extension direction, and the sidewall of the channel column 112 has a substantially vertical cross section.

[0117] Please refer to Figure 7B, the side of the gate stack structure is wavy, and it includes a plurality of first film layers 104 (such as insulating layers) and a plurality of gate layers 126 that are alternately arranged, wherein the end of the first film layer 104 protrudes from the end of the gate layer 126. The charge storage structure 110 is continuous in its extension direction, and the sidewall of the charge storage structure 110 has a wavy cross-section. In addition, the channel column 112 is discontinuous in its extension direction, and the plurality of channel portions of the channel column only correspond to the plurality of gate layers 126. More specifically, each channel column 112 is not integral in its extension direction, but is divided into a plurality of unconnected portions. In other words, the formed channel column 112 includes a plurality of channel portions 112a, 112b, 112c, and 112d, and one channel portion is located between two adjacent first film layers 104 and corresponds to only one gate layer 126 of the adjacent stack structure. That is, the channel portion 112a, the channel portion 112b, the channel portion 112c, and the channel portion 112d are arranged in sequence and do not contact each other in the extension direction of the channel pillar 112. This configuration method limits the charge storage structure 110 and the channel pillar 112 to the corresponding side of the gate layer 126, which can greatly reduce leakage current and provide better gate control and programming efficiency.

[0118] Below, we will refer to Figures 1A to 7B , illustrating the structure of the three-dimensional flash memory element of the present invention.

[0119] The three-dimensional flash memory element 10 / 20 / 30 / 40 / 50 / 60 of the present invention includes a gate stack structure, a plurality of separated arc-shaped channel columns 112, a plurality of source / drain columns 118 / 218 / 318, and a charge storage structure 110. The gate stack structure is disposed on a substrate 100 and includes a plurality of gate layers 126 electrically insulated from each other. A plurality of separated arc-shaped channel columns 112 are disposed on the substrate 100 and penetrate the gate stack structure. A plurality of source / drain columns 118 / 218 / 318 are disposed on the substrate 100 and penetrate the gate stack structure, wherein two source / drain columns 118 / 218 / 318 are respectively disposed at both ends of each of the plurality of arc-shaped channel columns 112. The charge storage structure 110 is disposed between each of the plurality of gate layers 126 and the corresponding arc-shaped channel column 112.

[0120] In the three-dimensional flash memory element 10 / 20 / 30 / 40 of the present invention, two adjacent arc-shaped channel pillars 112 are arranged in mirror-symmetric configuration.

[0121] In the three-dimensional flash memory device 50 / 60 of the present invention, two adjacent arc-shaped channel pillars 112 are arranged in a non-mirror symmetric configuration.

[0122] In the three-dimensional flash memory device 10 / 20 / 30 / 40 / 50 / 60 of the present invention, an insulating column 114 / 113 / 105 is disposed between two adjacent arc-shaped channel columns 112 .

[0123] In the three-dimensional flash memory element 10 of the present invention, multiple insulating pillars 114 in different columns are staggered. In the three-dimensional flash memory element 20 / 30 of the present invention, multiple insulating pillars 113 / 105 in different columns are aligned. However, the present invention is not limited to this. In the three-dimensional flash memory element 10 / 20 / 30 / 40 / 50 / 60 of the present invention, multiple insulating pillars in different columns can be designed to be aligned or staggered according to layout requirements.

[0124] In the three-dimensional flash memory device 10 / 30 of the present invention, the source / drain columns 118 / 318 at the corresponding ends of two adjacent ones of the plurality of arc-shaped channel columns 112 are separated from each other. In the three-dimensional flash memory device 10 / 30 of the present invention, a contact plug 122 / 320 is electrically connected to the source / drain columns 118 / 318 at the corresponding ends of two adjacent ones of the plurality of arc-shaped channel columns 112.

[0125] In the three-dimensional flash memory device 20 / 40 / 50 / 60 of the present invention, the source / drain pillars 218 at the corresponding ends adjacent to two of the plurality of arc-shaped channel pillars 112 are connected to each other. In the three-dimensional flash memory device 20 / 40 / 50 / 60 of the present invention, a contact plug 222 is electrically connected to the connected source / drain pillars 218.

[0126] In the three-dimensional flash memory device 10 / 20 / 30 / 40 / 50 / 60 of the present invention, the contact plug 122 / 222 / 320 is electrically connected to a conductive line W1 / W2 / W on the gate stack structure.

[0127] In the three-dimensional flash memory element 10 / 20 / 30 / 40 / 50 / 60 of the present invention, the conductive lines W1 / W2 / W include source lines or bit lines.

[0128] In the three-dimensional flash memory device 10 / 20 / 30 / 40 / 50 / 60 of the present invention, the sidewalls of each of the charge storage structures 110 have a substantially smooth cross-section (see Fig. 7A ).

[0129] In the three-dimensional flash memory device 10 / 20 / 30 / 40 / 50 / 60 of the present invention, the sidewall of each of the charge storage structures 110 has a wavy cross-section (see Figure 7B ).

[0130] In the three-dimensional flash memory element 10 / 20 / 30 / 40 / 50 / 60 of the present invention, each of the arc-shaped channel pillars 112 is continuous in its extension direction (see Fig. 7A ).

[0131] In the three-dimensional flash memory element 10 / 20 / 30 / 40 / 50 / 60 of the present invention, each of the plurality of arc-shaped channel pillars 112 is discontinuous in its extension direction, and the plurality of channel portions of the arc-shaped channel pillars 112 only correspond to the plurality of gate layers 126 (see Figure 7B ).

[0132] In the three-dimensional flash memory device 10 / 20 / 30 / 40 of the present invention, the two ends of each of the plurality of arc-shaped channel pillars 112 are equidistant from the corresponding gate layer 126 .

[0133] In the three-dimensional flash memory device 50 / 60 of the present invention, the distances between the two ends of each of the plurality of arc-shaped channel pillars 112 and the corresponding gate layer are unequal.

[0134] In the three-dimensional flash memory device 10 / 20 / 30 / 40 / 50 / 60 of the present invention, the material of the plurality of arc-shaped channel pillars 112 includes non-doped polysilicon, and the material of the plurality of source / drain pillars includes doped polysilicon.

[0135] In the three-dimensional flash memory element 10 of the present invention, from a top view, the shape of each of the multiple source / drain posts 118 is L-shaped. In the three-dimensional flash memory element 20 / 50 / 60 of the present invention, from a top view, the shape of each of the multiple source / drain posts 218 is a combination of a circular / ring shape and an arc shape. In the three-dimensional flash memory element 30 of the present invention, from a top view, the shape of each of the multiple source / drain posts 318 is an arc shape. In the above-mentioned embodiments, the specific shapes of the source / drain posts are merely for illustration, but are not intended to limit the present invention. In other embodiments, the source / drain posts may have other shapes, such as I-shaped, polygonal, irregular, or a combination thereof.

[0136] In summary, in the three-dimensional flash memory device of the present invention, the memory cell has an arc-shaped channel column, which produces a curvature effect to enhance the operation of programming / erasing the memory cell, and can provide a longer channel length and better device performance. In addition, the three-dimensional flash memory device of the present invention can have a high integration and high area utilization, and meet the requirements of fast operation speed.

[0137] Although the present invention has been disclosed as above by way of embodiments, it is not intended to limit the present invention. Any person skilled in the art may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be subject to the claims.

Claims

1. A three-dimensional flash memory element, comprising: A gate stack structure is disposed on the substrate and includes a plurality of gate layers electrically insulated from each other; A plurality of separated arc-shaped channel pillars are disposed on the substrate and located in the gate stack structure; A plurality of source / drain columns are disposed on the substrate and penetrate the gate stack structure, wherein two source / drain columns are respectively disposed at two ends of each of the plurality of arc-shaped channel columns; as well as A charge storage structure disposed between each of the plurality of gate layers and the corresponding arc-shaped channel column; Each arc-shaped channel column includes two ends separated from each other, and two source / drain columns are correspondingly connected to the ends of each arc-shaped channel column. 2 . The three-dimensional flash memory device as claimed in claim 1 , wherein two adjacent arc-shaped channel pillars are arranged in a mirror-symmetrical manner. 3 . The three-dimensional flash memory device as claimed in claim 1 , wherein two adjacent ones of the arc-shaped channel pillars are arranged in a non-mirror symmetric configuration. 4 . The three-dimensional flash memory device as claimed in claim 1 , wherein an insulating column is disposed between two adjacent ones of the arc-shaped channel columns. 5 . The three-dimensional flash memory device as claimed in claim 4 , wherein the plurality of insulating pillars in different rows are arranged in a staggered manner. 6 . The three-dimensional flash memory device as claimed in claim 4 , wherein the plurality of insulating pillars in different rows are aligned. 7 . The three-dimensional flash memory element of claim 1 , wherein the source / drain columns adjacent to corresponding ends of two of the plurality of arc-shaped channel columns are separated from each other. 8 . The three-dimensional flash memory device as claimed in claim 7 , wherein a contact plug is electrically connected to the source / drain pillars at the corresponding ends adjacent to two of the plurality of arc-shaped channel pillars. 9 . The three-dimensional flash memory device as claimed in claim 8 , wherein the contact plug is electrically connected to a conductive line on the gate stack structure. 10 . The three-dimensional flash memory element of claim 9 , wherein the conductive line comprises a source line or a bit line. 11 . The three-dimensional flash memory element as claimed in claim 1 , wherein the source / drain columns at the corresponding ends of two adjacent ones of the plurality of arc-shaped channel columns that are arranged in a mirror-symmetrical manner are connected to each other. 12 . The three-dimensional flash memory device of claim 11 , wherein a contact plug is electrically connected to the connected source / drain pillars.

13. The three-dimensional flash memory device of claim 1, wherein a sidewall of each of the charge storage structures has a substantially smooth profile.

14. The three-dimensional flash memory device of claim 1, wherein a sidewall of each of the charge storage structures has a wavy cross-section. 15 . The three-dimensional flash memory device as claimed in claim 1 , wherein each of the arc-shaped channel pillars is continuous in its extension direction. 16 . The three-dimensional flash memory device as claimed in claim 1 , wherein each of the plurality of arc-shaped channel columns is discontinuous in its extension direction, and a plurality of channel portions of the arc-shaped channel columns only correspond to the plurality of gate layers. 17 . The three-dimensional flash memory device as claimed in claim 1 , wherein two ends of each of the plurality of arc-shaped channel pillars are equidistant from the corresponding gate layer. 18 . The three-dimensional flash memory device as claimed in claim 1 , wherein two ends of each of the plurality of arc-shaped channel pillars are at unequal distances from the corresponding gate layer. 19 . The three-dimensional flash memory device of claim 1 , wherein a material of the plurality of arc-shaped channel pillars comprises undoped polysilicon, and a material of the plurality of source / drain pillars comprises doped polysilicon. 20 . The three-dimensional flash memory device of claim 1 , wherein, viewed from above, each of the plurality of source / drain pillars has an L-shape, an I-shape, an irregular shape, a polygon, a circle, an arc, a ring, or a combination thereof.

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