A mixed precision arithmetic unit for data stream driven reconfigurable array

Abstract

The present invention discloses a mixed-precision arithmetic unit applied to a data stream-driven reconfigurable array, and relates to the field of arithmetic unit design. The present invention is an arithmetic unit that supports mixed precision and multiple working modes. Compared with the arithmetic units proposed at this stage, the present invention is oriented to general computing-intensive applications, and designs a high-energy-efficiency fixed-point arithmetic unit that supports multiple specifications and mixed precision, and selects the working mode according to the requirements; based on the low-power, low-overhead mixed-precision arithmetic unit designed by the present invention and a reasonable data stream scheduling method, the problem of low computing unit resource utilization and precision loss when the fixed-specification computing unit of the coarse-grained reconfigurable array is in a low-precision computing mode for neural network applications is solved, and the performance of the reconfigurable array for neural network applications is greatly improved.

Description

Technical Field

[0001] The present invention relates to the field of arithmetic unit design, and in particular to a mixed precision arithmetic unit applied to a data stream driven reconfigurable array. Background Art

[0002] The coarse-grained reconfigurable architecture for general computing-intensive applications is generally composed of processing units PE or reconfigurable units RC. The units are connected by reconfiguring the topology of interconnection lines, and the computing tasks are mapped by auxiliary software and hardware. Its main advantage is that it has achieved a good balance between performance and flexibility. Traditional general-purpose reconfigurable arrays only support single-precision integer operations, and are universal in application support. At the same time, neural network applications are an important part of computing-intensive applications. Studies have shown that for neural network applications, low-precision calculations can be performed with very low bit widths without losing precision, such as Int2, Int4, Int8 and Int16. Dedicated neural network accelerators improve processor performance and reduce hardware overhead by supporting low-precision calculation units. When supporting neural network applications in traditional reconfigurable arrays, if the calculation bit width and precision are always fixed to meet the highest requirements, it will generate a lot of area and power consumption overhead. Therefore, in order to support the characteristics of multi-precision operations of neural networks in coarse-grained reconfigurable arrays, and also support the high-precision calculation specifications of general computing-intensive applications, the reconfigurable array must support fixed-point mixed-precision calculation units in the design of the calculation units.

[0003] There are two main implementation methods for multi-precision multipliers: fission and fusion. The traditional multiplier first obtains the partial product through two input operands, and then compresses the partial product into a row of carries and a row of sums through a compression tree, and finally accumulates and sums to obtain the final result. In practical applications, Booth coding is usually used to reduce the number of partial products and the size of the compression tree, but this approach is more logically complex and requires additional control overhead. Figure 1 and Figure 2 The fission multiplier makes some changes to the standard array multiplier. It inputs two 32-bit operands X and Y and outputs a 64-bit result normally. If sub-word parallel 16-bit multiplication is to be achieved, a logical AND is performed through the input and the control signal of the precision mode selection, and the irrelevant parts P0 and P3 areas are set to 0. Only P1 and P2 areas perform valid operations. The fusion multiplier obtains a high-precision result by splicing low-precision multipliers.

[0004] It can be seen that the fission multi-precision multiplier has a smaller overall change than the standard multiplier, and the control logic is relatively simple. However, when calculating low-precision multiplication, all hardware resources are still working, resulting in a certain amount of computing power waste and unnecessary power consumption. Both types of multi-precision multipliers will increase area overhead. Among them, the fusion multi-precision multiplier has a larger area overhead while increasing throughput due to the duplication of multiple modules. From an architectural perspective, the biggest advantage of fission is the consistency of internal and external memory bandwidth. It does not require major changes to the architecture to support multi-precision calculations, but its performance, area and energy efficiency are at a disadvantage in low-precision mode, and it is not suitable for applications that require low-precision calculations, such as neural networks.

[0005] The computing bit width of the computing unit of the traditional coarse-grained reconfigurable array is always kept consistent. However, the reconfigurable array for general computing-intensive applications must be oriented to both neural network applications that require low-precision and high-parallel computing, and high-precision fixed-point computing of different specifications in remote sensing, satellite monitoring, and data processing applications such as FFT, MIMO, and matrix decomposition. At the same time, for high-precision integer computing units, directly performing low-precision operations will waste computing resources, and if low-precision multi-data parallel operations are used, the computing accuracy will be lost. In this data flow-driven architecture, how to use limited resources to improve computing efficiency and system performance, and be compatible with calculations of different precisions, and minimize the loss of precision while ensuring that the data flow bit width remains unchanged is a problem that designers need to consider.

[0006] Therefore, technicians in this field are committed to developing a mixed-precision operation unit for use in data stream-driven reconfigurable arrays. By designing a multi-mode, mixed-precision operation module, it supports fixed-point mixed-precision operations, supports fixed-point operations in operation modes such as addition and subtraction, multiplication, and multiplication and addition with or without a sign, and supports high-precision fixed-point operations while also supporting low-precision fixed-point operations in parallel. In typical applications such as neural networks, the loss of low-precision operations can be avoided, and on-chip resources can be effectively utilized with a small amount of overhead, greatly improving the throughput of system operations. Summary of the invention

[0007] In view of the above-mentioned defects of the prior art, the technical problem to be solved by the present invention is how to utilize limited resources to improve computing efficiency and system performance in a data flow-driven architecture, be compatible with calculations of different precisions, and minimize precision loss while ensuring that the data flow bit width remains unchanged.

[0008] To achieve the above-mentioned objectives, the present invention provides a mixed-precision arithmetic unit for application in a data stream-driven reconfigurable array, constructs a mixed-precision arithmetic unit based on a fission multiplier structure, supports multiple operation modes and mixed-precision multiplication and accumulation operations, is integrated into the processing unit of a coarse-grained reconfigurable array driven by a data stream, and can configure and adjust the applications mapped on the reconfigurable array.

[0009] Furthermore, the mixed-precision operation unit based on the fission multiplier structure mainly performs multiplication and addition operations, and reuses resources to realize signed / unsigned addition, subtraction, and multiplication operation modes.

[0010] Furthermore, in the mixed precision arithmetic unit based on the fission multiplier structure, the high-bit-width and high-precision multiplication operation performs Booth encoding on the partial products.

[0011] Furthermore, in the mixed-precision operation unit based on the fission multiplier structure, low-bit-width multiplication directly reuses the compression tree resources in the high-bit-width multiplier structure to achieve parallel multiplication and accumulation operations of multiple groups of low-precision data.

[0012] Furthermore, the mixed-precision arithmetic unit is integrated into the processing unit of the coarse-grained reconfigurable array. By statically configuring the PE, the execution mode of the arithmetic unit is parsed from the configuration register of the PE. At the same time, the processing unit adds a data splicing and packaging function for low-precision operations to facilitate further processing of the output data.

[0013] Furthermore, when the mixed-precision operation unit based on the fission multiplier structure adopts the mixed-precision operation mode, one operation of the operation unit is equivalent to realizing multiple multiplications and additions.

[0014] Furthermore, when mapping specific applications on a coarse-grained reconfigurable array driven by a data flow, the characteristics of the mixed-precision arithmetic unit are utilized to select appropriate dimensions to pack low-precision data for operation. The intermediate data are all high-bit width. After all the data are calculated, they are quantized into low-bit width data and written back through additional splicing operations before serving as input for the next task. Tasks with data dependencies are allocated as continuously as possible on the array to reduce the write-back of intermediate data.

[0015] Furthermore, it is implemented using Verilog.

[0016] Further, it is integrated into the CGRA system.

[0017] Furthermore, it is applied to neural networks.

[0018] In a preferred embodiment of the present invention, in a coarse-grained reconfigurable array, the processing units PE have the same structure, which is easy to expand. Therefore, it is necessary to support as many operations as possible while reducing the overhead as much as possible, so as to improve the flexibility of the overall architecture. The working mode of the module is determined by statically configuring the PE, and the configuration register contains the operation mode of the ALU. The main part of the operation unit is a multiplication and addition module. The addition can set the multiplier to 1 to reuse the multiplier and adder resources, the multiplication sets the addend to 0, and the subtraction can perform the complement operation on the addend. In the data flow-driven architecture system, the bit width of the overall data flow is consistent, so the fission structure is more suitable for application in PE to realize mixed precision operations. The integer fission multiplication structure can also be expanded into a mixed precision floating-point multiplication operation module. When realizing a multi-precision floating-point multiplier, the mantissa processing module is actually performing multiplication of two fixed-point numbers, so it can be replaced by a fission integer multi-precision multiplier. According to the IEEE standard, the mantissa widths of half-precision, single-precision, and double-precision floating-point numbers are 10, 23, and 52, respectively, which are not integer multiples of 2, so the multiplier in the mantissa processing module will waste some bits to achieve sub-word parallelism. At the same time, the order addition module also needs to support multiple low-precision additions in parallel, and the bit width issue also needs to be considered as with the mantissa part. In addition, the normalization and rounding units also need to be redesigned and split through multiplexers to support multiple precision modes.

[0019] Table 1 Operation modes supported by integer ALU

[0020]

[0021] Consider the more widely used integer operations, as shown in Table 1. When the data stream bit width is 32 bits, the ALU input and output are both 32 bits. If the result of the operation overflows, because once the algorithm is mapped to the array, the entire operation process can be determined, so if there is an overflow, the input data can be scaled in advance. Without considering overflow, only the lower 32 bits of the result are retained in normal mode. In most applications, 32 bits can cover the required data range and save a large part of the computing resource overhead. However, in low-precision operation mode, such as 8 bits, if the bit width is still unchanged, it is easy for data to overflow. If the original 32-bit output multiplication resources are reused, and it is necessary to ensure that the low-precision operation data does not overflow, according to Figure 1 The structure can only support two groups of 8-bit operations in parallel and output two 16-bit results, so the bandwidth cannot be effectively utilized.

[0022] Observing typical mixed-precision computing applications such as neural network inference, we found that multiplication and accumulation operations are widely used, so we improved the fission multiplier. The same partial product compression tree is used as usual for 32-bit operations, and supports multiplication and addition operations. Therefore, a new row is added to the last line of the compression tree as the input data for accumulation. The compression tree outputs two results, which are then summed by the adder to obtain the final operation result. When performing 8-bit low-precision operations, such as Figure 3 As shown in the figure, the partial products of the four groups of inputs are placed in the low bit of the original compression tree input, and the light gray part represents the actual 32-bit compression tree input. In this way, one operation is equivalent to performing four 8-bit multiplications and the accumulation of four products at the same time, and the bit width is sufficient to prevent overflow, without any precision loss, and can effectively utilize the data bandwidth. In addition, for 32-bit multiplication, Booth coding can also be used. Booth coding can reduce the number of partial products and reduce area overhead, but Booth coding has no benefit for multiplication operations with small bit widths, and the reduced area cannot offset the increased control logic overhead. Therefore, it is adjusted according to the specific bit width of the implementation. In the case of 32 bits or higher bit widths, Booth coding is used, and in the case of 8 bits, only the partial products are directly compressed. At the same time, the high bit needs to be filled with sign bits to meet the needs of signed or unsigned operation modes. In addition, the module can be expanded according to actual needs, for example, supporting two groups of 16-bit multiplication and accumulation operations at the same time, or expanding 32 bits to 64 bits of operation modules.

[0023] In summary, the technical features of the mixed-precision operation unit applied in the coarse-grained reconfigurable array proposed in the present invention are mainly reflected in: in the coarse-grained reconfigurable system driven by data flow, under the restriction of unchanged data bandwidth, a new implementation method supporting mixed-precision operations is proposed, which utilizes the structure of the basic multiplication unit compression tree to support high-bitwidth multiplication operations while being able to locally implement the accumulation operations of multiple groups of low-precision multiplications, thus avoiding precision loss. In typical mixed-precision applications such as neural networks, the operation throughput is greatly improved, the number of data transfers is reduced, and the overall performance is improved.

[0024] The present invention proposes a mixed-precision arithmetic unit applied in a data flow-driven coarse-grained reconfigurable array. The unit is implemented with Verilog and integrated into the entire CGRA system, and is synthesized with Design Compile to compare the area and power consumption gap between the unit and the basic arithmetic unit. The number of cycles required for execution is obtained by mapping typical low-precision applications on the CGRA processor platform, and compared with the results in a single mode, reflecting the technical effect of the present invention.

[0025] In order to compare with the mixed precision operation module proposed in the present invention, a 32-bit multiplication and addition module is used as a control unit. In addition, a reference operation unit is also implemented, which does not perform structural optimization and implements the same functions of the mixed precision operation module by using ordinary 8-bit multipliers and 32-bit multipliers.

[0026] When synthesized using the 28nm process library and the constraints are set to 1GHz, the area and power consumption are shown in Table 2.

[0027] Table 2 Comprehensive area and power consumption results of different types of computing units

[0028]

[0029] Since the multiplication and addition module has a long delay, when using combinational logic circuits and meeting the 1GHz timing requirement, the area overhead will be greater than that of the operation module implemented by pipelining. Here, the pipelining is performed by DC automatic retiming, which can optimize a certain area while meeting the timing. As can be seen from Table 2, the mixed-precision operation unit proposed in the present invention, when implemented by a combinational circuit, supports a variety of operations and mixed-precision operation modes at a 22% increase in area overhead compared to the basic 32-bit multiplication and addition module, and reduces power consumption by 5%. At the same time, compared with the non-optimized operation unit that simply implements the same function, the area is saved by 42% and the power consumption is saved by 46.6%. When implemented by a sequential logic circuit, compared with the basic 32-bit multiplication and addition module, the area overhead does not increase, and the power consumption overhead is reduced by 17.3%. At the same time, compared with the non-optimized operation unit that simply implements the same function, the area is saved by 49% and the power consumption is saved by 48.5%.

[0030] The operation module is integrated into a coarse-grained reconfigurable array. The overall architecture adopts the method of pre-fetching data and running in parallel. The task division is based on the size of the on-chip cache to ensure that each task is performed under full hit conditions. The on-chip cache is 128KB of 16 banks, so a task uses a maximum of 64KB of space. Here, the typical application Yolov3-tiny neural network is selected for mapping. The network contains 13 layers of convolution and 6 layers of pooling. It runs in two modes: ordinary 32-bit and quantized 8-bit low-precision. The number of clock cycles required for different layers of convolution and pooling is as follows: Figure 4 and Figure 5 As shown in the figure, for convolution, the data is packed when mapping 8-bit operations, and four groups of operations are performed in parallel. It can be seen that the operation time of most layers with low precision is about one-fourth of that of 32-bit operations, and the first task prefetch time cannot cover it up, so the performance improvement is not obvious.

[0031] For the pooling layer, the performance advantage is that due to the data splicing operation, the number of memory accesses will be reduced, bank conflicts will be reduced, and secondly, the number of tasks will be reduced after the overall splicing, which can reduce the overhead of switching tasks and configuring arrays. This is closely related to the specific task division. At the same time, the number of data write-backs will be reduced to one-fourth of the original. Overall, using low-precision operation mode, the entire application running time accounts for 26.5% of the normal mode, which can achieve nearly four times the performance improvement.

[0032] Compared with the prior art, the present invention has the following obvious substantial features and significant advantages:

[0033] In a data flow-driven coarse-grained reconfigurable system, under the constraint of unchanged data bandwidth, a new implementation method to support mixed-precision operations is proposed. By utilizing the structure of the basic multiplication unit compression tree, high-bitwidth multiplication operations can be supported while locally implementing the accumulation operations of multiple groups of low-precision multiplications, thus avoiding precision loss. In typical mixed-precision applications such as neural networks, the computing throughput is greatly improved, the number of data transfers is reduced, and the overall performance is improved.

[0034] The concept, specific structure and technical effects of the present invention will be further described below in conjunction with the accompanying drawings to fully understand the purpose, characteristics and effects of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 This is the schematic diagram of the Fission multiplier;

[0036] Figure 2 This is the schematic diagram of the Fussion multiplier;

[0037] Figure 3 This is a partial product diagram of 8-bit multiplication and accumulation;

[0038] Figure 4 It is the clock cycle of each convolutional layer of Yolov3-tiny;

[0039] Figure 5 It is the clock cycle of each pooling layer of Yolov3-tiny;

[0040] Figure 6 It is the overall architecture diagram of the coarse-grained reconfigurable array;

[0041] Figure 7 It is a simplified diagram of the processing unit structure;

[0042] Figure 8 It is a convolution diagram;

[0043] Fig. 9 It is the mapping flow graph of the convolution operation;

[0044] Fig.10 It is the mapping of convolution post-processing (pooling, Relu, quantization, splicing). DETAILED DESCRIPTION

[0045] The following describes several preferred embodiments of the present invention with reference to the drawings in the specification, so that the technical content is clearer and easier to understand. The present invention can be embodied in many different forms of embodiments, and the protection scope of the present invention is not limited to the embodiments mentioned in the text.

[0046] In the drawings, components with the same structure are indicated by the same numerical reference numerals, and components with similar structures or functions are indicated by similar numerical reference numerals. The size and thickness of each component shown in the drawings are arbitrarily shown, and the present invention does not limit the size and thickness of each component. In order to make the illustration clearer, the thickness of the components is appropriately exaggerated in some places in the drawings.

[0047] The present invention belongs to the field of arithmetic unit design, and relates to a method for implementing mixed-precision arithmetic in a coarse-grained reconfigurable array driven by a data stream. The invention is a mixed-precision arithmetic unit design supporting a coarse-grained reconfigurable array for low-precision neural network applications.

[0048] A mixed-precision operation unit for use in a data stream-driven reconfigurable array comprises building a novel mixed-precision operation unit based on a fission multiplier structure, supporting a variety of operation modes and mixed-precision multiplication and accumulation operations, and being suitable for a coarse-grained reconfigurable array driven by a data stream; integrating the unit into a processing unit of the array, and configuring and adjusting the application mapped on the reconfigurable array, so that the mixed-precision operation mode can improve performance while solving the problem of low resource utilization in a low-precision mode of a fission multiplier and the problem of precision loss caused by bit width limitation.

[0049] Construct a new mixed-precision operation unit based on the fission multiplier structure, including: mainly multiplication and addition operations, reusing resources to realize signed / unsigned addition, subtraction, multiplication and other various operation modes, high-bitwidth and high-precision multiplication operations to perform Booth encoding on partial products, and low-bitwidth multiplication directly reuses the compressed tree resources in the high-bitwidth multiplier structure to realize parallel multiplication and accumulation operations of multiple groups of low-precision data.

[0050] The coarse-grained reconfigurable array for data flow driving includes: integrating mixed-precision arithmetic units into the processing units of the coarse-grained reconfigurable array, and parsing the execution mode of the arithmetic units from the configuration registers of the PEs by statically configuring the PEs. At the same time, the processing units also need to add data splicing and packaging functions for low-precision operations to facilitate further processing of output data.

[0051] Constructing a new mixed-precision operation unit based on a fission multiplier structure, including: when using the mixed-precision operation mode, the operation unit is equivalent to implementing multiple multiplications and additions in one operation. Compared with directly using the fission multiplier, it improves resource utilization, improves the operation throughput, reduces data storage and transportation overhead, and avoids the accuracy loss caused by bandwidth limitations.

[0052] A coarse-grained reconfigurable array driven by data streams includes: when mapping specific applications on a data stream-driven reconfigurable array, utilizing the characteristics of a mixed-precision arithmetic unit, selecting appropriate dimensions to pack low-precision data for operation, and all intermediate data are high-bit width. After all data are calculated, they are quantized into low-bit width data and written back for additional splicing operations, and then used as input for the next task. Tasks with data dependencies are allocated on the array as continuously as possible to reduce the writing back of intermediate data. This not only makes full use of bandwidth without losing precision, reduces the number of data accesses, and improves computing throughput, but also reduces the number of PEs required to complete tasks, improving overall resource utilization.

[0053] Figure 6 It is the overall architecture diagram of the coarse-grained reconfigurable array; Figure 7 It is a simplified diagram of the processing unit structure.

[0054] The mixed precision computing unit proposed in the present invention can support mixed precision computing in multiple modes. It is applied to a reconfigurable array driven by a data stream and cooperates with a certain application mapping method to achieve a significant increase in throughput while avoiding precision loss. Taking the application of neural network reasoning as an example, its main operations are convolution, ReLu, pooling and other operations. The main operation of convolution is that the weight matrix slides on the image matrix, multiplies and accumulates the corresponding image data and weights, and the results of the corresponding positions of multiple input channels continue to be accumulated. The weight data of different convolution kernels corresponding to multiple output channels are repeated. The same operation is finally obtained to obtain the output of the convolution layer of the corresponding multiple output channels.

[0055] Take 3*3 convolution as an example, Figure 8 Since the input channels need to be accumulated in the end, they are packed according to the input channels in the low-precision operation mode, and four 8-bit data are spliced ​​into 32-bit data as input data for operation. While fully utilizing the bandwidth, the multiplication and accumulation operation mode of the mixed-precision operation unit can be used for operation, which is equivalent to completing four 8-bit multiplications, two 8-bit additions and one 16-bit addition in one operation, and outputting 32-bit data without precision loss.

[0056] Fig. 9It is the main calculation part of the mapping flow graph of low-precision convolution. It is implemented in the form of a basic systolic array. It saves partial products on-chip and updates input data and weights to minimize the write-back and read operations of partial products. There are three LSE units to fetch image data and nine LSEs to fetch weight data. For each convolution kernel, there are nine PEs for multiplication and accumulation. The first column of PE performs multiplication operations, multiplies the corresponding four groups of 8-bit input images and weights, and accumulates them into 32-bit data. The last two columns perform multiplication and accumulation operations, multiply and accumulate the corresponding four groups of data, and accumulate the calculation results of the first-level PE at the same time. The final accumulated results of the three rows of PE are accumulated again, and the partial products calculated by other channels are added. Three additional PEs are required to perform 32-bit addition operations to finally obtain the partial products, which are stored back to the memory using LSE.

[0057] After the convolutional layer operation is completed, the output data needs to be pooled, ReLU, quantized, etc. Fig.10 As shown, this is no different from normal operation in low-precision mode, both of which operate on 32-bit data. The difference is that additional splicing operations are required to splice the quantized data into the next set of required input forms. First, quantize the 32-bit data into 8-bit data, and then use PE to implement the splicing function. Pack the data according to the output channel of this layer, 8 bits into 16 bits, and 16 into 32 bits, as the input data of the next layer. When mapping the entire neural network, it is divided into blocks according to on-chip storage resources, loops are expanded according to computing resources, and pre-fetching data and task parallelism are adopted. At the same time, the movement of data back and forth between local memory and main memory is minimized to maximize the overall application performance.

[0058] The preferred specific embodiments of the present invention are described in detail above. It should be understood that ordinary technicians in the field can make many modifications and changes based on the concept of the present invention without creative work. Therefore, all technical solutions that can be obtained by technicians in the technical field based on the concept of the present invention through logical analysis, reasoning or limited experiments on the basis of the prior art should be within the scope of protection determined by the claims.

Claims

1. A mixed precision computing device for a data stream driven reconfigurable array, characterized in that: Build a mixed-precision arithmetic unit based on the fission multiplier structure, support multiple operation modes and mixed-precision multiplication and accumulation operations, integrate it into the processing unit of the coarse-grained reconfigurable array driven by data flow, and configure and adjust the applications mapped on the reconfigurable array; The mixed-precision arithmetic unit is integrated into the processing unit of the coarse-grained reconfigurable array. The execution mode of the arithmetic unit is parsed from the configuration register of the processing unit by statically configuring the processing unit. At the same time, the processing unit adds a data splicing and packaging function for low-precision operations to facilitate further processing of the output data. When mapping specific applications on a coarse-grained reconfigurable array driven by data flow, the characteristics of the mixed-precision arithmetic unit are utilized to select appropriate dimensions to pack low-precision data for operation. The intermediate data are all high-bit width. After all the data are calculated, they are quantized into low-bit width data and written back after additional splicing operations, and then used as input for the next task. Tasks with data dependencies are continuously allocated on the array to reduce the write-back of intermediate data.

2. The mixed precision computing device for use in a data stream driven reconfigurable array as claimed in claim 1, characterized in that: The mixed-precision operation unit based on the fission multiplier structure mainly performs multiplication and addition operations, and reuses resources to realize signed / unsigned addition, subtraction, and multiplication operation modes.

3. The mixed precision computing device for use in a data stream driven reconfigurable array as claimed in claim 1, characterized in that: The mixed precision operation unit based on the fission multiplier structure performs Booth encoding on partial products in high-bit-width and high-precision multiplication operations.

4. The mixed precision computing device for use in a data stream driven reconfigurable array as claimed in claim 1, characterized in that: In the mixed-precision operation unit based on the fission multiplier structure, low-bit-width multiplication directly reuses the compression tree resources in the high-bit-width multiplier structure to implement parallel multiplication and accumulation operations of multiple groups of low-precision data.

5. The mixed precision computing device for use in a data stream driven reconfigurable array as claimed in claim 1, characterized in that: The mixed-precision operation unit based on the fission multiplier structure implements multiple multiplications and additions in one operation when the mixed-precision operation mode is adopted.

6. The mixed precision computing device for use in a data stream driven reconfigurable array as claimed in claim 1, characterized in that: Implemented in Verilog.

7. The mixed precision computing device for use in a data stream driven reconfigurable array as claimed in claim 1, characterized in that: Integrated in the CGRA system.

8. The mixed precision computing device for use in a data stream driven reconfigurable array as claimed in claim 1, characterized in that: Application to neural networks.

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