Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same, the method comprising: providing a substrate for forming a first-type doped transistor, comprising a plurality of discrete active regions and an isolation region between the active regions; forming a polysilicon gate located in the active region and the isolation region on the substrate; removing the polysilicon gate located in the isolation region, and forming an opening in the polysilicon gate; filling a metal gate in the opening, the metal gate comprising a work function layer located at the bottom of the opening, the material of the work function layer comprising a second-type work function metal, the second type being different from the first type. The embodiments of the present invention are conducive to improving the problem of leakage current and enhancing the matching degree of the device.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] As the characteristic size of MOS devices continues to shrink, the problem of misalignment between the aluminum gate and the source and drain diffusion regions becomes more and more serious. The overlapping design of source, drain and gate leads to increasingly serious parasitic capacitance between the source, drain and gate. The semiconductor industry uses polysilicon gate instead of aluminum gate.

[0003] Polysilicon gate has three advantages: the first advantage is that polysilicon is not only compatible with silicon technology, but also can withstand high temperature annealing, which is a requirement for ion implantation; the second advantage is that the polysilicon gate is formed before the source and drain ion implantation. When the source and drain ions are implanted, the polysilicon gate can be used as a shielding layer, so the ions will only be implanted on both sides of the polysilicon gate, so that the source and drain diffusion regions are self-aligned with the polysilicon gate; the third advantage is that the work function can be changed by doping N-type and P-type impurity ions, thereby adjusting the threshold voltage of the device. Because the threshold voltage of MOS devices is determined by the difference in the work function of the substrate material and the gate material, polysilicon solves the problem of adjusting the threshold voltage of NMOS and PMOS in CMOS technology. In addition, polysilicon gates are also widely used in high-voltage devices or medium-voltage devices. Summary of the invention

[0004] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the leakage current problem and enhance the matching degree of the device.

[0005] To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate for forming a first-type doped transistor, the substrate comprising a plurality of discrete active areas and an isolation area between the active areas; forming a polysilicon gate located in the active area and the isolation area on the substrate; removing the polysilicon gate located in the isolation area and forming an opening in the polysilicon gate; filling a metal gate in the opening, the metal gate comprising a work function layer located at the bottom of the opening, the material of the work function layer comprising a second-type work function metal, and the second type is different from the first type.

[0006] Correspondingly, an embodiment of the present invention also provides a semiconductor structure, including: a substrate for forming a first-type doped transistor, the substrate including a plurality of discrete active areas and an isolation area between the active areas; a polysilicon gate located on the substrate of the active area; a metal gate located on the substrate of the isolation area along an extension direction of the polysilicon gate and in contact with a side wall of the polysilicon gate, the metal gate including a work function layer located at the bottom of the opening, the material of the work function layer including a second-type work function metal, the second type being different from the first type.

[0007] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0008] In the method for forming a semiconductor structure provided by an embodiment of the present invention, the substrate is used to form a first-type doped transistor; the polysilicon gate located in the isolation region is removed to form an opening, and a metal gate is filled in the opening, the metal gate includes a work function layer located at the bottom of the opening, the material of the work function layer includes a second-type work function metal, and the second type is different from the first type; the process of forming the opening includes the step of forming a mask layer by using a photolithography process, and in the photolithography process of forming the mask layer, even if there is an overlay offset or a size deviation problem along the extension direction of the polysilicon gate, resulting in the metal gate overlapping with the substrate of a part of the active area, because the material of the metal gate includes the second-type work function metal, when forming NMOS, the work function of the metal gate is higher than the work function of the polysilicon gate, and when forming PMOS, the work function of the metal gate is lower than the work function of the polysilicon gate, so that when the device is working, the difficulty of opening the channel below the metal gate increases, and the edge device (Edge device) formed by the metal gate and the substrate below it The threshold voltage of the transistor is higher than the threshold voltage of the device formed by the polysilicon gate and the substrate thereunder, so that the edge device formed by the metal gate and the substrate will not be turned on prematurely, which is beneficial to improve the leakage current problem, especially the leakage current problem of the medium voltage device.

[0009] Moreover, since the channel located under the metal gate will not be opened in advance, when the device is working, the opening or closing of the channel is mainly controlled by the polysilicon gate located in the active area. Even if the position of the opening is offset or the size of the opening is deviated along the extension direction of the polysilicon gate, resulting in etching of part of the polysilicon gate located in the active area, the offset or deviation is much smaller than the width of the channel, and has little effect on the electrical performance of the device, which is beneficial to improving the matching degree of the device, especially the matching degree of medium voltage devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figures 1 to 11 It is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure;

[0011] Figures 12 to 26 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0012] As can be seen from the background technology, polysilicon gates are widely used in high-voltage devices or medium-voltage devices. However, the devices currently formed still have the problem of poor performance. Taking the formation of medium-voltage devices as an example, the reasons for the poor performance of the devices are analyzed in combination with a method for forming a semiconductor structure.

[0013] Figures 1 to 11 The present invention is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure.

[0014] refer to Figures 1 to 3 , Figure 1 is a top view, Figure 2 for Figure 1 A partial enlarged view of Figure 3 for Figure 2 In the cross-sectional view at position AA, a substrate 1 is provided, including a plurality of discrete active regions I and isolation regions II located between the active regions I; a polysilicon gate 2 located in the active regions I and the isolation regions II is formed on the substrate 1 .

[0015] refer to Figure 4 and Figure 5 , Figure 4 is a top view, Figure 5 for Figure 4 In the cross-sectional view at position AA, an interlayer dielectric layer 3 is formed on the substrate 1 at the side of the polysilicon gate 2 .

[0016] refer to Figures 6 to 8 , respectively, schematically show the top view, removing the polysilicon gate 2 located in the isolation region II, and forming an opening 4 surrounded by the interlayer dielectric layer 3 and the polysilicon gate 2. The step of removing the polysilicon gate 2 located in the isolation region II includes: Figure 6 As shown, a mask layer 5 is formed on the polysilicon gate 2, and the mask layer 5 has a mask opening 6 that exposes the polysilicon gate 2 of the isolation region II; Figure 7 As shown, the polysilicon gate 2 is etched using the mask layer 5 as a mask; Figure 8 As shown, the mask layer 5 is removed.

[0017] refer to Fig. 9 , a metal gate 7 is filled in the opening 4 .

[0018] The above formation method is used to form a medium voltage device as an example. In the above formation method, the polysilicon gate 2 located in the isolation region II is removed to form an opening 4, and a metal gate 7 is formed in the opening 4, so that a gate contact hole plug in contact with the metal gate 7 can be formed on the metal gate 7 later, and the materials of the gate contact hole plug and the metal gate 7 both include metal materials, and the contact resistance between the gate contact hole plug and the metal gate 7 is small and the contact performance is high. By forming the metal gate 7 on the isolation region II, the polysilicon gate 2 can be electrically connected to an external circuit or other interconnection structure through the metal gate 7.

[0019] The process of forming the mask layer 5 includes photolithography processes such as exposure and development. When there is an alignment offset in the photolithography process or a deviation in the opening size of the mask opening 6, for example, Fig.10 As shown, when the photolithography process is carried out along the extension direction of the polysilicon gate 2 (such as Fig.10 When the alignment is offset or the opening size of the mask opening 6 is deviated, part of the polysilicon gate 2 of the active area I will be removed. Fig.11 As shown, when the metal gate 7 is formed, the metal gate 7 is also easily formed on a part of the substrate 1 of the active area I. When forming NMOS, the work function of the metal gate 7 is lower than the work function of the polysilicon gate 2, and when forming PMOS, the work function of the metal gate 7 is higher than the work function of the polysilicon gate 2, which easily leads to a reduction in the threshold voltage of the edge device (Edge Transistor) formed by the metal gate 7 and the substrate 1 located thereunder. When the device is working, the channel located below the metal gate 7 is easily turned on in advance, which is easy to generate leakage current, and it is also easy to cause the turn-on voltage of the area of ​​the substrate 1 of the active area I covered by the metal gate 7 and the polysilicon gate 2 to be different, which easily worsens the mismatch of the device and leads to poor performance of the device.

[0020] In order to solve the technical problem, in the method for forming a semiconductor structure provided by an embodiment of the present invention, by making the metal gate include a work function layer located at the bottom of the opening, the material of the work function layer includes a second type work function metal, during the photolithography process of forming the mask layer, even if there is an overlay offset or a size deviation problem along the extension direction of the polysilicon gate, resulting in the metal gate overlapping with the substrate of a part of the active area, since the material of the metal gate includes the second type work function metal, when forming NMOS, the work function of the metal gate is higher than the work function of the polysilicon gate in the active area, and when forming PMOS, the work function of the metal gate is lower than the work function of the polysilicon gate in the active area, so that when the device is working, the difficulty of opening the channel below the metal gate is increased, and the metal gate and the substrate below it are formed. The threshold voltage of the edge device formed by the metal gate and the substrate is higher than the threshold voltage of the device formed by the polysilicon gate and the substrate thereunder, so that when the device is working, the edge device formed by the metal gate and the substrate will not be turned on prematurely, which is beneficial to improving the leakage current problem, especially the leakage current problem of the medium voltage device; moreover, since the channel located under the metal gate will not be turned on prematurely, when the device is working, the opening or closing of the channel is mainly controlled by the polysilicon gate located in the active area, even if the position of the opening is offset or the size of the opening is deviated along the extension direction of the polysilicon gate, resulting in the etching of part of the polysilicon gate, the offset or deviation is much smaller than the width of the channel, which has little effect on the electrical performance of the device and is beneficial to improving the matching degree of the device, especially the matching degree of the medium voltage device.

[0021] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present invention more obvious and understandable, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0022] Figures 12 to 26 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.

[0023] refer to Figure 12 to Figure 14 , Fig.12 is a top view, Fig.13 for Fig.12 A partial enlarged view of Fig.14 for Fig.13 In the cross-sectional view at position aa, a substrate (not shown) is provided for forming a first-type doped transistor. The substrate includes a plurality of discrete active regions I and isolation regions II located between the active regions I.

[0024] The substrate is used to provide a platform for subsequent process steps. The substrate is used to form a first-type doped transistor. The first type refers to the doping type of the transistor. Specifically, the doping type of the transistor refers to the doping type of the source and drain doping regions in the transistor. As an example, the first-type doped transistor is an NMOS transistor. In other embodiments, the first-type doped transistor can also be a PMOS transistor.

[0025] In this embodiment, the substrate is used to form a medium voltage device (Medium Voltage Device) or a high voltage device (High Voltage Device), for example: a medium voltage device with an operating voltage of 3V to 10V, or a high voltage device with an operating voltage greater than 10V.

[0026] In this embodiment, the base includes a substrate 100 and an isolation structure 105 located in the isolation region II of the substrate 100. In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium.

[0027] Specifically, in this embodiment, a trench (not shown) is formed in the substrate 100 of the isolation region II. The step of forming the isolation structure 105 includes: filling the trench with an isolation material to form the isolation structure 105.

[0028] In this embodiment, trenches are formed by etching the substrate 100, thereby defining an active area (AA) I and an isolation area II on the substrate. Specifically, a plurality of isolated trenches are formed in the substrate, and the substrate 100 isolated by the trenches is used as the active area.

[0029] In this embodiment, the isolation structure 105 is also used to isolate adjacent devices. In this embodiment, the material of the isolation structure 105 is silicon oxide. In other embodiments, the material of the isolation structure can also be other dielectric materials such as silicon nitride or silicon oxynitride.

[0030] In this embodiment, after forming the trench and before filling the trench with an isolation material, the method for forming a semiconductor structure further includes: forming a liner layer 104 on the bottom surface and sidewalls of the trench and the top surface of the substrate 100 .

[0031] The liner layer 104 is used to improve the interface quality between the bottom surface and the sidewall of the trench and the top surface of the substrate 100, thereby improving the formation quality of the isolation structure 105. As an example, the material of the liner layer 104 is silicon oxide.

[0032] Continue to refer Figure 12 to Figure 14A polysilicon gate (PolyGate) 110 is formed on the substrate and located in the active region I and the isolation region II. In this embodiment, the polysilicon gate 110 is used as a device gate. When the device is working, the polysilicon gate 110 is used to control the opening and closing of the conductive channel.

[0033] In this embodiment, the material of the polysilicon gate 110 includes polysilicon.

[0034] In the present embodiment, in the step of forming the polysilicon gate 110, the forming method further includes: forming a stacked structure (not shown) between the polysilicon gate 110 and the substrate, including a gate dielectric layer 115 and a gate dielectric barrier layer 111 located on the gate dielectric layer 115. In the present embodiment, the gate dielectric layer 115 is located on the substrate where the isolation structure 105 is exposed.

[0035] The gate dielectric layer 115 is used to isolate the polysilicon gate 110 from the substrate. Moreover, after the polysilicon gate 110 located in the isolation region II is removed to form an opening and a metal gate is formed in the opening, the gate dielectric layer 115 is also used to achieve electrical isolation between the metal gate and the substrate.

[0036] The gate dielectric layer 115 is a gate oxide layer, or the gate dielectric layer 115 is a high-k gate dielectric layer, or the gate dielectric layer 115 includes a gate oxide layer and a high-k gate dielectric layer on the gate dielectric layer 115 .

[0037] The material of the gate oxide layer includes silicon oxide or silicon oxynitride. The material of the high-k gate dielectric layer includes a high-k dielectric material, which refers to a dielectric material having a relative dielectric constant greater than that of silicon oxide, such as HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or Al2O3.

[0038] After the metal gate is subsequently formed, the metal gate is located on the gate dielectric barrier layer 111. The gate dielectric barrier layer 111 is used to reduce the diffusion of the metal gate material into the gate dielectric layer 115 in the subsequent high-temperature annealing process. The gate dielectric barrier layer 111 also regulates the work function of the polysilicon gate 110 of the active area I.

[0039] In this embodiment, the material of the gate dielectric barrier layer 111 includes TiN. TiN not only has a high barrier capability, thereby making the effect of reducing the diffusion of the metal gate material into the gate dielectric layer 115 in the high temperature annealing process more significant, but also TiN is a work function metal commonly used in semiconductor processes, and therefore can also adjust the work function of the polysilicon gate 110 of the active region I, thereby adjusting the turn-on voltage of the channel below the polysilicon gate 110 of the active region I.

[0040] In this embodiment, an isolation structure 105 is formed in the substrate 100 in the isolation region II. Therefore, the polysilicon gate 110 is located on the substrate 100 and the isolation structure 105.

[0041] As an example, the steps of forming the polysilicon gate 110, the gate dielectric layer 115 and the gate dielectric barrier layer 111 include: forming a gate dielectric material layer (not shown) on the substrate, a gate dielectric barrier material layer (not shown) on the gate dielectric material layer, and a gate material layer (not shown) on the gate dielectric barrier material layer; forming a gate mask layer 125 on the gate material layer; using the gate mask layer 125 as a mask, patterning the gate material layer, the gate dielectric barrier material layer and the gate dielectric material layer, the remaining gate material layer is used as the polysilicon gate 110, the remaining gate dielectric barrier material layer is used as the gate dielectric barrier layer 111, and the remaining gate dielectric material layer is used as the gate dielectric layer 115. Therefore, a gate mask layer 125 is also formed on the top of the polysilicon gate 110.

[0042] The gate mask layer 125 is used as an etching mask for forming the polysilicon gate 110. In this embodiment, the material of the gate mask layer 125 is silicon nitride.

[0043] In this embodiment, after forming the polysilicon gate 110, the forming method further includes: forming a sidewall 130 on the sidewall of the polysilicon gate 110. The sidewall 130 is used to protect the sidewall of the polysilicon gate 110 and is also used to define the formation area of ​​the subsequent source and drain doping region. The material of the sidewall 130 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride oxide, silicon nitride oxide, boron nitride and boron carbonitride, and the sidewall 130 is a single-layer structure or a stacked structure.

[0044] As an example, the sidewall spacer 130 is a stacked structure, and the sidewall spacer 130 includes a first sidewall spacer (not shown) located on the sidewall of the polysilicon gate 110 and a second sidewall spacer (not shown) located on the sidewall of the first sidewall spacer. The material of the first sidewall spacer is silicon oxide, and the material of the second sidewall spacer is silicon nitride.

[0045] In this embodiment, for the convenience of illustration and description, only the spacer 130 and the gate mask layer 125 are illustrated in the cross-sectional view.

[0046] The subsequent steps also include: removing the polysilicon gate 110 located in the isolation region II and forming an opening in the polysilicon gate 110. Figure 15 to Figure 16 , Fig.15 is a top view, Fig.16 for Fig.15In the cross-sectional view at the position aa, in this embodiment, after forming the polysilicon gate 110 and before forming the opening, the forming method further includes: forming source and drain doped regions (not shown) in the substrate of the active region I on both sides of the polysilicon gate 110; and forming an interlayer dielectric layer 140 covering the source and drain doped regions on the substrate at the side of the polysilicon gate 110. When the device is working, the source and drain doped regions are used to provide carrier sources for the channel region.

[0047] Specifically, source and drain doping regions are formed in the substrate 100 on both sides of the polysilicon gate 110 .

[0048] When forming an NMOS transistor, the source and drain doping regions are doped with N-type ions, including P ions, As ions or Sb ions; when forming a PMOS transistor, the source and drain doping regions are doped with P-type ions, including B ions, Ga ions or In ions.

[0049] The interlayer dielectric layer 140 is used to isolate adjacent devices. The material of the interlayer dielectric layer 140 is an insulating material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon carbon nitride oxide. In this embodiment, the material of the interlayer dielectric layer 140 is silicon oxide.

[0050] As an example, the steps of forming the interlayer dielectric layer 140 include: forming an initial dielectric layer (not shown) on the substrate, the initial dielectric layer covering the gate mask layer 125; using a planarization process to remove the initial dielectric layer and the gate mask layer 125 above the top surface of the polysilicon gate 110, and the remaining initial dielectric layer serves as the interlayer dielectric layer 140.

[0051] In this embodiment, during the process of forming the interlayer dielectric layer 140, a planarization process is used to remove the initial dielectric layer and the gate mask layer 125 that are higher than the top surface of the polysilicon gate 110, thereby integrating the steps of forming the interlayer dielectric layer 140 and removing the gate mask layer 125, which is beneficial to improving process compatibility and process integration, and also improving the top surface height consistency of the interlayer dielectric layer 140 and the polysilicon gate 110.

[0052] The gate mask layer 125 is removed to expose the top surface of the polysilicon gate 110 , in preparation for the subsequent removal of the polysilicon gate 110 in the isolation region II.

[0053] In this embodiment, the process of forming the initial dielectric layer includes a deposition process such as a chemical vapor deposition process.

[0054] In this embodiment, a planarization process (e.g., chemical mechanical polishing process) is used to remove the initial dielectric layer and the gate mask layer 125 above the top surface of the polysilicon gate 110. The chemical mechanical polishing process is a global surface planarization technology, which is beneficial to improving the flatness of the top surface of the interlayer dielectric layer 140, thereby providing a flat surface for subsequent processes.

[0055] It should also be noted that, in this embodiment, the formation method further includes: after forming the source and drain doping regions and before forming the interlayer dielectric layer 140 , forming a source and drain silicide layer (not shown) on the top surface of the source and drain doping regions.

[0056] The source-drain silicide layer (not shown) is used to improve the adhesion between the source-drain doped region and the subsequent source-drain contact hole plug, and to reduce the contact resistance between the source-drain doped region and the source-drain contact hole plug, thereby improving the contact performance between the source-drain doped region and the source-drain contact hole plug.

[0057] The interlayer dielectric layer 140 covers the source and drain silicide layers accordingly.

[0058] In this embodiment, the material of the source / drain silicide layer includes TiSi, NiSi, CoSi or NiPtSi.

[0059] In this embodiment, a self-aligned silicide process is used to form the source and drain silicide layer. As an example, the steps of forming the source and drain silicide layer include: forming a metal layer (not shown) on the source and drain doped regions, the metal layer is also located on the isolation structure 105, the sidewalls of the sidewall 130, and the top and sidewalls of the gate mask layer 125; performing annealing to convert the metal layer in contact with the source and drain doped regions and a portion of the thickness of the source and drain doped regions into the source and drain silicide layer.

[0060] Among them, since a gate mask layer 125 is also formed on the top of the polysilicon gate 110, in the step of forming the metal layer, the metal layer will not be formed on the top of the polysilicon gate 110, and thus will not contact the top of the polysilicon gate 110. Accordingly, during the annealing process, a metal silicide layer will not be formed on the top surface of the polysilicon gate 110.

[0061] refer to Figures 17 to 22 , the polysilicon gate 110 located in the isolation region II is removed, and an opening 10 is formed in the polysilicon gate 110. The opening 10 is used to provide space for forming a metal gate. The opening 10 is located in the isolation region II, so that the metal gate formed subsequently is located in the isolation region II, and the polysilicon gate 110 is electrically connected to the external circuit through the metal gate. The gate contact hole plug is connected to the polysilicon gate 110 located in the active region I through the metal gate, which can reduce the contact resistance.

[0062] In this embodiment, in the step of forming the opening 10 , the opening 10 is surrounded by the remaining polysilicon gate 110 , the sidewall spacer 130 , and the interlayer dielectric layer 140 .

[0063] In this embodiment, the gate dielectric barrier layer 111 is used as a stop layer to remove the polysilicon gate 110 located in the isolation region II. Therefore, in the step of removing the polysilicon gate 110 located in the isolation region II to form the opening 10, the gate dielectric barrier layer 111 is exposed at the bottom of the opening 10.

[0064] As an example, the step of removing the polysilicon gate 110 located in the isolation region II includes:

[0065] like Fig.17 and Fig.18 As shown, Fig.17 is a top view, Fig.18 for Fig.17 In the cross-sectional view at position aa, a mask layer 145 covering the polysilicon gate 110 of the active region I is formed on the substrate, and a mask opening 20 exposing the polysilicon gate 110 of the isolation region II is formed in the mask layer 145 .

[0066] The mask layer 145 is used as a mask for etching the polysilicon gate 110. In this embodiment, the material of the mask layer 145 includes photoresist. The mask layer 145 can be formed by photolithography processes such as exposure and development.

[0067] The mask opening 20 exposes the polysilicon gate 110 of the isolation region II. In this embodiment, the mask opening 20 also exposes a portion of the interlayer dielectric layer 140 of the isolation region II. Therefore, along the extension direction of the polysilicon gate 110 (eg Fig.17 In the Y direction, the size of the mask opening 20 is larger than the size of the subsequently formed opening, which is beneficial to increase the process window for forming the mask opening 20.

[0068] It should be noted that in the semiconductor field, alignment deviation or size deviation usually occurs during the photolithography process. Therefore, in the actual process, the mask opening 20 may also be offset along the extension direction of the polysilicon gate 110, and the mask opening 20 may also expose a portion of the polysilicon gate 110 located in the active area I.

[0069] like Fig.19 and Fig. 20 As shown, Fig.19 is a top view, Fig. 20 for Fig.19 In the cross-sectional view at position aa, the mask layer 145 is used as a mask to remove the polysilicon gate 110 below the mask opening 20 to form an opening 10 .

[0070] In this embodiment, an anisotropic dry etching process is used to remove the polysilicon gate 110 below the mask opening 20. The anisotropic dry etching process has the characteristic of anisotropic etching, which is beneficial to improving the controllability of the etching profile of the polysilicon gate 110 and correspondingly improving the profile morphology quality of the opening 10.

[0071] In this embodiment, the gate dielectric barrier layer 111 is used as a stop layer to remove the polysilicon gate 110 located in the isolation region II.

[0072] It should be noted that in the semiconductor field, when there is an alignment offset or size deviation during the photolithography process, the mask opening 20 will extend along the extension direction of the polysilicon gate 110 (ie Fig.19 The mask opening 20 is offset in the Y direction (in the Y direction), resulting in that the mask opening 20 exposes a portion of the polysilicon gate 110 located in the active area I. Accordingly, in the process of removing the polysilicon gate 110 below the mask opening 20, a portion of the polysilicon gate 110 in the active area I is also removed, and the opening 10 correspondingly exposes a portion of the gate dielectric barrier layer 111 in the active area I.

[0073] like Fig.21 and Fig. 22 As shown, Fig.21 is a top view, Fig. 22 for Fig.21 In the cross-sectional view at position aa, the mask layer 145 is removed. In this embodiment, the mask layer 145 is removed by an ashing process.

[0074] refer to Fig.23 and Fig.24 , Fig.23 is a top view, Fig.24 for Fig.23 In the cross-sectional view at position aa, a metal gate 150 is filled in the opening 10 . The metal gate 150 includes a work function layer 52 located at the bottom of the opening 10 . The material of the work function layer 52 includes a second type work function metal, which is different from the first type.

[0075] By forming the metal gate 150 in the opening 10, a gate contact hole plug in contact with the metal gate 150 can be formed on the metal gate 150 later. The gate contact hole plug and the metal gate 150 are made of metal materials. The contact resistance between the gate contact hole plug and the metal gate 150 is small and the contact performance is high. Furthermore, by forming the metal gate 150 on the isolation region II, the polysilicon gate 110 can be electrically connected to an external circuit or other interconnection structure through the metal gate 150. In this embodiment, the metal gate 150 is formed on the gate dielectric barrier layer 111.

[0076] In this embodiment, even along the extension direction of the polysilicon gate 110 (ie Fig.23The problem of overlay offset or size deviation occurs on the substrate of the active region 1 (as shown in the Y direction in FIG. 1 ), causing the metal gate 150 to overlap with the substrate of a portion of the active region 1 (as shown in FIG. 1 ). Fig.25 and Fig.26 As shown, since the metal gate 150 includes a work function layer 52 located at the bottom of the opening, the material of the work function layer 52 includes a second type work function metal, and the second type is different from the first type. When forming NMOS, the work function of the metal gate 150 is greater than the work function of the polysilicon gate 110 located in the active area I, and when forming PMOS, the work function of the metal gate 150 is lower than the work function of the polysilicon gate 110 in the active area I, so that when the device is working, the difficulty of opening the channel below the metal gate 150 increases, and the threshold voltage of the edge device (Edge Transistor) formed by the metal gate 150 and the substrate located thereunder is higher than the threshold voltage of the device formed by the polysilicon gate 110 and the substrate located thereunder, so that when the device is working, the edge device formed by the metal gate 150 and the substrate will not be opened prematurely, which is beneficial to improve the leakage current problem.

[0077] Moreover, since the channel located below the metal gate 150 will not be opened in advance, when the device is working, the opening or closing of the channel is mainly controlled by the polysilicon gate 110. Even if the position of the opening 10 is offset or the size of the opening 10 is deviated along the extension direction of the polysilicon gate 110, resulting in partial etching of the polysilicon gate 110 in the active area I, the offset or deviation is much smaller than the width of the channel, which has little effect on the electrical performance of the device, and is beneficial to improving the matching degree of the device.

[0078] Specifically, in this embodiment, when the device is working, the opening or closing of the channel is mainly controlled by the gate dielectric barrier layer 111 of the active region I.

[0079] When the first type doped transistor is an N-type transistor, the second type work function metal is a P-type work function metal. When an N-type transistor is formed, the material of the metal gate 150 includes a P-type work function metal, thereby increasing the work function of the metal gate 150, thereby increasing the threshold voltage of the channel under the metal gate 150, so that the channel of the edge device is controlled by the polysilicon gate 110 of the active region I.

[0080] Specifically, in this embodiment, when the first-type doped transistor is an N-type transistor, in the process of forming the metal gate 150, the work function of the second-type work function metal is greater than the work function of the gate dielectric barrier layer 111, so that the work function of the metal gate 150 is greater than the work function of the polysilicon gate 110 located in the active area I, and further when the device is working, the opening or closing of the channel is mainly controlled by the gate dielectric barrier layer 111 in the active area I.

[0081] In this embodiment, the work function of the P-type work function metal is 4.5 eV to 5.5 eV. The material of the P-type work function metal includes one or more of TiN, Ta, TaN, TaSiN and TiSiN.

[0082] When the first type doped transistor is a P type transistor, the second type work function metal is an N type work function metal. When forming a P type transistor, by making the material of the metal gate 150 include an N type work function metal, the work function of the metal gate 150 is reduced, thereby increasing the threshold voltage of the channel under the metal gate 150, so that the channel of the edge device is controlled by the polysilicon gate 110 of the active region I.

[0083] Specifically, in this embodiment, when the first-type doped transistor is a P-type transistor, in the process of forming the metal gate 150, the work function of the second-type work function metal is smaller than the work function of the gate dielectric barrier layer 111, thereby making the work function of the metal gate 150 lower than the work function of the polysilicon gate 110 in the active area I, thereby making the opening or closing of the channel mainly controlled by the gate dielectric barrier layer 111 in the active area I when the device is working.

[0084] In this embodiment, the work function of the N-type work function metal is 3.9 eV to 4.3 eV. The material of the N-type work function metal includes one or more of TiAl, TaAlN, TiAlN, MoN, TaCN and AlN.

[0085] In this embodiment, the metal gate 150 further includes a gate electrode layer 53 located on the work function layer 52 and filling the opening 10. The work function layer 52 is used to adjust the work function of the metal gate 150 to increase the threshold voltage of the edge device formed by the metal gate 150 and the substrate.

[0086] The gate electrode layer 53 is used as an electrode to electrically connect the metal gate 150 to an external circuit or other interconnection structure. In this embodiment, the material of the gate electrode layer 53 is Al. In other embodiments, the material of the gate electrode layer can also be W, Cu, Ag, Au, Pt, Ni or Ti.

[0087] In this embodiment, the steps of forming the metal gate 150 include: forming a work function film (not shown) on the side wall and bottom of the opening 10, and the work function film is also formed on the polysilicon gate 110 and the interlayer dielectric layer 140; forming a gate electrode film (not shown) filling the opening 10 on the work function film; removing the gate electrode film and the work function film above the top surface of the polysilicon gate 110 and the interlayer dielectric layer 140, and the remaining work function film is used as the work function layer 52, and the remaining gate electrode film is used as the gate electrode layer 53.

[0088] In this embodiment, the process of forming the work function film includes an atomic layer deposition process or a physical vapor deposition process. In this embodiment, the process of forming the gate electrode film includes one or more of a chemical vapor deposition process, a physical vapor deposition process and an electrochemical plating process.

[0089] In this embodiment, a planarization process is used to remove the gate electrode film and the work function film above the interlayer dielectric layer 140 and the top surface of the polysilicon gate 110. Specifically, the planarization process includes a chemical mechanical polishing process.

[0090] In this embodiment, after the metal gate 150 is formed, the forming method further includes: forming a gate contact hole plug (not shown) on the metal gate 150 and in contact with the metal gate 150 .

[0091] The gate contact plug contacts the metal gate 150 to electrically connect the metal gate 150 to an external circuit or interconnection structure, thereby electrically connecting the polysilicon gate 110 to an external circuit or other interconnection structure. The description of the gate contact plug is not repeated in this embodiment.

[0092] Accordingly, the present invention also provides a semiconductor structure. Fig.23 and Fig.24 , Fig.23 is a top view, Fig.24 for Fig.23 The cross-sectional view at position aa shows a schematic structural diagram of an embodiment of a semiconductor structure of the present invention.

[0093] The semiconductor structure includes: a substrate (not shown) for forming a first type doped transistor, the substrate including a plurality of discrete active regions I and an isolation region II between the active regions I; a polysilicon gate 110 located on the substrate of the active region I; a metal gate 150 extending along the extension direction of the polysilicon gate 110 (such as Fig.23 The metal gate 150 is located on the substrate of the isolation region II and contacts the sidewall of the polysilicon gate 110. The metal gate 150 includes a work function layer 52. The material of the work function layer 52 includes a second type work function metal, which is different from the first type.

[0094] In the embodiment of the present invention, the step of forming the metal gate 150 includes: removing the polysilicon gate 110 located in the isolation region II to form an opening, and filling the metal gate 150 in the opening. The process of forming the opening includes the step of forming a mask layer by using a photolithography process. By making the material of the work function layer 52 include the second type work function metal, during the photolithography process of forming the mask layer, even if there is an overlay offset or a size deviation along the extension direction of the polysilicon gate 110, resulting in the metal gate 150 overlapping with the substrate of a portion of the active area I, since the material of the metal gate 150 includes the second type work function metal, the second type is different from the first type, so that when forming NMOS, the work function of the metal gate 150 is higher than the work function of the polysilicon gate 110 of the active area I, and when forming PMOS, the work function of the metal gate 150 is lower than the work function of the polysilicon gate 110, so that when the device is working, the difficulty of opening the channel below the metal gate 150 increases, and the threshold voltage of the edge device formed by the metal gate 150 and the substrate below it is higher than the threshold voltage of the device formed by the polysilicon gate 110 and the substrate below it, so that the edge device formed by the metal gate 150 and the substrate will not be opened prematurely, which is conducive to improving the leakage current problem.

[0095] Moreover, since the channel under the metal gate 150 will not be opened in advance, when the device is working, the opening or closing of the channel is mainly controlled by the polysilicon gate 110. Even if the metal gate 150 overlaps with the substrate of the active area I along the extension direction of the polysilicon gate 110, the overlapping size is much smaller than the length or width of the channel, which has little effect on the electrical performance of the device and is also beneficial to improving the matching degree of the device.

[0096] The substrate is used to form a first-type doped transistor. The first type refers to the doping type of the transistor. Specifically, the doping type of the transistor refers to the doping type of the source and drain doping regions in the transistor. As an example, the first-type doped transistor is an NMOS transistor. In other embodiments, the first-type doped transistor can also be a PMOS transistor.

[0097] In this embodiment, the substrate is used to form a medium voltage device or a high voltage device, for example, a medium voltage device with an operating voltage of 3V to 10V, or a high voltage device with an operating voltage greater than 10V. In this embodiment, the substrate includes a substrate 100 and an isolation structure 105 located in the isolation region II of the substrate 100. In this embodiment, the substrate 100 is a silicon substrate.

[0098] The isolation structure 105 is used to define the shape and position of the active region I.

[0099] In this embodiment, the material of the isolation structure 105 is silicon oxide. In this embodiment, a groove (not shown) is also formed in the substrate 100. The isolation structure 105 is located in the groove.

[0100] In this embodiment, a plurality of isolated grooves are provided in the substrate, and the grooves are used to define an active area (AA) I and an isolation area II on the substrate, wherein the substrate 100 isolated by the grooves is used as the active area I, and the remaining area is used as the isolation area II.

[0101] In this embodiment, the semiconductor structure also includes: a liner layer 104, which is located between the sidewalls and bottom surface of the trench and the isolation structure 105. The liner layer 104 is also located on the top surface of the substrate exposed by the isolation structure 105, as well as between the polysilicon gate 110 and the substrate, and between the metal gate 150 and the substrate.

[0102] The process of forming the isolation structure 105 includes the step of etching the substrate to form a groove, and the liner layer 104 is used to improve the bottom surface and sidewalls of the groove, and the defects of the substrate surface, thereby improving the interface quality of the bottom surface and sidewalls of the groove and the top surface of the substrate, and further improving the formation quality of the isolation structure 105. As an example, the material of the liner layer 104 is silicon oxide.

[0103] When the device is working, the polysilicon gate 110 serves as a device gate to control the opening and closing of the conductive channel. In this embodiment, the polysilicon gate 110 is located on the substrate 100 and the isolation structure 105 .

[0104] In this embodiment, the material of the polysilicon gate 110 includes polysilicon.

[0105] In this embodiment, the semiconductor structure also includes: a stacked structure (not shown) located between the polysilicon gate 110 and the substrate, and between the metal gate 150 and the substrate, the stacked structure including a gate dielectric layer 115 and a gate dielectric barrier layer 111 located on the gate dielectric layer 115 .

[0106] The gate dielectric layer 115 is used to isolate the polysilicon gate 110 from the substrate and the metal gate 150 from the substrate. The gate dielectric layer 115 is a gate oxide layer, or the gate dielectric layer 115 is a high-k gate dielectric layer, or the gate dielectric layer 115 includes a gate oxide layer and a high-k gate dielectric layer on the gate dielectric layer 115.

[0107] The material of the gate oxide layer includes silicon oxide or silicon oxynitride. The material of the high-k gate dielectric layer includes a high-k dielectric material, which refers to a dielectric material having a relative dielectric constant greater than that of silicon oxide, such as HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or Al2O3.

[0108] The gate dielectric barrier layer 111 is used to reduce the diffusion of the material of the metal gate 150 into the gate dielectric layer 115 in the subsequent high temperature annealing process, and the gate dielectric barrier layer 111 can also adjust the work function of the polysilicon gate 110 and the substrate 100, thereby adjusting the threshold voltage of the polysilicon gate 110. Specifically, when the device is working, the opening or closing of the channel is mainly controlled by the gate dielectric barrier layer 111 of the active area I.

[0109] In this embodiment, the material of the gate dielectric barrier layer 111 includes TiN. TiN not only has a high barrier capability, thereby making the effect of reducing the diffusion of the material of the metal gate 150 into the gate dielectric layer 115 in the high temperature annealing process more significant, but also TiN is a work function metal commonly used in semiconductor processes, and therefore can also adjust the work function of the polysilicon gate 110 of the active region I, thereby adjusting the turn-on voltage of the channel below the polysilicon gate 110 of the active region I.

[0110] In this embodiment, the semiconductor structure further includes: a sidewall 130 located on the sidewalls of the polysilicon gate 110 and the metal gate 150. The sidewall 130 is used to protect the sidewalls of the polysilicon gate 110 and the metal gate 150, and is also used to define the formation area of ​​the source and drain doping regions.

[0111] In this embodiment, for the convenience of illustration and description, only the side wall 130 is illustrated in the cross-sectional view.

[0112] In this embodiment, the semiconductor structure also includes: source and drain doped regions (not shown), located in the substrate of the active region I on both sides of the polysilicon gate 110; and an interlayer dielectric layer 140, on the substrate on the sides of the polysilicon gate 110 and the metal gate 150 and covering the source and drain doped regions.

[0113] When the device is working, the source and drain doping regions are used to provide carrier sources for the channel region. Specifically, the source and drain doping regions are located in the substrate 100 on both sides of the polysilicon gate 110. When forming an NMOS transistor, the source and drain doping regions are doped with N-type ions; when forming a PMOS transistor, the source and drain doping regions are doped with P-type ions.

[0114] The interlayer dielectric layer 140 is used to isolate adjacent devices. In this embodiment, the material of the interlayer dielectric layer 140 is silicon oxide.

[0115] In this embodiment, the semiconductor structure further includes: a source-drain silicide layer (not shown), which is located between the top surface of the source-drain doped region and the interlayer dielectric layer 140. The source-drain silicide layer is used to improve the adhesion between the source-drain doped region and the subsequent source-drain contact hole plug, and reduce the contact resistance between the source-drain doped region and the source-drain contact hole plug, thereby improving the contact performance between the source-drain doped region and the source-drain contact hole plug.

[0116] By setting a metal gate 150 located on the substrate of the isolation region II and in contact with the polysilicon gate 110, a gate contact hole plug in contact with the metal gate 150 can be formed on the metal gate 150 subsequently. The materials of the gate contact hole plug and the metal gate 150 both include metal materials. The contact resistance between the gate contact hole plug and the metal gate 150 is small and the contact performance is high. Furthermore, by forming the metal gate 150 on the isolation region II, the polysilicon gate 110 can be electrically connected to an external circuit or other interconnection structure through the metal gate 150.

[0117] In this embodiment, the metal gate 150 includes a work function layer 52 on the substrate and a gate electrode layer 53 on the work function layer 52. The work function layer 52 is used to adjust the work function of the metal gate 150 to increase the threshold voltage of the edge device formed by the metal gate 150 and the substrate.

[0118] When the first type doped transistor is an N-type transistor, the second type work function metal is a P-type work function metal. When an N-type transistor is formed, by making the material of the work function layer 52 include a P-type work function metal, the work function of the metal gate 150 can be increased, thereby increasing the threshold voltage of the channel located below the metal gate 150, so that the channel of the edge device is controlled by the polysilicon gate 110 of the active region I.

[0119] Specifically, in this embodiment, when the first-type doped transistor is an N-type transistor, the work function of the second-type work function metal is greater than the work function of the gate dielectric barrier layer 111, so that the work function of the metal gate 150 is greater than the work function of the polysilicon gate 110 located in the active area I, and further, when the device is working, the opening or closing of the channel is mainly controlled by the gate dielectric barrier layer 111 in the active area I.

[0120] In this embodiment, the work function of the P-type work function metal is 4.5 eV to 5.5 eV. The material of the P-type work function metal includes one or more of TiN, Ta, TaN, TaSiN and TiSiN.

[0121] In this embodiment, when the first-type doped transistor is a P-type transistor, the second-type work function metal is an N-type work function metal. When the first-type doped transistor is a P-type transistor, by making the material of the metal gate 150 include an N-type work function metal, the work function of the metal gate 150 can be reduced, thereby increasing the threshold voltage of the channel located below the metal gate 150, so that the channel of the edge device is controlled by the polysilicon gate 110 of the active region I.

[0122] Specifically, in this embodiment, when the first-type doped transistor is a P-type transistor, in the process of forming the metal gate 150, the work function of the second-type work function metal is smaller than the work function of the gate dielectric barrier layer 111, thereby making the work function of the metal gate 150 lower than the work function of the polysilicon gate 110 in the active area I, thereby making the opening or closing of the channel mainly controlled by the gate dielectric barrier layer 111 in the active area I when the device is working.

[0123] In this embodiment, the work function of the N-type work function metal is 3.9 eV to 4.3 eV. The material of the N-type work function metal includes one or more of TiAl, TaAlN, TiAlN, MoN, TaCN and AlN.

[0124] The gate electrode layer 53 is used to realize electrical connection between the metal gate 150 and an external circuit or other interconnection structures. In this embodiment, the material of the gate electrode layer 53 is Al.

[0125] The semiconductor structure can be formed by the formation method described in the above embodiment, or by other formation methods. For the specific description of the semiconductor structure described in this embodiment, reference can be made to the corresponding description in the above embodiment, and this embodiment will not be repeated here.

[0126] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate for forming a first-type doped transistor, the substrate comprising a plurality of discrete active regions and isolation regions between the active regions; forming a polysilicon gate located in the active area and the isolation area on the substrate; Removing the polysilicon gate located in the isolation region, forming an opening in the polysilicon gate, removing the polysilicon gate located in the isolation region, and in the step of forming the opening in the polysilicon gate, also removing part of the polysilicon gate in the active region; A metal gate is filled in the opening, wherein the metal gate includes a work function layer located at the bottom of the opening, and the material of the work function layer includes a second type work function metal, which is different from the first type. In the extension direction of the polysilicon gate, the metal gate overlaps with the substrate of a portion of the active area.

2. The method for forming a semiconductor structure according to claim 1, wherein: In the step of forming the polysilicon gate, the method for forming the semiconductor structure further comprises: forming a stacked structure between the polysilicon gate and the substrate, comprising a gate dielectric layer and a gate dielectric barrier layer located on the gate dielectric layer; The gate dielectric barrier layer is used as a stop layer to remove the polysilicon gate located in the isolation region.

3. The method for forming a semiconductor structure according to claim 2, wherein: The material of the gate dielectric barrier layer includes TiN.

4. The method for forming a semiconductor structure according to claim 2 or 3, characterized in that: When the first-type doped transistor is an N-type transistor, during the process of forming the metal gate, the work function of the second-type work function metal is greater than the work function of the gate dielectric barrier layer; When the first-type doped transistor is a P-type transistor, during the process of forming the metal gate, the work function of the second-type work function metal is smaller than the work function of the gate dielectric barrier layer.

5. The method for forming a semiconductor structure according to claim 1, wherein: When the first-type doped transistor is an N-type transistor, the second-type work function metal is a P-type work function metal; when the first-type doped transistor is a P-type transistor, the second-type work function metal is an N-type work function metal.

6. The method for forming a semiconductor structure according to claim 5, wherein: The work function of the P-type work function metal is 4.5 eV to 5.5 eV; the work function of the N-type work function metal is 3.9 eV to 4.3 eV.

7. The method for forming a semiconductor structure according to claim 1, wherein: The step of removing the polysilicon gate located in the isolation area includes: forming a mask layer covering the polysilicon gate of the active area on the substrate, a mask opening exposing the polysilicon gate of the isolation area is formed in the mask layer; using the mask layer as a mask, removing the polysilicon gate under the mask opening to form the opening; and removing the mask layer.

8. The method for forming a semiconductor structure according to claim 1, wherein: A dry etching process is adopted to remove the polysilicon gate located in the isolation area.

9. The method for forming a semiconductor structure according to claim 1, wherein: After forming the polysilicon gate and before forming the opening, the method for forming the semiconductor structure further includes: forming source-drain doped regions in the substrate of the active area on both sides of the polysilicon gate; and forming an interlayer dielectric layer covering the source-drain doped regions on the substrate on the side of the polysilicon gate.

10. The method for forming a semiconductor structure according to claim 9, wherein: The method for forming the semiconductor structure further includes: forming a source-drain silicide layer on the top surface of the source-drain doping region after forming the source-drain doping region and before forming the interlayer dielectric layer.

11. The method for forming a semiconductor structure according to claim 1, wherein: After forming the metal gate, the method for forming the semiconductor structure further includes: forming a gate contact hole plug on the metal gate that contacts the metal gate.

12. The method for forming a semiconductor structure according to claim 1, wherein: The steps of forming the metal gate include: forming a work function film on the sidewalls and bottom of the opening, and the work function film is also formed on the polysilicon gate and the interlayer dielectric layer; forming a gate electrode film filling the opening on the work function film; removing the gate electrode film and the work function film above the top surface of the polysilicon gate and the interlayer dielectric layer, and the remaining work function film is used as the work function layer, and the remaining gate electrode film is used as the metal gate.

13. The method for forming a semiconductor structure according to claim 12, wherein: The process of forming the work function film includes an atomic layer deposition process or a physical vapor deposition process.

14. A semiconductor structure, characterized in that: include: A substrate for forming a first-type doped transistor, the substrate comprising a plurality of discrete active regions and isolation regions between the active regions; A polysilicon gate, located on the substrate of the active region; A metal gate is located on the base of the isolation region along the extension direction of the polysilicon gate and contacts the side wall of the polysilicon gate. The metal gate includes a work function layer. The material of the work function layer includes a second type work function metal, which is different from the first type. The metal gate is also formed on part of the active region. Along the extension direction of the polysilicon gate, the metal gate overlaps with the base of part of the active region.

15. The semiconductor structure according to claim 14, wherein: The semiconductor structure further includes: a stacked structure located between the polysilicon gate and the substrate, and between the metal gate and the substrate, wherein the stacked structure includes a gate dielectric layer and a gate dielectric barrier layer located on the gate dielectric layer.

16. The semiconductor structure according to claim 15, wherein: The material of the gate dielectric barrier layer includes TiN.

17. The semiconductor structure according to claim 15 or 16, characterized in that: When the first-type doped transistor is an N-type transistor, the work function of the second-type work function metal is greater than the work function of the gate dielectric barrier layer; when the first-type doped transistor is a P-type transistor, the work function of the second-type work function metal is less than the work function of the gate dielectric barrier layer.

18. The semiconductor structure according to claim 14, wherein: When the first-type doped transistor is an N-type transistor, the second-type work function metal is a P-type work function metal; when the first-type doped transistor is a P-type transistor, the second-type work function metal is an N-type work function metal.

19. The semiconductor structure according to claim 18, wherein: The work function of the P-type work function metal is 4.5 eV to 5.5 eV; the work function of the N-type work function metal is 3.9 eV to 4.3 eV.

20. The semiconductor structure according to claim 18, wherein: The material of the P-type work function metal includes one or more of TiN, Ta, TaN, TaSiN and TiSiN; the material of the N-type work function metal includes one or more of TiAl, TaAlN, TiAlN, MoN, TaCN and AlN.

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