A method for adjusting chip test voltage

Abstract

The present disclosure provides a method for adjusting chip test voltage, including: obtaining a test voltage requirement value of a chip to be tested and a test voltage value provided by a tester, wherein the test voltage requirement value includes a first low voltage value and a first high voltage value, and the test voltage value includes a second low voltage value and a second high voltage value; when the first low voltage value is lower than the second low voltage value and the first high voltage value is lower than the second high voltage value, connecting a voltage regulating module, inputting the second low voltage value and the second high voltage value into a first interface of the voltage regulating module, and at the same time, connecting the second interface of the voltage regulating module to an external power supply, wherein the external power supply provides a negative voltage value; connecting the third interface of the voltage regulating module to an input pin of the chip to be tested, wherein the third interface outputs voltages of the first low voltage value and the first high voltage value. Without changing the tester itself, the diversified requirements for test voltage of the test chip can be met.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuit testing, and in particular to a method for adjusting a chip test voltage. Background Art

[0002] The field of integrated circuit testing technology is a core industry of the new generation of information technology industry and has an extremely important strategic position. After integrated circuits, such as chips, are packaged, they need to undergo various tests to meet subsequent application requirements. However, due to the limitations of large-scale testing equipment, it is not possible to meet a variety of testing requirements, and it is not possible to equip a testing device for each testing requirement. Therefore, the existing testing equipment or methods limit the diversified testing requirements and bring many inconveniences to integrated circuit testing. Summary of the invention

[0003] The purpose of the present invention is to provide a method for adjusting chip test voltage, which can solve the technical problem of diversified requirements for integrated circuit test voltage. The specific scheme is as follows:

[0004] According to a specific embodiment of the present invention, the present invention provides a method for adjusting a chip test voltage, comprising:

[0005] Obtaining a test voltage requirement value of the chip to be tested and a test voltage value provided by the tester, wherein the test voltage requirement value includes a first low voltage value and a first high voltage value, and the test voltage value includes a second low voltage value and a second high voltage value;

[0006] When the first low pressure value is lower than the second low pressure value and the first high pressure value is lower than the second high pressure value, the voltage regulating module is turned on, the second low pressure value and the second high pressure value are input into the first interface of the voltage regulating module, and at the same time, the second interface of the voltage regulating module is connected to an external power supply, wherein the external power supply provides a negative pressure value;

[0007] The third interface of the voltage regulating module is connected to the input pin of the chip under test, wherein the third interface outputs a voltage of a first low voltage value and a first high voltage value.

[0008] Optionally, the difference between the first low pressure value and the first high pressure value is equal to the difference between the second low pressure value and the second high pressure value.

[0009] Optionally, the negative pressure value provided by the external power supply is equal to the difference between the first low pressure value and the second low pressure value.

[0010] Optionally, the first low voltage value is a negative voltage value.

[0011] Optionally, the voltage regulation module includes a first capacitor and a first resistor, wherein one end of the first capacitor is connected to the first interface, and the other end is connected to the second interface, one end of the first resistor is connected to the third interface, and the other end is connected to the other end of the first capacitor and then to the second interface.

[0012] Optionally, the voltage regulating module includes a first transistor Q1, a second transistor Q2 and a third transistor Q3, and the first transistor Q1 and the second transistor Q2 are connected in series and then connected in parallel with the third transistor Q3.

[0013] Optionally, the voltage regulating module further includes a second capacitor and a second resistor, and the second capacitor and the second resistor are connected in parallel and then in series with the third transistor Q3.

[0014] Optionally, the voltage regulation module further includes a third capacitor and a third resistor, the third resistor is connected in series between the gate of the first transistor Q1 and the gate of the third transistor Q3, and the third capacitor is connected between the gate of the third transistor Q3 and the ground.

[0015] Optionally, the external power supply includes n voltage sources connected in series, satisfying the following relationship:

[0016] u s =u s1 +u s2 +……+u sn .

[0017] Optionally, the method further includes: connecting the output end of the chip to be tested to the test machine, and after the test machine receives the output parameters of the chip to be tested, determining the test result of the chip to be tested.

[0018] Compared with the prior art, the embodiments of the present invention have the following technical effects:

[0019] The present invention provides a chip test voltage adjustment method, which obtains the test voltage requirement value of the chip to be tested and the test voltage value provided by the tester, and analyzes that when the test voltage requirement value of the chip to be tested does not match the test voltage value provided by the tester, the voltage adjustment module is turned on, and the test voltage value provided by the tester is adjusted by the negative pressure value provided by the external power supply to meet the test voltage requirement value. Thus, without changing the tester itself, the test voltage value of the input test chip can be adjusted according to the test voltage requirement value of the chip to be tested, thereby meeting the test requirements of the test chip and meeting the diversified test voltage requirements of the test chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The drawings herein are incorporated into and constitute a part of the specification, showing embodiments consistent with the present invention, and together with the specification, are used to explain the principles of the present invention. Obviously, the drawings described below are only some embodiments of the present invention, and for those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative work. In the drawings:

[0021] Figure 1 FIG. 1 is a diagram of a chip test voltage adjustment structure according to an embodiment of the present invention.

[0022] Figure 2 FIG. 1 is a schematic diagram of a voltage regulating module structure according to an embodiment of the present invention.

[0023] Figure 3 FIG. 4 is a schematic diagram of a voltage regulating module structure according to another embodiment of the present invention.

[0024] Figure 4 FIG. 4 is a structural diagram of a voltage source according to an embodiment of the present invention.

[0025] Figure 5 The figure is a flow chart of a method for adjusting chip test voltage according to an embodiment of the present invention.

[0026] Figure 6 FIG. 1 is a structural diagram of a chip test voltage adjustment system according to an embodiment of the present invention.

[0027] Figure 7 The electronic device structure diagram of one embodiment of the present invention. DETAILED DESCRIPTION

[0028] In order to make the purpose, technical scheme and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0029] The terms used in the embodiments of the present invention are only for the purpose of describing specific embodiments, and are not intended to limit the present invention. The singular forms "a", "said" and "the" used in the embodiments of the present invention and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings, and "multiple" generally includes at least two.

[0030] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0031] It should be understood that although the terms first, second, third, etc. may be used to describe in the embodiments of the present invention, these should not be limited to these terms. These terms are only used to distinguish. For example, without departing from the scope of the embodiments of the present invention, the first may also be referred to as the second, and similarly, the second may also be referred to as the first.

[0032] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a product or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such product or device. In the absence of more restrictions, the elements defined by the sentence "comprises a" do not exclude the presence of other identical elements in the product or device including the elements.

[0033] The optional embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0034] Figure 1 A schematic diagram of the structure of a test system provided in some embodiments of the present disclosure, such as Figure 1 As shown, the test system 100 includes an automatic tester 10 (ATE, Automatic Test Equipment), for example, an integrated circuit automatic tester. The automatic tester is used to detect the performance and function of an integrated circuit, such as a chip, and a plurality of connection components are arranged on the top surface thereof, which are used to connect with a test board and provide the test board with tester resources, i.e., various test signals. The chip is, for example, an FBGA chip, a flash chip, etc. The interfaces related to the automatic tester 10 of the present application include a test voltage output interface for providing a test voltage, and a signal receiving interface for receiving chip test results.

[0035] In the integrated circuit test, the automatic tester 10 will send a series of high and low voltages to the input pins of the tested chip 40 at different timing points, and compare the output voltages at the expected timing points of the output pins of the test chip 40, thereby judging whether the test chip 40 meets its function. Some types of test chips, such as A / D conversion chips, high-power amplifier integrated circuits, etc., require dual power supplies, that is, one positive voltage and one negative voltage. For example, a high-power amplifier integrated circuit uses OCL (Output CapacitorLess, a power amplifier circuit that omits a large capacitor at the output end), and needs to be tested with dual power supplies. As an example, the automatic test machine 10, such as: the PS1600 board of V93000 can provide a square wave voltage of [-1.5v, 6.5v], and the data transmission speed is 1600Mbps; the HSD800 board of J750HD can provide a square wave voltage of [-1.5v, 6.5v], and the data transmission speed is 800Mbps; the D IO module of the STS8200 platform can provide a square wave voltage of [-2v, 7v], and the frequency is 5MHz.

[0036] It can be seen that the negative voltage value of the test voltage provided by the automatic tester 10 is -1.5V or -2V. If a test negative voltage lower than -1.5V is required in chip testing, the test platform exemplified above cannot meet the test requirements.

[0037] The voltage regulating module 20, such as Figure 1 As shown, the voltage regulating module 20 is configured to adjust the test voltage of the automatic test machine 10 to meet the requirements of the test chip. As an example, the voltage regulating module 20 includes the following implementations.

[0038] As one of the implementation methods, Figure 2 As shown, the voltage regulating module 20 includes a first capacitor 204, a first resistor 205, and a first interface 201, a second interface 202, and a third interface 203, wherein one end of the first capacitor 204 is connected to the first interface 201 of the voltage regulating module 20, and the other end is connected to the second interface 202, one end of the first resistor 205 is connected to the third interface 203, and the other end is connected to the other end of the first capacitor 204 and then connected to the second interface 202. The capacitance of the first capacitor 204 and the resistance of the first resistor 205 can be selected according to the voltage range to be adjusted, and are not limited here. The voltage regulating module 20 of this embodiment has a simple structure and flexible device selection. When the capacitance of the first capacitor 204 and the resistance of the first resistor 205 are determined, the range of the regulated voltage can be flexibly calculated, which is particularly suitable for some integrated circuit tests with a small adjustment range.

[0039] As one of the implementation methods, Figure 3As shown, the voltage regulating module 200 includes a first transistor Q1, a second transistor Q2 and a third transistor Q3. The first transistor Q1 and the second transistor Q2 are connected in series and then connected in parallel with the third transistor Q3.

[0040] Optionally, the voltage regulating module 200 further includes a second capacitor 301 and a second resistor 302 . The second capacitor 301 and the second resistor 302 are connected in parallel and then in series with the third transistor Q3 .

[0041] Optionally, the voltage regulating module 200 further includes a third capacitor 303 and a third resistor 304, wherein the third resistor 304 is connected in series between the gate of the first transistor Q1 and the gate of the third transistor Q3, and the third capacitor 303 is connected between the gate of the third transistor Q3 and the ground line. The sizes of the second capacitor 301, the second resistor 302, the third capacitor 303 and the third resistor 304 can be selected according to the voltage range to be adjusted, and are not limited here.

[0042] The voltage regulating module 200 of this embodiment has a relatively complex structure. The voltage regulating circuit is flexibly configured by controlling the first transistor Q1, the second transistor Q2 and the third transistor Q3. It is suitable for testing some integrated circuits with a large regulation range and can select output values ​​according to requirements.

[0043] like Figure 4 As shown, the external power supply may include n voltage sources connected in series, satisfying the following relationship:

[0044] u s =u s1 +u s2 +……+u sn .

[0045] n is a natural number greater than 1, and each voltage source u in series sn The sizes can be the same or different, and can be pre-configured according to the range of voltage adjustment required, so that the voltage to be adjusted can be flexibly obtained.

[0046] like Figure 5 As shown, according to a specific embodiment of the present invention, the present invention provides a method for adjusting a chip test voltage, comprising the following method steps:

[0047] Step S502: Obtain the test voltage requirement value of the chip to be tested and the test voltage value provided by the tester, wherein the test voltage requirement value includes a first low voltage value and a first high voltage value, and the test voltage value includes a second low voltage value and a second high voltage value.

[0048] Among them, the test voltage requirement value of the chip to be tested can be determined according to the model of the chip to be tested. For example, the test voltage requirement of chip A to be tested is a square wave voltage of [-3v, 0v], and the test voltage requirement of chip B to be tested is a square wave voltage of [-3.5, 1.5V], etc. The test voltage of the chip to be tested is determined by the internal circuit structure of the integrated circuit. The tester can obtain the test voltage value through the instructions after the chip is packaged. The test voltage value provided by the tester is related to the model of the tester. As mentioned above, the PS1600 board of the V93000 can provide a square wave voltage of [-1.5v, 6.5v]; the HSD800 board of the J750HD can provide a square wave voltage of [-1.5v, 6.5v]; the DIO module of the STS8200 platform can provide a square wave voltage of [-2v, 7v].

[0049] Optionally, the first low voltage value is a negative voltage value, the first high voltage value is a positive voltage value, and the difference between the first low voltage value and the first high voltage value constitutes the amplitude of the square wave voltage; the second low voltage value is a negative voltage value, the second high voltage value is a positive voltage value, and the difference between the second low voltage value and the second high voltage value constitutes the amplitude of the square wave voltage. The amplitude of the square wave voltage formed by the difference between the first low voltage value and the first high voltage value is equal to the amplitude of the square wave voltage formed by the difference between the second low voltage value and the second high voltage value. The specific value can be arbitrarily configured, and there is no limitation on this, which is determined by the actual test equipment.

[0050] Step S504: When the first low pressure value is lower than the second low pressure value and the first high pressure value is lower than the second high pressure value, the voltage regulating module is turned on, and the second low pressure value and the second high pressure value are input into the first interface of the voltage regulating module. At the same time, the second interface of the voltage regulating module is connected to an external power supply, wherein the external power supply provides a negative pressure value.

[0051] As described above, the negative voltage value of the test voltage provided by the automatic tester 10 is -1.5V or -2V. If a negative voltage value lower than -1.5V is required in the chip test, that is, when the first low voltage value is lower than the second low voltage value, for example, when the first low voltage value is -3V, the test platform described above cannot meet the test requirements, and the voltage regulating module needs to be connected for voltage regulation. Because the test amplitude of the same square wave voltage needs to be met, when the first low voltage value is lower than the second low voltage value, the first high voltage value is also lower than the second high voltage value.

[0052] At this time, it is necessary to connect the voltage regulating module 20, input the second low pressure value and the second high pressure value into the first interface of the voltage regulating module 20, so as to adjust according to the second low pressure value and the second high pressure value, and at the same time, connect the second interface of the voltage regulating module to the external power supply, wherein the external power supply provides a negative pressure value.

[0053] The external power supply may include n voltage sources connected in series, satisfying the following relationship:

[0054] u s =u s1 +u s2 +……+u sn .

[0055] n is a natural number greater than 1, and each voltage source u in series sn The sizes can be the same or different, and can be pre-configured according to the range of voltage adjustment required, so that the voltage to be adjusted can be flexibly obtained.

[0056] Optionally, the difference between the first low pressure value and the first high pressure value is equal to the difference between the second low pressure value and the second high pressure value, so as to ensure that the amplitude and frequency remain unchanged after the voltage regulation.

[0057] Optionally, the negative pressure value provided by the external power supply is equal to the difference between the first low pressure value and the second low pressure value. For example, when the low pressure value is adjusted from -1.5V to -3V, the negative pressure value provided by the external power supply to be input is -1.5V.

[0058] Step S506: Connecting the third interface of the voltage regulating module to the input pin of the chip under test, wherein the third interface outputs voltages of a first low voltage value and a first high voltage value.

[0059] This embodiment uses an ATE tester to provide a positive voltage signal with a frequency of f, sets the high level VIH of the signal pin to be aV, the low level VIL to be bV, and the external power supply 30 provides a negative voltage -nV to the voltage regulating module 20. The negative voltage can be connected in series using any number of external power supplies as needed, and then the positive and negative electrodes are reversed and connected to the voltage regulating module 20 or the voltage regulating module 200. The output result after voltage regulation is a square wave signal with a frequency of f, a high level voltage equal to VIH=(an)V, and a low level voltage VIL=(bn)V.

[0060] As an embodiment, for example, testing a chip requires providing an input signal with a frequency of 50MHz, VIH=0V, VIL=-3V. The ATE platform used for the test is V93000, and the model of the voltage regulator module 20 is: ZFBT-4R2GW+. The V93000 platform is used to set an input voltage of 50MHz, VIL=0V, VIH=3V to the input port of the voltage regulator module 20, and the external power supply 30 sets -3v to the reference voltage port of the voltage regulator module 20, and the output port of the voltage regulator module 20 is input to the chip port. When V93000 inputs VIL=0V, the voltage converted to the chip by the voltage regulator module 20 is -3V, and when V93000 inputs VIH=3V, the voltage converted to the chip by the voltage regulator module 20 is 0V, that is, the frequency remains unchanged, and the purpose of converting the test voltage from 0~3V to -3~0V is achieved.

[0061] As one of the implementation methods, Figure 2 As shown, the voltage regulating module 20 includes a first capacitor 204, a first resistor 205, and a first interface 201, a second interface 202, and a third interface 203, wherein one end of the first capacitor 204 is connected to the first interface 201 of the voltage regulating module 20, and the other end is connected to the second interface 202, one end of the first resistor 205 is connected to the third interface 203, and the other end is connected to the other end of the first capacitor 204 and then connected to the second interface 202. The capacitance of the first capacitor 204 and the resistance of the first resistor 205 can be selected according to the voltage range to be adjusted, and are not limited here. The voltage regulating module 20 of this embodiment has a simple structure and flexible device selection. When the capacitance of the first capacitor 204 and the resistance of the first resistor 205 are determined, the range of the regulated voltage can be flexibly calculated, which is particularly suitable for some integrated circuit tests with a small adjustment range.

[0062] As one of the implementation methods, Figure 3 As shown, the voltage regulating module 200 includes a first transistor Q1, a second transistor Q2 and a third transistor Q3. The first transistor Q1 and the second transistor Q2 are connected in series and then connected in parallel with the third transistor Q3.

[0063] Optionally, the voltage regulating module 200 further includes a second capacitor 301 and a second resistor 302 . The second capacitor 301 and the second resistor 302 are connected in parallel and then in series with the third transistor Q3 .

[0064] Optionally, the voltage regulating module 200 further includes a third capacitor 303 and a third resistor 304, wherein the third resistor 304 is connected in series between the gate of the first transistor Q1 and the gate of the third transistor Q3, and the third capacitor 303 is connected between the gate of the third transistor Q3 and the ground line. The sizes of the second capacitor 301, the second resistor 302, the third capacitor 303 and the third resistor 304 can be selected according to the voltage range to be adjusted, and are not limited here.

[0065] The voltage regulating module 200 of this embodiment has a relatively complex structure. The voltage regulating circuit is flexibly configured by controlling the first transistor Q1, the second transistor Q2 and the third transistor Q3. It is suitable for testing some integrated circuits with a large regulation range and can select output values ​​according to requirements.

[0066] Optionally, it also includes: connecting the output end of the chip to be tested to the test machine, and after the test machine receives the output parameters of the chip to be tested, judging the test result of the chip to be tested. After obtaining the test voltage that meets the requirements, the test voltage is input into the chip to be tested, and the chip to be tested will output the test signal to the test machine, and the test machine judges the quality of the chip according to the input test signal.

[0067] The present invention provides a chip test voltage adjustment method, which obtains the test voltage requirement value of the chip to be tested and the test voltage value provided by the tester, and analyzes that when the test voltage requirement value of the chip to be tested does not match the test voltage value provided by the tester, the voltage adjustment module is turned on, and the test voltage value provided by the tester is adjusted by the negative pressure value provided by the external power supply to meet the test voltage requirement value. Thus, without changing the tester itself, the test voltage value of the input test chip can be adjusted according to the test voltage requirement value of the chip to be tested, thereby meeting the test requirements of the test chip and meeting the diversified test voltage requirements of the test chip.

[0068] According to the embodiments provided by the present disclosure, Figure 6 As shown, the present disclosure provides a chip test voltage adjustment system 600, comprising:

[0069] An acquisition unit 602 is configured to acquire a test voltage requirement value of the chip to be tested and a test voltage value provided by the tester, wherein the test voltage requirement value includes a first low voltage value and a first high voltage value, and the test voltage value includes a second low voltage value and a second high voltage value;

[0070] The connecting unit 604 is configured to connect the voltage regulating module when the first low pressure value is lower than the second low pressure value and the first high pressure value is lower than the second high pressure value, input the second low pressure value and the second high pressure value into the first interface of the voltage regulating module, and connect the second interface of the voltage regulating module to an external power supply, wherein the external power supply provides a negative pressure value;

[0071] The connecting unit 606 is configured to connect the third interface of the voltage regulating module to the input pin of the chip under test, wherein the third interface outputs a voltage of a first low voltage value and a first high voltage value.

[0072] The difference between the first low pressure value and the first high pressure value is equal to the difference between the second low pressure value and the second high pressure value.

[0073] The negative pressure value provided by the external power supply is equal to the difference between the first low pressure value and the second low pressure value.

[0074] The first low voltage value is a negative voltage value.

[0075] The voltage regulation module includes a first capacitor and a first resistor, wherein one end of the first capacitor is connected to the first interface, and the other end is connected to the second interface, one end of the first resistor is connected to the third interface, and the other end is connected to the other end of the first capacitor and then connected to the second interface.

[0076] The voltage regulating module includes a first transistor Q1, a second transistor Q2 and a third transistor Q3. The first transistor Q1 and the second transistor Q2 are connected in series and then connected in parallel with the third transistor Q3.

[0077] The voltage regulating module further includes a second capacitor and a second resistor. The second capacitor and the second resistor are connected in parallel and then in series with the third transistor Q3.

[0078] The voltage regulating module further includes a third capacitor and a third resistor. The third resistor is connected in series between the gate of the first transistor Q1 and the gate of the third transistor Q3. The third capacitor is connected between the gate of the third transistor Q3 and the ground line.

[0079] The external power supply includes n voltage sources connected in series, satisfying the following relationship:

[0080] u s =u s1 +u s2 +……+u sn .

[0081] It also includes: a testing unit configured to connect the output end of the chip to be tested to the testing machine, and after the testing machine receives the output parameters of the chip to be tested, it determines the test result of the chip to be tested.

[0082] The present invention provides a chip test voltage adjustment system, which obtains the test voltage requirement value of the chip to be tested and the test voltage value provided by the tester, and analyzes that when the test voltage requirement value of the chip to be tested does not match the test voltage value provided by the tester, the voltage adjustment module is turned on, and the test voltage value provided by the tester is adjusted by the negative pressure value provided by the external power supply to meet the test voltage requirement value. Therefore, without changing the tester itself, the test voltage value of the input test chip can be adjusted according to the test voltage requirement value of the chip to be tested, thereby meeting the test requirements of the test chip and meeting the diversified test voltage requirements of the test chip.

[0083] like Figure 7 As shown, this embodiment provides an electronic device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the method steps described in the above embodiment.

[0084] An embodiment of the present disclosure provides a non-volatile computer storage medium, wherein the computer storage medium stores computer executable instructions, and the computer executable instructions can execute the method steps described in the above embodiment.

[0085] The present disclosure provides a computer program product, including a computer program, wherein the computer program implements the method described in the above embodiment when executed by a processor.

[0086] Reference below Figure 7 , which shows a schematic diagram of the structure of an electronic device suitable for implementing the embodiments of the present disclosure. The electronic device in the embodiments of the present disclosure may include, but is not limited to, mobile terminals such as mobile phones, notebook computers, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), vehicle-mounted terminals (such as vehicle-mounted navigation terminals), etc., and fixed terminals such as digital TVs, desktop computers, etc. Figure 7 The electronic device shown is only an example and should not bring any limitation to the functions and scope of use of the embodiments of the present disclosure.

[0087] like Figure 7As shown, the electronic device may include a processing device (e.g., a central processing unit, a graphics processing unit, etc.) 701, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 702 or a program loaded from a storage device 708 into a random access memory (RAM) 703. In the RAM 703, various programs and data required for the operation of the electronic device are also stored. The processing device 701, the ROM 702, and the RAM 703 are connected to each other via a bus 704. An input / output (I / O) interface 705 is also connected to the bus 704.

[0088] Typically, the following devices may be connected to the I / O interface 705: input devices 706 including, for example, a touch screen, a touch pad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; output devices 707 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; storage devices 708 including, for example, a magnetic tape, a hard disk, etc.; and communication devices 709. The communication devices 709 may allow the electronic device to communicate with other devices wirelessly or by wire to exchange data. Although Figure 7 An electronic device having various devices is shown, but it should be understood that it is not required to implement or possess all the devices shown. More or fewer devices may be implemented or possessed instead.

[0089] In particular, according to an embodiment of the present disclosure, the process described above with reference to the flowchart can be implemented as a computer software program. For example, an embodiment of the present disclosure includes a computer program product, which includes a computer program carried on a computer-readable medium, and the computer program includes a program code for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from a network through a communication device 709, or installed from a storage device 708, or installed from a ROM 702. When the computer program is executed by the processing device 701, the above-mentioned functions defined in the method of the embodiment of the present disclosure are executed.

[0090] It should be noted that the computer-readable medium disclosed above may be a computer-readable signal medium or a computer-readable storage medium or any combination of the above two. The computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present disclosure, a computer-readable storage medium may be any tangible medium containing or storing a program that may be used by or in combination with an instruction execution system, device or device. In the present disclosure, a computer-readable signal medium may include a data signal propagated in a baseband or as part of a carrier wave, in which a computer-readable program code is carried. This propagated data signal may take a variety of forms, including but not limited to an electromagnetic signal, an optical signal, or any suitable combination of the above. The computer readable signal medium may also be any computer readable medium other than a computer readable storage medium, which may send, propagate or transmit a program for use by or in conjunction with an instruction execution system, apparatus or device. The program code contained on the computer readable medium may be transmitted using any suitable medium, including but not limited to: wires, optical cables, RF (radio frequency), etc., or any suitable combination of the above.

[0091] The computer-readable medium may be included in the electronic device, or may exist independently without being incorporated into the electronic device.

[0092] Computer program code for performing the operations of the present disclosure may be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, C++, and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, as a separate software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving a remote computer, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0093] The flow chart and block diagram in the accompanying drawings illustrate the possible architecture, function and operation of the system, method and computer program product according to various embodiments of the present disclosure. In this regard, each square box in the flow chart or block diagram can represent a module, a program segment or a part of a code, and the module, the program segment or a part of the code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some implementations as replacements, the functions marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two square boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each square box in the block diagram and / or flow chart, and the combination of the square boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0094] The units involved in the embodiments described in the present disclosure may be implemented by software or hardware, wherein the name of a unit does not, in some cases, limit the unit itself.

Claims

1. A method for adjusting chip test voltage, characterized in that include: Obtaining a test voltage requirement of the chip to be tested and a test voltage provided by the tester, wherein the test voltage requirement includes a required square wave voltage having a first low voltage value and a first high voltage value, and the test voltage includes a test square wave voltage having a second low voltage value and a second high voltage value; When the first low voltage value is lower than the second low voltage value and the first high voltage value is lower than the second high voltage value, the voltage regulating module is turned on, the test square wave voltage having the second low voltage value and the second high voltage value is input into the first interface of the voltage regulating module, and at the same time, the second interface of the voltage regulating module is connected to an external power supply, wherein the external power supply provides a negative pressure value; Connecting the third interface of the voltage regulating module to the input pin of the chip to be tested, wherein the third interface outputs a required square wave voltage having a first low voltage value and a first high voltage value, The difference between the first low pressure value and the first high pressure value is equal to the difference between the second low pressure value and the second high pressure value.

2. The method according to claim 1, characterized in that The negative pressure value provided by the external power supply is equal to the difference between the first low pressure value and the second low pressure value.

3. The method according to claim 1, characterized in that The first low voltage value is a negative voltage value.

4. The method according to claim 1, characterized in that: The voltage regulation module includes a first capacitor and a first resistor, wherein one end of the first capacitor is connected to the first interface, and the other end is connected to the second interface, one end of the first resistor is connected to the third interface, and the other end is connected to the other end of the first capacitor and then connected to the second interface.

5. The method according to claim 1, characterized in that The voltage regulating module includes a first transistor Q1, a second transistor Q2 and a third transistor Q3. The first transistor Q1 and the second transistor Q2 are connected in series and then connected in parallel with the third transistor Q3.

6. The method according to claim 5, characterized in that The voltage regulating module further includes a second capacitor and a second resistor. The second capacitor and the second resistor are connected in parallel and then in series with the third transistor Q3.

7. The method according to claim 6, characterized in that The voltage regulating module further includes a third capacitor and a third resistor. The third resistor is connected in series between the gate of the first transistor Q1 and the gate of the third transistor Q3. The third capacitor is connected between the gate of the third transistor Q3 and the ground line.

8. The method according to claim 1, characterized in that The external power supply includes n voltage sources connected in series, satisfying the following relationship: in s =in s1 +in s2 +……+in sn n is a natural number greater than 1, and the sizes of each voltage source connected in series may be the same or different.

9. The method according to claim 1, characterized in that: Also includes: The output end of the chip to be tested is connected to the test machine, and after the test machine receives the output parameters of the chip to be tested, it determines the test result of the chip to be tested.

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