Fan-out wafer-level packaging structure and packaging method

Abstract

The present invention provides a fan-out type wafer-level packaging structure and a preparation method, the structure comprising: two or more semiconductor chips with pads, the semiconductor chips are arranged in a fan-out type wafer array, each semiconductor chip has its own initial position; a plastic sealing layer, covering the surface of the semiconductor chip and between each semiconductor chip, each semiconductor chip has its own offset position after plastic sealing, and the offset position has an offset distance relative to the initial position; a rewiring layer, formed on the semiconductor chip to achieve interconnection between each semiconductor chip, the rewiring layer at least includes a first rewiring layer, the first rewiring layer is formed on the surface of the semiconductor chip, and is aligned and connected with the pad of the semiconductor chip; a metal bump is formed on the rewiring layer. The fan-out type wafer-level packaging structure can achieve effective alignment between the semiconductor chip and the rewiring layer, and improve the yield rate of wafer packaging.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor packaging, and in particular relates to a fan-out wafer-level packaging structure and a packaging method. Background Art

[0002] With the rapid development of the integrated circuit manufacturing industry, people's requirements for integrated circuit packaging technology are also constantly increasing. The existing packaging technologies include ball grid array packaging (BGA), chip size packaging (CSP), wafer level packaging (WLP), three-dimensional packaging (3D) and system packaging (SiP). Among them, wafer level packaging (WLP) has gradually been adopted by most semiconductor manufacturers due to its outstanding advantages. All or most of its process steps are completed on silicon wafers that have completed the previous process, and finally the wafers are directly cut into separate independent devices. Wafer level packaging (WLP) has its unique advantages: ① High packaging processing efficiency, multiple wafers can be processed at the same time; ② It has the advantages of flip chip packaging, that is, light, thin, short and small; ③ Compared with the previous process, only two processes, pin rewiring (RDL) and bump production, are added, and the rest are all traditional processes; ④ Reduce the multiple tests in traditional packaging. Therefore, major IC packaging companies in the world have invested in the research, development and production of this type of WLP.

[0003] Fan-out wafer-level packaging has attracted much attention from manufacturers such as mobile device manufacturers due to its advantages of miniaturization, low cost and high integration. Fan-out wafer-level packaging is currently most suitable for the demanding mobile / wireless market and is also very attractive to other markets that focus on high performance and small size.

[0004] The existing fan-out wafer-level packaging process generally involves first pasting the semiconductor chip to the adhesive layer of the supporting substrate, and then using a plastic encapsulation material for plastic encapsulation. During the plastic encapsulation process, the plastic encapsulation material is heated to a liquid state and pressed under a high temperature environment. This process will cause the wafer to warp, generally upward (such as Figure 1 As shown in the figure, when the whole wafer is warped, several semiconductor chips on the wafer will drift in different degrees in various directions, so that the pads on the semiconductor chips will deviate from the original positions on the wafer. When the whole wafer is warped upward, the semiconductor chips at the edge of the wafer and the semiconductor chips in the middle of the wafer will drift, and the semiconductor chips at the edge will have a larger offset than those in the center. When the semiconductor chips drift, the subsequent packaging process will be severely tested. For example, when the redistribution layer (RDL) is subsequently formed, due to the drift of the semiconductor chips, when the dielectric layer of the re-distribution layer is formed by photolithography, the photolithography pattern and the semiconductor chip pads cannot be accurately aligned, which reduces the alignment accuracy of the entire re-distribution layer preparation, thereby affecting the yield of wafer packaging. Summary of the invention

[0005] In view of the shortcomings of the prior art mentioned above, the object of the present invention is to provide a fan-out wafer-level packaging structure and a packaging method, which are used to solve the problems in the prior art that the fan-out wafer-level packaging causes wafer warping and semiconductor chip drift after the semiconductor chip is plastic-sealed, thereby increasing the difficulty of the subsequent packaging process and affecting the yield of wafer packaging.

[0006] To achieve the above-mentioned object and other related objects, the present invention provides a packaging method of a fan-out wafer-level packaging structure, the packaging method comprising:

[0007] Providing two or more semiconductor chips with bonding pads;

[0008] Bonding the semiconductor chip to the bonding layer to form a fan-out wafer array, wherein the fan-out wafer array is divided into more than two semiconductor chip units, and each of the semiconductor chips has its own initial position;

[0009] The semiconductor chips are packaged with a plastic packaging layer, each of the semiconductor chips has a respective offset position, and the offset position has an offset distance relative to the initial position;

[0010] The adhesive layer is removed, and a rewiring layer is formed on the semiconductor chip to realize interconnection between the semiconductor chips; the rewiring layer includes at least one first rewiring layer, and the method for forming the first rewiring layer includes: forming a dielectric layer on the semiconductor chip; taking the area corresponding to each semiconductor chip unit as a dielectric layer etching unit, correspondingly, dividing the dielectric layer into more than two dielectric layer etching units, etching all the dielectric layer etching units one by one using a photolithography process to form a through hole in the dielectric layer to expose the pad of each semiconductor chip, wherein the photolithography exposure direction of the photolithography process is readjusted each time the dielectric layer etching unit is etched; forming a patterned metal wiring layer corresponding to the through hole in the through hole and on the dielectric layer;

[0011] Metal bumps are formed on the rewiring layer.

[0012] Optionally, the adhesive layer is adhered to a supporting substrate; and before forming the rewiring layer, the supporting substrate and the adhesive layer are removed simultaneously.

[0013] Optionally, the rewiring layer also includes at least one second rewiring layer formed on the first rewiring layer, and the method for forming the second rewiring layer includes: forming the dielectric layer on the surface of the upper rewiring layer; etching the dielectric layer using a photolithography process to form a through hole in the dielectric layer to expose the patterned metal wiring layer of the upper layer; forming a patterned metal wiring layer corresponding to the through hole in the through hole and on the dielectric layer.

[0014] Optionally, the adhesive layer includes one of an adhesive tape, an adhesive made by a spin coating process, or an epoxy resin.

[0015] Optionally, the material of the plastic sealing layer includes one of polyimide, silicone and epoxy resin.

[0016] Optionally, the material of the dielectric layer includes one or a combination of two or more of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphosilicate glass, and fluorine-containing glass, and the material of the metal wiring layer includes one or a combination of two or more of copper, aluminum, nickel, gold, silver, and titanium.

[0017] The present invention also provides a fan-out wafer-level packaging structure, the packaging structure comprising:

[0018] Two or more semiconductor chips with bonding pads, the semiconductor chips are arranged in a fan-out wafer array, and each of the semiconductor chips has its own initial position;

[0019] A plastic sealing layer, covering the surface of the semiconductor chip and between the semiconductor chips, each of the semiconductor chips has a respective offset position after plastic sealing, and the offset position has an offset distance relative to the initial position;

[0020] A rewiring layer is formed on the semiconductor chip to realize interconnection between the semiconductor chips, and the rewiring layer includes at least one first rewiring layer, which is formed on the surface of the semiconductor chip and is aligned and connected with the pad of the semiconductor chip;

[0021] Metal bumps are formed on the rewiring layer.

[0022] Optionally, the rewiring layer includes a patterned dielectric layer and a patterned metal wiring layer.

[0023] Optionally, the material of the patterned dielectric layer includes one or a combination of two or more of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphosilicate glass, and fluorine-containing glass, and the material of the patterned metal wiring layer includes one or a combination of two or more of copper, aluminum, nickel, gold, silver, and titanium.

[0024] Optionally, the material of the plastic sealing layer includes one of polyimide, silicone and epoxy resin.

[0025] As described above, the fan-out wafer-level packaging structure and packaging method of the present invention, when forming the first layer of rewiring layer, divide the fan-out wafer array into multiple etching units by dividing the units, and etch and open windows for each etching unit one by one to form through holes exposing the semiconductor chip pads. The lithography exposure direction in the lithography process is readjusted each time the window is etched, which is equivalent to decomposing one alignment exposure into multiple alignment exposures. Each alignment exposure adjusts the exposure direction according to the offset distance and offset direction of the semiconductor chip in the etching unit where it is located, effectively improving the alignment accuracy of the lithography process when forming the rewiring layer. Based on this high-precision lithography alignment effect, the alignment accuracy of the subsequently formed rewiring layer can be effectively improved, thereby effectively improving the yield of wafer packaging; and the method only needs to set a light shielding structure on the lithography mask to achieve, the method is simple and feasible, and has strong operability. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 A three-dimensional schematic diagram showing warping and drifting of a conventional fan-out wafer-level package after the semiconductor chip is plastic-sealed.

[0027] Figure 2 to Figure 17 Shown is a schematic cross-sectional structure diagram presented at each step of the packaging method of the fan-out wafer-level packaging structure of the present invention.

[0028] Component number description

[0029] 100 Wafer

[0030] 200 Semiconductor Chips

[0031] 201 Solder pad

[0032] 202 Adhesive layer

[0033] 203 Fan-Out Wafer Array

[0034] 204 semiconductor chip unit

[0035] 205 plastic layer

[0036] 206 dielectric layer

[0037] 207 Dielectric layer etching unit

[0038] 208 photoresist layer

[0039] 209 Light mask with shielding structure

[0040] 210 Through hole

[0041] 211 Patterned dielectric layer

[0042] 212 Patterned Metal Wiring Layer

[0043] 213 First rewiring layer

[0044] 214 Second rewiring layer

[0045] 215 Rewiring Layer

[0046] 216 metal bumps

[0047] 217 Supporting base DETAILED DESCRIPTION

[0048] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0049] See also Figures 2 to 17 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0050] like Figure 1 As shown, in the existing fan-out wafer-level packaging process, after the semiconductor chip is plastic-sealed, the entire wafer will warp, and the semiconductor chip will drift to varying degrees in all directions, so that the pads on the semiconductor chip will deviate from their original positions on the wafer. This will pose a severe test to the back-end process of the fan-out wafer-level packaging, resulting in a decrease in the yield of wafer packaging.

[0051] The inventor discovered the above problem, and based on this problem, analyzed various factors in detail from each link of the packaging, and comprehensively proposed a packaging method for a fan-out wafer-level packaging structure. The packaging method starts from the back-end process after the semiconductor chip is plastic-sealed. When forming the first layer of the rewiring layer, the fan-out wafer array is divided into multiple etching units by dividing the units, and each etching unit is etched and opened one by one to form a through hole for exposing the semiconductor chip pad. The photolithography exposure direction in the photolithography process is readjusted each time the window is etched, which is equivalent to decomposing one alignment exposure into multiple alignment exposures. Each alignment exposure adjusts the exposure direction according to the offset distance and offset direction of the semiconductor chip in the etching unit where it is located, effectively improving the alignment accuracy of the photolithography process when forming the rewiring layer. Based on this high-precision photolithography alignment effect, the alignment accuracy of the rewiring layer formed subsequently can be effectively improved, thereby effectively improving the yield of wafer packaging; and the method only needs to set a light shielding structure on the photolithography mask to achieve the method, which is simple and feasible, and has strong operability.

[0052] like Figures 2 to 17 As shown, the packaging method includes:

[0053] like Figure 2 and Figure 3 As shown, step 1) is first performed to provide two or more semiconductor chips 200 with bonding pads 201 .

[0054] The semiconductor chip 200 can be any existing semiconductor chip suitable for packaging, and can be an independent functional chip, such as a memory chip, a circuit chip, etc., or an integrated functional chip, such as an APU chip, a GPU chip, etc., without limitation herein. The material of the pad 201 in the semiconductor chip 200 includes metal aluminum, which is an aluminum pad. When preparing the pad 201, in order to improve the electrical properties of the pad and the bonding properties with the semiconductor chip 200, etc., an adhesive layer can also be formed under the pad 201, and an anti-reflection layer can be formed on the pad 201.

[0055] like Figure 2 and Figure 3 As shown, step 2) is then performed to bond the semiconductor chip 200 to the bonding layer 202 to form a fan-out wafer array 203, wherein the fan-out wafer array 203 is divided into more than two semiconductor chip units 204, and each of the semiconductor chips 200 has its own initial position.

[0056] It should be noted here that, based on the requirements of packaging efficiency, packaging size, etc., the fan-out wafer array 203 generally has multiple semiconductor chips 200 bonded thereto. In most cases, far more than two semiconductor chips 200 are bonded thereto, and the more semiconductor chips 200 are bonded thereto, the more obvious the effect achieved by this embodiment. The number of pads 201 on the semiconductor chip 200 is not limited to the two shown in the figure, and the specific number is set according to the specific semiconductor chip 200.

[0057] As an example, the number of the semiconductor chips 200 in each semiconductor chip unit 204 can be determined based on the maximum offset distance of the semiconductor chips 200 in the semiconductor chip unit 204 after subsequent semiconductor chip plastic encapsulation. The number of the semiconductor chip units 204 divided by the fan-out wafer array 203 is more than two, that is, it can be two or more, and the more the number, the more obvious the effect achieved by this embodiment. In this embodiment, for ease of understanding, the semiconductor chips 200 arranged in a row in the figure are one semiconductor chip unit 204, so the semiconductor chip unit 204 in the cross-sectional view can only show one semiconductor chip 200, and the figure takes two semiconductor chip units 204 arranged in this manner as an example for explanation.

[0058] like Figure 2 As shown, as an example, the semiconductor chip 200 is only bonded to the bonding layer 202 to form the fan-out wafer array 203. This method has a low cost, but is more prone to warping and drifting after subsequent plastic packaging. The bonding layer 202 can be a material such as tape, UV bonding glue formed by spin coating, or epoxy resin. In this embodiment, the bonding layer 202 is a UV bonding glue formed by spin coating, and the viscosity of the UV bonding glue will decrease under ultraviolet light.

[0059] like Figure 3 As shown, as an example, the adhesive layer 202 is bonded to the supporting substrate 217, and the fan-out wafer array 203 is formed by the supporting substrate 217. The supporting substrate 217 can be made of glass, ceramic, metal, polymer and the like. In this embodiment, the supporting substrate 217 includes one of glass, transparent semiconductor material, and transparent polymer, so that the UV adhesive can be subsequently exposed from the back of the supporting substrate 217, which greatly simplifies the subsequent peeling process.

[0060] When the semiconductor chip 200 is bonded to the bonding layer 202, the side of the semiconductor chip 200 with the solder pad 201 is bonded toward the bonding layer. After the bonding layer is removed and before the rewiring layer is formed, the semiconductor chip is turned upside down to facilitate the formation of the rewiring layer on the semiconductor chip.

[0061] like Figure 4 As shown, then proceed to step 3), the semiconductor chip 200 is encapsulated with a plastic layer 205, each of the semiconductor chips 200 has its own offset position, and the offset position has an offset distance relative to the initial position. During plastic encapsulation, the plastic encapsulation material is heated to a liquid state, and is pressed in a high temperature environment. Since all the semiconductor chips 200 are wafer arrays formed by re-bonding one by one, warping will occur under this pressing pressure, and the semiconductor chip 200 will drift, that is, the offset position of the semiconductor chip 200 after plastic encapsulation in the wafer array will have an offset distance relative to its initial position in the wafer array (initial position), and since each semiconductor chip 200 is located in a different position in the wafer array, the direction and degree of its offset are also different, and accordingly, the pads on the semiconductor chip will also be offset.

[0062] As an example, the material of the plastic encapsulation layer 205 includes one of polyimide, silica gel and epoxy resin. The plastic encapsulation layer 205 is formed into an opaque material by adding additives.

[0063] As an example, the process used to plastic-encapsulate the semiconductor chip 200 includes: an injection molding process, a compression molding process, a printing process, a transfer molding process, a liquid sealant curing molding process, a vacuum lamination process, and a spin coating process. In this embodiment, each semiconductor chip 200 is plastic-encapsulated by an injection molding process, and the plastic sealing layer 205 is opaque silica gel.

[0064] like Figures 5 to 13 As shown, then proceed to step 4), remove the adhesive layer 202 (as shown Figure 5 As shown), and a rewiring layer 215 is formed on the semiconductor chip 200 (as shown Fig.13 As shown in the figure), to realize the interconnection between each semiconductor chip 200; the rewiring layer 215 includes at least one first rewiring layer 213, and the method for forming the first rewiring layer 213 includes: forming a dielectric layer 206 on the semiconductor chip 200; taking the area corresponding to each semiconductor chip unit 204 as a dielectric layer etching unit 207, correspondingly, dividing the dielectric layer 206 into more than two dielectric layer etching units 207, and etching all the dielectric layer etching units 207 one by one by using a photolithography process (as shown in the figure); Figures 8 to 10 ), so as to form a through hole 210 in the dielectric layer 206 to expose the pad 201 of each semiconductor chip 200, wherein the photolithography exposure direction of the photolithography process is readjusted each time the dielectric layer etching unit 207 is etched; a patterned metal wiring layer 212 (such as Fig.11shown).

[0065] When forming the first rewiring layer 213, the fan-out wafer array 203 is divided into a plurality of exposure and etching units by dividing the units, and each dielectric layer etching unit 207 is etched and opened one by one to form a through hole exposing the semiconductor chip pad. The lithography exposure direction in the lithography process is readjusted each time the window is etched, which is equivalent to decomposing one alignment exposure into multiple alignment exposures. Each alignment exposure adjusts the exposure direction according to the offset distance and offset direction of the semiconductor chip in the etching unit where it is located, which effectively improves the alignment accuracy of the lithography process when forming the rewiring layer. Based on this high-precision lithography alignment effect, the alignment accuracy of the subsequently formed rewiring layer can be effectively improved, thereby effectively improving the yield of wafer packaging. Moreover, this method only needs to set a light shielding structure on the lithography mask to achieve implementation, and the method is simple and feasible with strong operability.

[0066] When the fan-out wafer array 203 is formed by the adhesive layer 202 and the supporting substrate 217 , the supporting substrate 217 is removed simultaneously with the adhesive layer 202 .

[0067] like Figures 6 to 11 As shown, as an example, when the material of the dielectric layer 206 is selected to include one or a combination of two or more of epoxy resin, silica gel, BCB, silicon oxide, phosphorus silicon glass, and fluorine-containing glass, the method for forming the first rewiring layer 213 includes:

[0068] like Figure 6 As shown, a dielectric layer 206 is formed on the semiconductor chip 200. The dielectric layer 206 can be formed by chemical vapor deposition process or physical vapor deposition process;

[0069] like Figure 7 As shown, a photoresist layer 208 is then coated on the dielectric layer 206;

[0070] like Figure 8 As shown, a mask 209 with a shielding structure is then used to expose the photoresist layer 208, so that the photoresist layer 208 on the dielectric layer etching unit 207 on the left is exposed to form a corresponding etching window, and then an etching process is used to etch the dielectric layer 206 through the etching window to form a through hole 210 in the dielectric layer etching unit 207 on the left, and the through hole 210 exposes the pad 201 on the semiconductor chip 200 in the semiconductor chip unit 204 on the left;

[0071] like Fig. 9As shown, the relative direction between the photomask 209 with a shielding structure and the dielectric layer etching unit 207 is then adjusted, and then the photomask 209 with a shielding structure is used to expose the photoresist layer 208, so that the photoresist layer 208 on the dielectric layer etching unit 207 on the right is exposed to form a corresponding etching window, and then the dielectric layer 206 is etched through the etching window using an etching process to form a through hole 210 in the dielectric layer etching unit 207 on the right, and the through hole 210 exposes the pad 201 on the semiconductor chip 200 in the semiconductor chip unit 204 on the right. In this example, two dielectric layer etching units 207 are used as an example for explanation. In practice, there may be more than two dielectric layer etching units 207. At this time, continue this step until the dielectric layer 206 is completely patterned to form a patterned dielectric layer 211 (such as Fig.10 shown);

[0072] like Fig.11 As shown, a metal wiring layer is finally formed in the through hole 210 and on the surface of the patterned dielectric layer 211 by chemical vapor deposition, physical vapor deposition, sputtering, electroplating or chemical plating, and the metal wiring layer is etched to form a patterned metal wiring layer 212. The material of the metal wiring layer includes one or a combination of two or more of copper, aluminum, nickel, gold, silver and titanium.

[0073] like Figures 11 to 14 As shown, as an example, when the material of the dielectric layer 206 is selected to include one or a combination of two or more of PI and PBO, the method of forming the first rewiring layer 213 includes:

[0074] like Fig.12 As shown, a dielectric layer 206 is formed on the semiconductor chip 200;

[0075] like Fig.13 As shown, a photolithography process is directly applied to the dielectric layer 206. Specifically, a photomask 209 with a shielding structure is used to expose the dielectric layer 206, so that the dielectric layer etching unit 207 on the left is exposed to form a through hole 210 in the dielectric layer etching unit 207 on the left. The through hole 210 exposes the pad 201 on the semiconductor chip 200 in the semiconductor chip unit 204 on the left.

[0076] like Fig.14As shown, the relative direction between the photomask 209 with a shielding structure and the dielectric layer etching unit 207 is then adjusted, and then the photomask 209 with a shielding structure is used to expose the dielectric layer 206 to form a through hole 210 in the dielectric layer etching unit 207 on the right, and the through hole 210 exposes the pad 201 on the semiconductor chip 200 in the semiconductor chip unit 204 on the right. In this example, two dielectric layer etching units 207 are used as an example for explanation. In practice, there may be more than two dielectric layer etching units 207. At this time, continue this step until the dielectric layer 206 is completely patterned to form a patterned dielectric layer 211 (as shown in FIG. 2 ). Fig.10 shown);

[0077] like Fig.11 As shown, a metal wiring layer is finally formed in the through hole 210 and on the surface of the patterned dielectric layer 211 by chemical vapor deposition, physical vapor deposition, sputtering, electroplating or chemical plating, and the metal wiring layer is etched to form a patterned metal wiring layer 212. The material of the metal wiring layer includes one or a combination of two or more of copper, aluminum, nickel, gold, silver and titanium.

[0078] like Fig.15 and Fig.16 As shown, as an example, the rewiring layer 215 also includes at least one second rewiring layer 214 formed on the first rewiring layer 213, and the method for forming the second rewiring layer 214 includes: forming the dielectric layer 206 on the surface of the upper rewiring layer 213; etching the dielectric layer 206 using conventional photolithography and etching processes to form a patterned dielectric layer 211 (such as Fig.15 ), so as to form a through hole in the patterned dielectric layer 211 to expose the patterned metal wiring layer 212 of the previous layer; and form a patterned metal wiring layer 212 (such as Fig.16 shown).

[0079] like Fig.17 As shown, step 5) is finally performed to form metal bumps 216 on the rewiring layer 215 .

[0080] As an example, the metal bump 216 includes one of a gold-tin solder ball, a silver-tin solder ball, and a copper-tin solder ball, or the metal bump 216 includes a metal column and a solder ball formed on the metal column, preferably, the metal column is a copper column or a nickel column. In this embodiment, the metal bump 216 is a gold-tin solder ball, and its manufacturing steps include: first forming a gold-tin layer on the surface of the rewiring layer 215, and then using a high-temperature reflow process to reflow the gold-tin layer into a ball shape, and forming a gold-tin solder ball after cooling; or using a ball planting process to form a gold-tin solder ball.

[0081] like Fig.17 As shown, this embodiment also provides a fan-out wafer-level packaging structure, which can be prepared by the preparation method of the fan-out wafer-level packaging structure of the above embodiment. The beneficial effects that can be achieved by the fan-out wafer-level packaging structure can be found in the preparation method of the above embodiment, which will not be repeated below. The packaging structure includes:

[0082] Two or more semiconductor chips 200 with bonding pads 201, wherein the semiconductor chips 200 are arranged in a fan-out wafer array 203, and each of the semiconductor chips 200 has its own initial position;

[0083] A plastic encapsulation layer 205, covering the surface of the semiconductor chip 200 and between the semiconductor chips 200, each of the semiconductor chips 200 has its own offset position after plastic encapsulation, and the offset position has an offset distance relative to the initial position;

[0084] A rewiring layer 215 is formed on the semiconductor chip 200 to realize interconnection between the semiconductor chips 200. The rewiring layer 215 includes at least one first rewiring layer 213. The first rewiring layer 213 is formed on the surface of the semiconductor chip 200 and is aligned and connected with the pad 201 of the semiconductor chip 200.

[0085] Metal bumps 216 are formed on the rewiring layer 215 .

[0086] As an example, the rewiring layer 215 includes a patterned dielectric layer 211 and a patterned metal wiring layer 212. Preferably, the material of the patterned dielectric layer 211 includes one or a combination of two or more of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphorus silicon glass, fluorine-containing glass, and the material of the patterned metal wiring layer 212 includes one or a combination of two or more of copper, aluminum, nickel, gold, silver, and titanium.

[0087] As an example, the material of the plastic packaging layer 205 includes one of polyimide, silicone and epoxy resin.

[0088] In summary, the present embodiment provides a fan-out type wafer-level packaging structure and packaging method. When forming the first layer of rewiring layer, the fan-out type wafer array is divided into a plurality of etching units by dividing the units, and each etching unit is etched and opened one by one to form a through hole for exposing the semiconductor chip pad. The photolithography exposure direction in the photolithography process is readjusted each time the window is etched, which is equivalent to decomposing one alignment exposure into multiple alignment exposures. Each alignment exposure adjusts the exposure direction according to the offset distance and offset direction of the semiconductor chip in the etching unit where it is located, effectively improving the alignment accuracy of the photolithography process when forming the rewiring layer. Based on this high-precision photolithography alignment effect, the alignment accuracy of the rewiring layer formed subsequently can be effectively improved, thereby effectively improving the yield of wafer packaging; and the method only needs to set a light shielding structure on the photolithography mask to achieve the method, and the method is simple and feasible, and has strong operability. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0089] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A packaging method for a fan-out wafer-level packaging structure, It is characterized in that The packaging method comprises: Providing two or more semiconductor chips with bonding pads; Bonding the semiconductor chip to the bonding layer to form a fan-out wafer array, wherein the fan-out wafer array is divided into more than two semiconductor chip units, and each of the semiconductor chips has its own initial position; The semiconductor chips are packaged with a plastic packaging layer, each of the semiconductor chips has a respective offset position, and the offset position has an offset distance relative to the initial position; The adhesive layer is removed, and a rewiring layer is formed on the semiconductor chip to realize interconnection between the semiconductor chips; the rewiring layer includes at least one first rewiring layer, and the method for forming the first rewiring layer includes: forming a dielectric layer on the semiconductor chip; taking the area corresponding to each semiconductor chip unit as a dielectric layer etching unit, correspondingly, dividing the dielectric layer into more than two dielectric layer etching units, etching all the dielectric layer etching units one by one using a photolithography process to form a through hole in the dielectric layer to expose the pad of each semiconductor chip, wherein the photolithography exposure direction of the photolithography process is readjusted each time the dielectric layer etching unit is etched; forming a patterned metal wiring layer corresponding to the through hole in the through hole and on the dielectric layer; Metal bumps are formed on the rewiring layer.

2. The packaging method of the fan-out wafer-level packaging structure according to claim 1, Features: The adhesive layer is adhered to the supporting substrate; before forming the rewiring layer, the supporting substrate and the adhesive layer are removed simultaneously.

3. The packaging method of the fan-out wafer-level packaging structure according to claim 1, Features: The rewiring layer also includes at least one second rewiring layer formed on the first rewiring layer, and the method for forming the second rewiring layer includes: forming the dielectric layer on the surface of the upper rewiring layer; etching the dielectric layer using a photolithography process to form a through hole in the dielectric layer to expose the patterned metal wiring layer of the upper layer; forming a patterned metal wiring layer corresponding to the through hole in the through hole and on the dielectric layer.

4. The packaging method of the fan-out wafer-level packaging structure according to claim 1, Features: The adhesive layer includes one of an adhesive tape, an adhesive made by a spin coating process, or an epoxy resin.

5. The packaging method of the fan-out wafer-level packaging structure according to claim 1, Features: The material of the plastic sealing layer includes one of polyimide, silica gel and epoxy resin.

6. The packaging method of the fan-out wafer-level packaging structure according to claim 1, Features: The material of the dielectric layer includes one or a combination of two or more of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphosilicate glass, and fluorine-containing glass, and the material of the metal wiring layer includes one or a combination of two or more of copper, aluminum, nickel, gold, silver, and titanium.

7. A fan-out wafer-level packaging structure, It is characterized in that The packaging structure comprises: Two or more semiconductor chips with pads, the semiconductor chips are arranged in a fan-out wafer array, and each of the semiconductor chips has its own initial position; wherein an adhesive layer is formed under the pads, and an anti-reflection layer is formed on the pads; A plastic sealing layer, covering the surface of the semiconductor chip and between the semiconductor chips, each of the semiconductor chips has a respective offset position after plastic sealing, and the offset position has an offset distance relative to the initial position; A rewiring layer is formed on the semiconductor chip to realize interconnection between the semiconductor chips, and the rewiring layer includes at least one first rewiring layer, which is formed on the surface of the semiconductor chip and is aligned and connected with the pad of the semiconductor chip; Metal bumps are formed on the rewiring layer.

8. The fan-out wafer-level packaging structure according to claim 7, Features: The rewiring layer includes a patterned dielectric layer and a patterned metal wiring layer.

9. The fan-out wafer-level packaging structure according to claim 8, Features: The material of the patterned dielectric layer includes one or a combination of two or more of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphosilicate glass, and fluorine-containing glass; the material of the patterned metal wiring layer includes one or a combination of two or more of copper, aluminum, nickel, gold, silver, and titanium.

10. The fan-out wafer-level packaging structure according to claim 7, Features: The material of the plastic sealing layer includes one of polyimide, silica gel and epoxy resin.

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