Array substrate and preparation method thereof

Abstract

The present invention provides an array substrate and a method for preparing the same. The method for preparing the array substrate includes the following steps: sequentially forming a light shielding material layer, a buffer material layer and an active material layer on a substrate layer; patterning the light shielding material layer, the buffer material layer and the active material layer through the same half-tone mask process to form an active layer, a buffer layer and a light shielding layer; and preparing a conductive film layer and an insulating film layer on the substrate layer through a thin film transistor process. The array substrate and the method for preparing the same provided by the present invention can pattern the three film layers of the light shielding layer, the buffer layer and the active layer together through a yellow light process, which greatly reduces the number of times the yellow light process is used compared with the prior art.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor preparation, and in particular to an array substrate and a preparation method thereof. Background Art

[0002] With the development of liquid crystal display technology, the size of display screens is getting larger and larger. The carrier mobility of the traditional hydrogenated amorphous silicon (a-Si:H) thin film transistors is not high enough to drive large-size liquid crystal display panels. Generally speaking, the carrier mobility of metal oxide thin film transistors is significantly higher than that of a-Si:H thin film transistors. In order to improve the charging rate of thin film transistor devices, IGZO semiconductor layers gradually replace a-Si:H semiconductor layers and are used in the design of large-size liquid crystal panels.

[0003] However, at present, whether it is to prepare an array substrate containing an IGZO semiconductor layer or an array substrate containing a semiconductor layer formed by other metal oxides, each film layer needs to be subjected to processes such as deposition, exposure and development, etching, and stripping. However, as long as each process involves exposure and development, it will bring great consumption to the factory's production capacity and materials, and will also increase the production cycle time, greatly reduce production efficiency, and increase production costs.

[0004] Taking the array substrate of the top gate structure as an example, generally at least 7 process steps including exposure and development are required. Therefore, it is necessary to simplify the existing preparation process of the array substrate and save the number of process steps including exposure and development to achieve the purpose of saving production costs. Summary of the invention

[0005] The object of the present invention is to provide an array substrate and a method for manufacturing the same, so as to solve the technical problems of reduced production efficiency and excessively high production cost caused by an excessive number of photomasks in the existing TFT manufacturing process.

[0006] To achieve the above-mentioned purpose, the present invention provides a method for preparing an array substrate, which comprises the following steps: forming a shading material layer, a buffer material layer and an active material layer in sequence on a substrate layer; patterning the shading material layer, the buffer material layer and the active material layer through the same half-tone mask process to form an active layer, a buffer layer and a shading layer; and preparing a conductive film layer and an insulating film layer on the substrate layer through a thin film transistor process.

[0007] Furthermore, the steps of forming the active layer, the buffer layer and the light-shielding layer include: forming a photoresist material layer on a surface of the active material layer away from the buffer material layer; patterning the photoresist material layer through a half-tone mask process to form a stepped photoresist layer; and patterning the active material layer, the buffer material layer and the light-shielding material layer through a multi-etching process.

[0008] Furthermore, the array substrate has a first etching area, a second etching area connected to the first etching area, and a third etching area connected to the second etching area. The step of patterning the active material layer, the buffer material layer, and the light-shielding material layer includes: removing the active material layer in the first etching area by wet etching; removing the buffer material layer in the first etching area and the photoresist layer in the second etching area by dry etching; removing the light-shielding material layer in the first etching area and the active material layer in the second etching area by wet etching; and removing the photoresist layer in the third etching area.

[0009] Furthermore, a thickness of the photoresist layer in the second etching region is smaller than a thickness of the photoresist layer in the third etching region.

[0010] Furthermore, the steps of preparing the conductive film layer and the insulating film layer include: forming an insulating layer and a gate layer on the active layer by the same photolithography process; forming an interlayer dielectric layer on the substrate layer; and forming a source and drain layer on the interlayer dielectric layer.

[0011] Furthermore, the method for preparing the array substrate further includes the following steps: forming a passivation layer on the insulating film layer; forming a contact hole on the passivation layer by a photolithography process; and forming a pixel electrode layer on the passivation layer.

[0012] Furthermore, the method for preparing the array substrate further comprises the following step: forming a planar layer on the passivation layer.

[0013] The present invention also provides an array substrate, which is prepared by the array substrate preparation method as described above. The array substrate comprises a light shielding layer, a buffer layer, an active layer, a conductive film layer and an insulating film layer. The light shielding layer is arranged on a substrate layer. The buffer layer is arranged on a surface of the light shielding layer away from the light shielding layer. The active layer is arranged on a surface of the buffer layer away from the light shielding layer. The conductive film layer and the insulating film layer are arranged on the substrate layer.

[0014] Furthermore, the insulating film layer includes an insulating layer and an interlayer dielectric layer. The insulating layer is disposed on a surface of the active layer away from the buffer layer. The interlayer dielectric layer is disposed on the substrate layer and covers the light shielding layer, the buffer layer, the active layer and the buffer layer.

[0015] The conductive film layer includes a gate layer and a source-drain layer. The gate layer is arranged between the insulating layer and the interlayer dielectric layer. The source-drain layer is arranged on a surface of the interlayer dielectric layer away from the gate layer and is electrically connected to the active layer.

[0016] Furthermore, the array substrate further comprises a passivation layer and a contact hole. The passivation layer is disposed on the interlayer dielectric layer and covers the conductive film layer. The contact hole penetrates the passivation layer.

[0017] The advantages of the present invention are as follows: in the array substrate and the preparation method thereof provided by the present invention, the three film layers of the light shielding layer, the buffer layer and the active layer can be patterned together through a yellow light process, which greatly reduces the number of times the yellow light process is used compared with the existing technology, shortens the production cycle time, and thus improves production efficiency. At the same time, it also reduces the factory capacity and material loss, and reduces the production cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0019] Figure 1 is a schematic diagram of a layered structure of an array substrate in an embodiment of the present invention;

[0020] Figure 2 is a schematic diagram of a layered structure of an array substrate in an embodiment of the present invention;

[0021] Figure 3 is a schematic flow chart of a method for preparing an array substrate in an embodiment of the present invention;

[0022] Figure 4 This is a schematic diagram of a layered structure after a light shielding material layer is formed in step S10 in an embodiment of the present invention;

[0023] Figure 5 This is a schematic diagram of a layered structure after a buffer material layer is formed in step S10 in an embodiment of the present invention;

[0024] Figure 6 Schematic diagram of a layered structure after forming an active material layer in step S10 in an embodiment of the present invention;

[0025] Figure 7 Schematic diagram of the layered structure after the photoresist layer is formed in step S20 in an embodiment of the present invention;

[0026] Figure 8 Schematic diagram of the layered structure after the active material layer is patterned in step S30 in an embodiment of the present invention;

[0027] Fig. 9 Schematic diagram of the layered structure after the buffer layer is formed in step S30 in an embodiment of the present invention;

[0028] Fig.10 Schematic diagram of the layered structure after the light shielding layer and the active layer are formed in step S30 in an embodiment of the present invention;

[0029] Fig.11 Schematic diagram of the layered structure after the photoresist layer is removed in step S30 in an embodiment of the present invention;

[0030] Fig.12 Schematic diagram of a layered structure after forming an insulating material layer and a gate material layer in step S40 in an embodiment of the present invention;

[0031] Fig.13 Schematic diagram of a layered structure after forming an insulating layer and a gate layer in step S40 in an embodiment of the present invention;

[0032] Fig.14 Schematic diagram of a layered structure after an interlayer dielectric layer is formed in step S40 in an embodiment of the present invention;

[0033] Fig.15 Schematic diagram of the layered structure after deep holes and shallow holes are formed in step S40 in an embodiment of the present invention;

[0034] Fig.16 Schematic diagram of the layered structure after the source and drain layers are formed in step S40 in an embodiment of the present invention.

[0035] The components in the figure are shown as follows:

[0036] Array substrate 1; Substrate layer 10;

[0037] Light shielding layer 20; Buffer layer 30;

[0038] Active layer 40; First connecting portion 41;

[0039] A second connecting portion 42; A channel portion 43;

[0040] Insulating layer 50; Gate layer 60;

[0041] Interlayer dielectric layer 70; Source and drain layer 80;

[0042] Source layer 81; First lead 811;

[0043] A second pin 812; A drain layer 82;

[0044] A third pin 821; a passivation layer 90;

[0045] Planar layer 100; Contact hole 110;

[0046] First etching area 1A; Second etching area 1B;

[0047] The third etching area 1C; the photoresist layer 120;

[0048] Light shielding material layer 20'; Buffer material layer 30';

[0049] Active material layer 40'; Insulating material layer 50';

[0050] Gate material layer 60'; Deep hole 130;

[0051] Shallow hole 140. DETAILED DESCRIPTION

[0052] The preferred embodiments of the present invention are described below with reference to the drawings in the specification to prove that the present invention can be implemented. The embodiments of the invention can fully introduce the present invention to those skilled in the art, making its technical content clearer and easier to understand. The present invention can be embodied through many different forms of embodiments of the invention, and the protection scope of the present invention is not limited to the embodiments mentioned in the text.

[0053] In the drawings, components with the same structure are indicated by the same numerical reference numerals, and components with similar structures or functions are indicated by similar numerical reference numerals. The size and thickness of each component shown in the drawings are arbitrarily shown, and the present invention does not limit the size and thickness of each component. In order to make the illustration clearer, the thickness of the components is appropriately exaggerated in some places in the drawings.

[0054] In addition, the following descriptions of the various embodiments of the invention are made with reference to the attached diagrams to illustrate specific embodiments of the invention that the present invention can be implemented with. The directional terms mentioned in the present invention, such as "upper", "lower", "front", "back", "left", "right", "inner", "outer", "side", etc., are only with reference to the directions of the attached drawings. Therefore, the directional terms used are for better and clearer description and understanding of the present invention, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", "third", etc. are used for descriptive purposes only and cannot be understood as indicating or implying relative importance.

[0055] When some components are described as being "on" another component, the component may be directly placed on the other component; there may also be an intermediate component on which the component is placed, and the intermediate component is placed on the other component. When a component is described as being "mounted on" or "connected to" another component, the two may be understood to be directly "mounted on" or "connected", or one component may be indirectly "mounted on" or "connected to" another component via an intermediate component.

[0056] The present invention provides an array substrate 1, such as Figure 1As shown, the array substrate 1 includes a substrate layer 10, a light shielding layer 20, a buffer layer 30 and a thin film transistor structure layer.

[0057] The light shielding layer 20 is disposed on the substrate layer 10. The light shielding layer 20 is made of a conductive metal material and has a thickness of 500-10000 angstroms. The light shielding layer 20 is used to shield the active layer 40 in the thin film transistor structure layer from incident light entering from the substrate layer 10 side to prevent the light from affecting the operation of the active layer 40.

[0058] The buffer layer 30 is disposed on a surface of the light shielding layer 20 away from the substrate layer 10. The buffer layer 30 is made of inorganic materials such as silicon oxide and silicon nitride, and has a thickness of 1000-5000 angstroms. The buffer layer 30 is used to reduce the impact force on the display panel device during production and transportation, and to insulate and protect the light shielding layer 20.

[0059] like Figure 1 and Figure 2 As shown, the thin film transistor structure layer is arranged on the buffer layer 30, which includes a conductive film layer and an insulating film layer. The conductive film layer includes an active layer 40, a gate layer 60 and a source and drain layer 80, and the insulating film layer includes an insulating layer 50 and an interlayer dielectric layer 70. The insulating film layer is used to insulate and protect the conductive film layer to prevent short circuits between wirings.

[0060] The active layer 40 is disposed on a surface of the buffer layer 30 away from the light shielding layer 20, and includes a first connecting portion 41, a second connecting portion 42 and a channel portion 43. The first connecting portion 41 and the second connecting portion 42 are respectively disposed at two ends of the channel portion 43. The active layer 40 is made of metal oxide, and its thickness is 100-1000 angstroms. Preferably, the metal oxide can be one of semiconductor oxides such as indium gallium zinc oxide (IGZO), indium zinc tritium oxide (IZTO), indium gallium zinc tritium oxide (IGZTO), etc.

[0061] The insulating layer 50 is disposed on a surface of the active layer 40 away from the buffer layer 30 and corresponds to the channel portion 43 in the active layer 40. The insulating layer 50 has a thickness of 1000-3000 angstroms and is made of inorganic materials such as silicon oxide and silicon nitride. Specifically, the insulating layer 50 can be a single layer of silicon oxide, a single layer of silicon nitride, or a plurality of layers of silicon oxide material layers and a plurality of layers of silicon nitride material layers alternately stacked. The insulating layer 50 is used to insulate and separate the active layer 40 from the gate layer 60.

[0062] The gate layer 60 is disposed on a surface of the insulating layer 50 away from the active layer 40. The gate layer 60 has a thickness of 2000-10000 angstroms and is made of a conductive metal material. Specifically, the conductive metal material may be a single metal material or an alloy material having excellent conductive properties, such as molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti).

[0063] The interlayer dielectric layer 70 is arranged on the substrate layer 10, and covers the light shielding layer 20, the buffer layer 30, the active layer 40, the insulating layer 50 and the exposed surface of the gate layer 60. The thickness of the interlayer dielectric layer 70 on the gate layer 60 is 2000-10000 angstroms. The interlayer dielectric layer 70 is also made of inorganic materials such as silicon oxide and silicon nitride. Specifically, the interlayer dielectric layer 70 can also be a single layer of silicon oxide, a single layer of silicon nitride, or a multi-layer silicon oxide material layer and a multi-layer silicon nitride material layer alternately stacked. The interlayer dielectric layer 70 is used to insulate and separate the gate layer 60 from the source and drain layer 80.

[0064] The source-drain electrode layer 80 is disposed on a surface of the interlayer dielectric layer 70 away from the gate layer 60. The source-drain electrode layer 80 has a thickness of 2000-10000 angstroms and is also made of a conductive metal material. Specifically, the conductive metal material may be a single metal material or an alloy material having excellent conductive properties, such as molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti).

[0065] The source-drain electrode layer 80 includes a source electrode layer 81 and a drain electrode layer 82. The source electrode layer 81 is located above the first connection portion 41, and a first pin 811 and a second pin 812 extend from the bottom surface thereof. The first pin 811 passes through the interlayer dielectric layer 70 to be electrically connected to the first connection portion 41. The second pin 812 passes through the interlayer dielectric layer 70 and the buffer layer 30 in sequence to be electrically connected to the light shielding layer 20, thereby shielding external electrons from affecting the electrical properties of the active layer 40. The drain electrode layer 82 is located above the second connection portion 42, and a third pin 821 extends from the bottom surface thereof. The third pin 821 passes through the interlayer dielectric layer 70 to be electrically connected to the second connection portion 42.

[0066] When current and voltage are passed through the gate layer 60 in the thin film transistor structure layer, an electric field will be generated, which will cause the surface of the active layer 40 to generate induced charges and change the width of the channel portion 43 in the active layer 40, thereby achieving the purpose of controlling the current of the source and drain layer 80 and realizing the driving of each light-emitting pixel in the display panel.

[0067] The array substrate 1 further includes a passivation layer 90 and a planarization layer 100 .

[0068] The passivation layer 90 is disposed on the interlayer dielectric layer 70 and covers the source-drain electrode layer 80. The thickness of the passivation layer 90 is 1000-5000 angstroms, and it is made of inorganic materials such as silicon oxide and silicon nitride. Specifically, the passivation layer 90 can also be a single layer of silicon oxide, a single layer of silicon nitride, or a multi-layer silicon oxide material layer and a multi-layer silicon nitride material layer alternately stacked. The passivation layer 90 is used to passivate and protect the source-drain electrode layer 80.

[0069] The planarization layer 100 is disposed on a surface of the passivation layer 90 away from the interlayer dielectric layer 70 , and is used to planarize the surface of the array substrate 1 .

[0070] The passivation layer 90 and the planar layer 100 have a contact hole 110. The contact hole 110 passes through the passivation layer 90 and the planar layer 100 and corresponds to the source electrode layer 81 in the source-drain electrode layer 80. The pixel electrode can be electrically connected to the thin film transistor structure layer through the contact hole 110.

[0071] The present invention also provides a method for preparing an array substrate 1, which is used to prepare the array substrate 1 as described above. The process of the method for preparing the array substrate 1 is as follows: Figure 3 As shown, it includes the following steps:

[0072] Step S10) forming a light shielding material layer 20', a buffer material layer 30' and an active material layer 40':

[0073] A glass substrate is prepared as the substrate layer 10, and a layer of metal material with a film thickness of 500-10000 angstroms is deposited on the substrate layer 10 after cleaning to form a Figure 4 A layer of inorganic material with a film thickness of 1000-5000 angstroms is deposited on a surface of the light shielding material layer 20' away from the substrate layer 10 to form a Figure 5 A layer of metal oxide with a film thickness of 100-1000 angstroms is deposited on a surface of the buffer material layer 30' away from the light shielding material layer 20' to form a Figure 6 The active material layer 40' is shown in FIG.

[0074] Step S20) forming a photoresist layer 120:

[0075] like Figure 7 As shown, the array substrate 1 comprises a first etching region 1A, a second etching region 1B connected to the first etching region 1A, and a third etching region 1C connected to the second etching region 1B.

[0076] A photoresist material layer is coated on a surface of the active material layer 40' away from the buffer material layer 30', and the photoresist material layer is patterned by a half-tone yellow light process, the photoresist material layer in the first etching area 1A is removed, and a part of the photoresist material layer in the second etching area 1B and the entire photoresist material layer in the third etching area 1C are retained to form a Figure 7 The photoresist layer 120 shown in FIG. The thickness of the photoresist layer 120 in the second etching area 1B is less than the thickness of the photoresist layer 120 in the third etching area 1C, thereby forming a stepped photoresist layer 120 .

[0077] Step S30) forming a light shielding layer 20, a buffer layer 30 and an active layer 40:

[0078] The active material layer 40' is patterned by wet etching to remove the active material layer 40' in the first etching area 1A, forming Figure 8 The buffer material layer 30' and the photoresist layer 120 are then patterned by dry etching, the buffer material layer 30' in the first etching area 1A and the photoresist layer 120 in the second etching area 1B are removed, and the thickness of the photoresist layer 120 in the third etching area 1C is reduced to form a Fig. 9 The buffer layer 30 and the photoresist layer 120 are shown in FIG.

[0079] The light shielding material layer 20' is patterned by wet etching, and the light shielding material layer 20' in the first etching area 1A and the active material layer 40' in the second etching area 1B are removed to form a Fig.10 The light shielding layer 20 and the active layer 40 are shown in FIG.

[0080] The photoresist layer 120 in the third etching area 1C is stripped to form Fig.11 The layered structure described in .

[0081] Step S40) preparing a conductive film layer and an insulating film layer:

[0082] A layer of inorganic material with a film thickness of 1000-3000 angstroms and a layer of metal material with a film thickness of 2000-10000 angstroms are sequentially deposited on the active layer 40 to form a Fig.12 The insulating material layer 50' and the gate material layer 60' are shown in FIG. The gate material layer 60' is patterned by a yellow light etching process, and then the insulating material layer 50' is patterned by a dry etching method to form a Fig.13 The insulating layer 50 and the gate layer 60 described in FIG.

[0083] While dry etching the insulating material layer 50 ′, the active layer 40 is plasma treated to form a first connection portion 41 and a second connection portion 42 with a lower resistance on the active layer 40 , while the active layer 40 below the insulating layer 50 is not treated and maintains semiconductor characteristics to form a channel portion 43 .

[0084] A layer of inorganic material covering the exposed surfaces of the light shielding layer 20, the buffer layer 30, the active layer 40, the insulating layer 50 and the gate layer 60 is deposited on the substrate layer 10 to form a Fig.14 The interlayer dielectric layer 70 is shown in FIG.

[0085] A deep hole 130 and two shallow holes 140 are formed in the interlayer dielectric layer 70 and the buffer layer 30 by photolithography and etching processes. Fig.15 As shown, the deep hole 130 penetrates the interlayer dielectric layer 70 and the buffer layer 30 to the surface of the light shielding layer 20. The shallow hole 140 corresponds to the first connecting portion 41 and the second connecting portion 42, respectively, and penetrates the interlayer dielectric layer to the surface of the active layer 40.

[0086] A layer of metal material with a film thickness of 2000-10000 angstroms is deposited on a surface of the interlayer dielectric layer away from the gate layer 60, and the metal material fills the deep hole 130 and the shallow hole 140 to form the source and drain electrode material layer. The source and drain electrode material layer is patterned to form Fig.16 The source and drain layer 80 is shown in FIG.

[0087] The gate layer 60 and the source-drain layer 80 are both conductive film layers, and the insulating layer 50 and the interlayer dielectric layer 70 are both insulating film layers.

[0088] Step S50) preparing the passivation layer 90 and the planarization layer 100:

[0089] A layer of inorganic material covering the source and drain electrode layer 80 is deposited on the interlayer dielectric layer 70 to form the passivation layer 90. The planarization layer 100 is formed on a surface of the passivation layer 90 away from the interlayer dielectric layer 70. The passivation layer 90 and the planarization layer 100 are patterned, and contact holes 110 are prepared in the passivation layer 90 and the planarization layer 100 to form a Figure 1 The array substrate 1 shown in FIG.

[0090] In the array substrate and the preparation method thereof provided in the embodiments of the present invention, the light shielding layer, the buffer layer and the active layer can be patterned by only one yellow light process, which greatly reduces the number of yellow light processes used compared with the prior art, shortens the production cycle time, and thus improves production efficiency. At the same time, it also reduces factory capacity and material loss, and reduces production costs.

[0091] In other embodiments of the present invention, an array substrate without a flat layer is also provided. Accordingly, compared with the preparation method provided in the embodiment of the present invention, the preparation method of the array substrate omits the step of "preparing a flat layer", and the remaining layered structure and preparation method are similar to the array substrate and preparation method provided in the embodiment of the present invention, so no further details are given here. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0092] Although the present invention is described herein with reference to specific embodiments, it should be understood that these embodiments are merely examples of the principles and applications of the present invention. It should therefore be understood that many modifications may be made to the exemplary embodiments and that other arrangements may be devised without departing from the spirit and scope of the present invention as defined by the appended claims. It should be understood that the various dependent claims and features described herein may be combined in a manner different from that described in the original claims. It should also be understood that features described in conjunction with individual embodiments may be used in other described embodiments.

Claims

1. A method for preparing an array substrate, characterized in that: The following steps are involved: forming a light shielding material layer, a buffer material layer and an active material layer in sequence on a substrate layer; Patterning the light shielding material layer, the buffer material layer and the active material layer through a same half-tone mask process to form an active layer, a buffer layer and a light shielding layer; Prepare a conductive film layer and an insulating film layer on the substrate layer by a thin film transistor process; The steps of forming the active layer, the buffer layer and the light shielding layer include: forming a photoresist material layer on a surface of the active material layer away from the buffer material layer; Patterning the photoresist material layer by a half-tone mask process to form a stepped photoresist layer; patterning the active material layer, the buffer material layer and the light shielding material layer through a multi-pass etching process; The array substrate comprises a first etching region, a second etching region connected to the first etching region, and a third etching region connected to the second etching region; The step of patterning the active material layer, the buffer material layer and the light shielding material layer comprises: removing the active material layer in the first etching area by wet etching; removing the buffer material layer in the first etching area and the photoresist layer in the second etching area by dry etching; removing the light shielding material layer in the first etching area and the active material layer in the second etching area by wet etching; The photoresist layer in the third etching area is removed.

2. The method for preparing an array substrate according to claim 1, wherein: The thickness of the photoresist layer in the second etching region is smaller than the thickness of the photoresist layer in the third etching region.

3. The method for preparing an array substrate according to claim 1, wherein: The steps of preparing the conductive film layer and the insulating film layer include: forming an insulating layer and a gate layer on the active layer by a same photolithography process; forming an interlayer dielectric layer on the substrate layer; A source-drain layer is formed on the interlayer dielectric layer.

4. The method for preparing an array substrate according to claim 1, wherein: The following steps are also included: forming a passivation layer on the insulating film layer; forming a contact hole on the passivation layer by a photolithography process; A pixel electrode layer is formed on the passivation layer.

5. The method for preparing an array substrate according to claim 4, wherein: The following steps are also included: A planarization layer is formed on the passivation layer.

6. An array substrate, characterized in that: The array substrate is manufactured by the method for manufacturing an array substrate according to any one of claims 1 to 5; the array substrate comprises: A light shielding layer is provided on a substrate layer; A buffer layer is disposed on a surface of the light shielding layer away from the light shielding layer; An active layer is disposed on a surface of the buffer layer away from the light shielding layer; The conductive film layer and the insulating film layer are arranged on the substrate layer.

7. The array substrate according to claim 6, characterized in that: The insulating film layer comprises: An insulating layer, disposed on a surface of the active layer away from the buffer layer; an interlayer dielectric layer, disposed on the substrate layer and covering the light shielding layer, the buffer layer, the active layer and the buffer layer; The conductive film layer comprises: A gate layer, disposed between the insulating layer and the interlayer dielectric layer; The source-drain electrode layer is disposed on a surface of the interlayer dielectric layer away from the gate layer and is electrically connected to the active layer.

8. The array substrate according to claim 7, characterized in that: Also includes; A passivation layer, disposed on the interlayer dielectric layer and covering the conductive film layer; A contact hole penetrates the passivation layer.

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