Array substrate and display panel
By designing the first gate electrode on the array substrate to cover the conductive channel and block backlight light, the problem of increased leakage current caused by backlight light in the prior art is solved, and lower leakage current and better thin film transistor shutdown performance are achieved. .
Patent Information
- Application Number
- CN202111555031.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2021-12-17
- Publication Date
- 2024-12-13
- Estimated Expiration
- 2041-12-17
AI Technical Summary
The existing array substrates are designed to design the gate electrode of the thin film transistor and the vertical channel structure on the same horizontal plane, resulting in an increase in leakage current under the influence of backlight light, making it difficult to completely close.
By designing the orthogonal projection of the first gate electrode on the substrate on the array substrate to cover the first conductive channel, the backlight illumination is blocked and the leakage current is reduced.
It effectively avoids the impact of backlight illumination on the conductive channel, reduces the leakage current of the array substrate, and improves the shutdown performance of the thin film transistor.
Smart Images
Figure CN114335183B_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of display technology, and in particular to an array substrate and a display panel. Background Art
[0002] In the panel manufacturing process, the quality design of thin film transistor devices is particularly important. There is now a technical solution that changes the horizontal channel structure formed by the source and drain electrodes in the thin film transistor device into a vertical channel structure, and sets the gate of the thin film transistor and the vertical channel structure on the same horizontal plane. On the one hand, the above technical solution is conducive to reducing the occupied area of the thin film transistor device on the substrate and improving the pixel aperture ratio. On the other hand, by controlling the length of the gate in the vertical direction, the length of the vertical channel can be increased, thereby increasing the conduction current of the thin film transistor device.
[0003] However, the above technical solution has the following technical defects: since the gate of the thin film transistor and the vertical channel structure are designed on the same horizontal plane, the active layer is close to the glass substrate, which is easily affected by backlight, causing a sharp increase in the leakage current of the thin film transistor and making it difficult to completely shut down the thin film transistor. Summary of the invention
[0004] The present application provides an array substrate and a display panel to solve the technical problem of large leakage current of the existing array substrate.
[0005] The present application provides an array substrate, which includes:
[0006] substrate;
[0007] a first gate electrode, the first gate electrode being disposed on the substrate;
[0008] A first insulating layer, wherein the first insulating layer is disposed on the first gate electrode and has a first through hole;
[0009] a first electrode, the first electrode being disposed on the first insulating layer;
[0010] a second insulating layer, wherein the second insulating layer is disposed on the first insulating layer and covers the first electrode, and the second insulating layer is provided with a second through hole and a third through hole, and the first through hole is connected to the second through hole;
[0011] a second gate electrode, the second gate electrode being disposed in the first through hole and the second through hole and connected to the first gate electrode;
[0012] A first conductive channel, wherein the first conductive channel is disposed in the third through hole and connected to the first electrode;
[0013] a second electrode, the second electrode is disposed on the second insulating layer and connected to the first conductive channel; wherein,
[0014] The orthographic projection of the first electrode on the substrate covers the orthographic projection of the first conductive channel on the substrate.
[0015] Optionally, in some embodiments of the present application, the first gate electrode and the second gate electrode layer are arranged perpendicular to each other.
[0016] Optionally, in some embodiments of the present application, the array substrate further includes a first connecting electrode, a fourth through hole is provided on the first conductive channel, the first connecting electrode is arranged in the fourth through hole, and one end of the first connecting electrode is connected to the first electrode.
[0017] Optionally, in some embodiments of the present application, the first surface of the first electrode is in contact with the first surface of the first conductive channel.
[0018] Optionally, in some embodiments of the present application, the array substrate also includes a second conductive channel, the second insulating layer is provided with a fifth through hole, the second conductive channel is arranged in the fifth through hole, the second conductive channel is connected to the first conductive channel, and the second conductive channel is located between the first electrode and the second gate electrode, and the second conductive channel is insulated from the second gate electrode.
[0019] Optionally, in some embodiments of the present application, one end of the second conductive channel is connected to the first electrode.
[0020] Optionally, in some embodiments of the present application, the other end of the second conductive channel is connected to the second electrode.
[0021] Optionally, in some embodiments of the present application, the first conductive channel and the second conductive channel are stacked.
[0022] Optionally, in some embodiments of the present application, the array substrate also includes a second connecting electrode, the second connecting electrode is arranged on the first conductive channel, the second electrode is arranged on the second connecting electrode, and the orthographic projection of the second gate electrode in the layer extension direction covers the orthographic projection of the second connecting electrode in the layer extension direction.
[0023] Optionally, in some embodiments of the present application, the first surface of the second conductive channel is connected to the first surface of the second connecting electrode.
[0024] Optionally, in some embodiments of the present application, the second surface of the second conductive channel is connected to the first surface of the second electrode.
[0025] Optionally, in some embodiments of the present application, the second electrode covers the second conductive channel.
[0026] Optionally, in some embodiments of the present application, the first conductive channel is an oxide semiconductor material, and the first insulating layer and the second insulating layer are inorganic insulating materials.
[0027] Optionally, in some embodiments of the present application, the second conductive channel is made of oxide semiconductor material.
[0028] Correspondingly, the present application also provides a display panel, which includes the above-mentioned array substrate and also includes a pixel electrode, wherein the pixel electrode is arranged on the second electrode and the pixel electrode is connected to the second electrode.
[0029] Optionally, in some embodiments of the present application, a passivation layer is further included, wherein the passivation layer is located between the pixel electrode and the second electrode, and the pixel electrode is connected to the second electrode through a via hole on the passivation layer.
[0030] The present application provides an array substrate and a display panel, wherein the array substrate comprises: a substrate;
[0031] A first gate electrode, the first gate electrode is arranged on the substrate; a first insulating layer, the first insulating layer is arranged on the first gate electrode, and the first insulating layer is provided with a first through hole; a first electrode, the first electrode is arranged on the first insulating layer; a second insulating layer, the second insulating layer is arranged on the first insulating layer and covers the first electrode, and the second insulating layer is provided with a second through hole and a third through hole, the first through hole is connected to the second through hole; a second gate electrode, the second gate electrode is arranged in the first through hole and the second through hole, and is connected to the first gate electrode; a first conductive channel, the first conductive channel is arranged in the third through hole and is connected to the first electrode; a second electrode, the second electrode is arranged on the second insulating layer and is connected to the first conductive channel; wherein the orthographic projection of the first electrode on the substrate covers the orthographic projection of the first conductive channel on the substrate. In the present application, by using the orthographic projection of the first gate electrode on the substrate to cover the orthographic projection of the first conductive channel on the substrate, the first gate electrode can block backlight illumination, thereby avoiding the influence of backlight illumination on the first conductive channel, and reducing the leakage current of the array substrate. BRIEF DESCRIPTION OF THE DRAWINGS
[0032] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.
[0033] Figure 1 A first structural schematic diagram of the array substrate provided in this application;
[0034] Figure 2 A second structural schematic diagram of the array substrate provided in this application;
[0035] Figure 3 A third structural schematic diagram of the array substrate provided in this application;
[0036] Figure 4 A fourth structural schematic diagram of the array substrate provided in this application;
[0037] Figure 5 A fifth structural schematic diagram of the array substrate provided in this application;
[0038] Figure 6 A schematic diagram of a display panel provided in this application. DETAILED DESCRIPTION
[0039] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of this application.
[0040] In the description of the present application, it should be understood that the terms "upper", "lower", "front", "back", "left", "right", "inside", "outside", etc. indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the said features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.
[0041] The present application provides an array substrate and a display panel, which are described in detail below. It should be noted that the description order of the following embodiments is not intended to limit the preferred order of the embodiments of the present application.
[0042] See also Figure 1 , Figure 1 The present application provides an array substrate 100 , which includes a substrate 10 , a first gate electrode 20 , a first insulating layer 30 , a first electrode 40 , a second insulating layer 50 , a first conductive channel 60 , a second gate electrode 70 and a second electrode 80 .
[0043] Specifically, the first electrode 40 and the second electrode 80 in the above array substrate provided in the present application are equivalent to the source electrode or the drain electrode in the prior art. In specific implementation, the first electrode can be used as the source electrode and the second electrode can be used as the drain electrode, or the second electrode can be used as the source electrode and the first electrode can be used as the drain electrode, which is not limited here. That is, the first electrode 40 is the source electrode and the second electrode 80 is the drain electrode; or the first electrode 40 is the drain electrode and the second electrode 80 is the source electrode.
[0044] Among them, the first gate electrode 20 is arranged on the substrate 10, the first insulating layer 30 is arranged on the first gate electrode 20, and the first insulating layer 30 is provided with a first through hole, and the first electrode 40 is arranged on the first insulating layer 30; the second insulating layer 50 is arranged on the first insulating layer 30 and covers the first electrode 40, and the second insulating layer 50 is provided with a second through hole and a third through hole, and the first through hole is connected to the second through hole; the second gate electrode 70 is arranged in the first through hole and the second through hole, and is connected to the first gate electrode 20.
[0045] The first conductive channel 60 is arranged in the third through hole and connected to the first electrode 40; the second electrode 80 is arranged on the second insulating layer 50 and connected to the first conductive channel 60; wherein the orthographic projection of the first electrode 20 on the substrate 10 covers the orthographic projection of the first conductive channel 60 on the substrate 10.
[0046] The present application sets the extension direction of the second gate electrode to be the same as the extension direction of the first conductive channel, thereby controlling the length of the second gate electrode in the vertical direction, thereby increasing the length of the first conductive channel, thereby increasing the conduction current of the array substrate device. In addition, the present application also uses the orthographic projection of the first gate electrode on the substrate to cover the orthographic projection of the first conductive channel on the substrate, and the first gate electrode can block backlight illumination, thereby avoiding the influence of backlight illumination on the first conductive channel, and reducing the leakage current of the array substrate.
[0047] In some embodiments, in order to improve processing efficiency and reduce material costs, the first gate electrode 20 and the second gate electrode 70 are arranged perpendicular to each other. Specifically, the first gate electrode 20 is arranged horizontally, and the second gate electrode 70 is arranged vertically.
[0048] Also, please refer to Figure 6 , Figure 6 is a schematic diagram of a display panel provided in the present application. The present application also provides a display panel 1000, which includes the above-mentioned array substrate 100 provided in the present application. The implementation of the display panel can refer to the above-mentioned embodiment of the array substrate, and the repeated parts will not be repeated.
[0049] The display panel 1000 further includes a pixel electrode 200 . The pixel electrode 200 is disposed on the second electrode 80 , and the pixel electrode 200 is connected to the second electrode 80 .
[0050] In some embodiments, the display panel 1000 further includes a passivation layer 300 , wherein the passivation layer 300 is located between the pixel electrode 200 and the second electrode 80 , and the pixel electrode 200 is connected to the second electrode 80 through a via hole on the passivation layer 300 .
[0051] Specifically, the array substrate provided in the present application can be applied to liquid crystal display panels, OLED display devices, and other organic electroluminescent devices, which are not limited here.
[0052] See also Figure 2 , Figure 2 is a second structural diagram of the array substrate provided in this application. Figure 1 The provided array substrate is different in that the array substrate 100 further includes a first connecting electrode 41 , a fourth through hole is provided on the first conductive channel 60 , the first connecting electrode 41 is arranged in the fourth through hole, and one end of the first connecting electrode 41 is connected to the first electrode 40 .
[0053] By providing the first connecting electrode, the overlapping length of the second gate electrode and the first electrode and the first connecting electrode can be increased, thereby improving the on-state current of the array substrate.
[0054] In some embodiments, the orthographic projection of the first electrode 40 on the substrate 10 is staggered from the orthographic projection of the first gate electrode 20 on the substrate 10. In addition, the first connecting electrode 41 and the first electrode 40 are disposed perpendicular to each other.
[0055] In addition, in some embodiments, the first surface of the first electrode 40 is connected to the first surface of the first conductive channel 60. This can further increase the connection area between the conductive channel and the first electrode, and improve the connection stability between the conductive channel of the array substrate and the first electrode.
[0056] See also Figure 3 , Figure 3 is a third structural schematic diagram of the array substrate provided in this application. Figure 1 The provided array substrate is different in that the array substrate also includes a second conductive channel 90, the second insulating layer 50 is provided with a fifth through hole, the second conductive channel 90 is arranged in the fifth through hole, the second conductive channel 90 is connected to the first conductive channel 60, and the second conductive channel 90 is located between the first electrode 40 and the second gate electrode 70, and the second conductive channel 90 is insulated from the second gate electrode 70.
[0057] By providing the second conductive channel between the first electrode and the second gate electrode, the insulation effect between the first gate electrode and the first electrode can be enhanced, thereby avoiding a short circuit between the second gate electrode and the first electrode.
[0058] In some embodiments, one end of the second conductive channel 90 is connected to the first electrode 40. Specifically, the side surface of the lower end of the second conductive channel 90 is connected to the first electrode 40, which can further increase the connection area between the conductive channel and the first electrode, and improve the connection stability between the conductive channel of the array substrate and the first electrode.
[0059] In some embodiments, the other end of the second conductive channel 90 is connected to the second electrode 80. Specifically, the end surface of the upper end of the second conductive channel 90 is connected to the second electrode 80, which can further increase the connection area between the conductive channel and the second electrode, and improve the connection stability between the conductive channel of the array substrate and the second electrode.
[0060] In addition, in some embodiments, the first conductive channel 60 and the second conductive channel 90 are stacked in sequence. The stacked first conductive channel and the second conductive channel can reduce the occupied space and maximize the contact area between the first conductive channel and the second conductive channel.
[0061] Furthermore, in a specific implementation, the array substrate provided in the present application may be an oxide array substrate, and the first conductive channel 60 and the second conductive channel 90 of the array substrate may be oxide semiconductor materials such as indium gallium zinc oxide, indium gallium tin oxide oxide, indium zinc oxide, etc. Correspondingly, the first insulating layer 30 and the second insulating layer 50 in the array substrate device may include inorganic insulating materials such as silicon dioxide, silicon nitride, silicon oxynitride, aluminum oxide, and titanium oxide.
[0062] Of course, in a specific implementation, the array substrate provided by the present application can also be a low-temperature polycrystalline silicon array substrate, that is, the first conductive channel 60 and the second conductive channel 90 of the array substrate can be amorphous silicon, polycrystalline silicon or microcrystalline silicon materials, and correspondingly, the first insulating layer 30 and the second insulating layer 50 in the array substrate device can be organic insulating materials such as resin-based insulating materials and acrylic-based insulating materials.
[0063] See also Figure 4 , Figure 4 is a fourth structural diagram of the array substrate provided in the present application. Figure 1 The provided array substrate is different in that the array substrate also includes a second connecting electrode 81, the second connecting electrode 81 is arranged on the first conductive channel 60, the second electrode 80 is arranged on the second connecting electrode 81, and the orthographic projection of the second gate electrode 70 in the layer extension direction covers the orthographic projection of the second connecting electrode 81 in the layer extension direction.
[0064] The present application adds a second connecting electrode and covers the orthographic projection of the second gate electrode in the layer extension direction with the orthographic projection of the second connecting electrode in the layer extension direction, thereby increasing the overlapping length of the second gate electrode and the second connecting electrode, thereby improving the on-state current of the array substrate.
[0065] See also Figure 5 , Figure 5 is a fifth structural diagram of the array substrate provided in the present application. Figure 1 The provided array substrate is different in that the array substrate 100 further includes a first connecting electrode 41 , a fourth through hole is provided on the first conductive channel 60 , the first connecting electrode 41 is arranged in the fourth through hole, and one end of the first connecting electrode 41 is connected to the first electrode 40 .
[0066] By providing the first connecting electrode, the overlapping length of the second gate electrode and the first electrode and the first connecting electrode can be increased, thereby improving the on-state current of the array substrate.
[0067] Further, in some embodiments, the array substrate 100 also includes a second conductive channel 90, the second insulating layer 50 is provided with a fifth through hole, the second conductive channel 90 is arranged in the fifth through hole, the second conductive channel 90 is connected to the first conductive channel 60, and the second conductive channel 90 is located between the first electrode 40 and the second gate electrode 70, and the second conductive channel 90 is insulated from the second gate electrode 70.
[0068] By providing the second conductive channel between the first electrode and the second gate electrode, the insulation effect between the first gate electrode and the first electrode can be enhanced, thereby avoiding a short circuit between the second gate electrode and the first electrode.
[0069] Furthermore, the second conductive channel 90 is located between the first connecting electrode 41 and the second gate electrode 70 .
[0070] In addition, in some embodiments, the first conductive channel 60 and the second conductive channel 90 are stacked in sequence. The stacked first conductive channel and the second conductive channel can reduce the occupied space and maximize the contact area between the first conductive channel and the second conductive channel.
[0071] Further, in some embodiments, one end of the second conductive channel 90 is connected to the first electrode 40. Specifically, the other end of the first connection electrode 41 is connected to one end of the second conductive channel 90, so that one end of the second conductive channel can be connected to the first electrode.
[0072] In addition, the other end of the second conductive channel 90 is connected to the second electrode 80. Specifically, the end surface of the upper end of the second conductive channel 90 is connected to the second electrode 80. Moreover, the first electrode 40 is connected to the first conductive channel through the first connecting electrode, which can increase the connection area between the first electrode, the second electrode and the conductive channel, and improve the connection stability between the electrode and the conductive channel.
[0073] In some embodiments, the orthographic projection of the first electrode 40 on the substrate 10 is staggered from the orthographic projection of the first gate electrode 20 on the substrate 10 .
[0074] In addition, in some embodiments, the first surface of the first electrode 40 is connected to the first surface of the first conductive channel 60. This can further increase the connection area between the conductive channel and the first electrode, and improve the connection stability between the conductive channel of the array substrate and the first electrode.
[0075] Furthermore, the array substrate 100 also includes a second connecting electrode 81, which is arranged on the first conductive channel 60, and the second electrode 80 is arranged on the second connecting electrode 81, and the orthographic projection of the second gate electrode 70 in the layer extension direction covers the orthographic projection of the second connecting electrode 81 in the layer extension direction.
[0076] The present application adds a second connecting electrode and covers the orthographic projection of the second gate electrode in the layer extension direction with the orthographic projection of the second connecting electrode in the layer extension direction, thereby increasing the overlapping length of the second gate electrode and the second connecting electrode, thereby improving the on-state current of the array substrate.
[0077] In some embodiments, the first surface of the second conductive channel 90 is connected to the first surface of the second connection electrode 71. The second surface of the second conductive channel 90 is connected to the first surface of the second electrode 80. The connection area between the conductive channel and the second electrode can be further increased, which can improve the connection stability between the conductive channel of the array substrate and the second electrode. The first surface and the second surface of the second conductive channel 90 are adjacent and perpendicular to each other.
[0078] Furthermore, the second electrode 80 covers the second conductive channel 90. This can prevent the second conductive channel from being exposed and reduce the number of insulating layers.
[0079] The above is a detailed introduction to an array substrate and a display panel provided in an embodiment of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for technical personnel in this field, according to the idea of the present application, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.
Claims
1. An array substrate, characterized in that: include: substrate; a first gate electrode, the first gate electrode being disposed on the substrate; A first insulating layer, wherein the first insulating layer is disposed on the first gate electrode and has a first through hole; a first electrode, the first electrode being disposed on the first insulating layer; a second insulating layer, wherein the second insulating layer is disposed on the first insulating layer and covers the first electrode, and the second insulating layer is provided with a second through hole and a third through hole, and the first through hole is connected to the second through hole; a second gate electrode, the second gate electrode being disposed in the first through hole and the second through hole and connected to the first gate electrode; A first conductive channel, wherein the first conductive channel is disposed in the third through hole and connected to the first electrode; a second electrode, the second electrode is disposed on the second insulating layer and connected to the first conductive channel; wherein, The orthographic projection of the first gate electrode on the substrate covers the orthographic projection of the first conductive channel on the substrate; The extension direction of the second gate electrode is arranged to be the same as the extension direction of the first conductive channel; The array substrate further includes a first connecting electrode, a fourth through hole is provided on the first conductive channel, the first connecting electrode is arranged in the fourth through hole, and one end of the first connecting electrode is connected to the first electrode; The orthographic projection of the first electrode on the substrate is staggered from the orthographic projection of the first gate electrode on the substrate, and the first connecting electrode and the first electrode are arranged perpendicular to each other; The first surface of the first electrode is in contact with the first surface of the first conductive channel.
2. The array substrate according to claim 1, characterized in that: The array substrate also includes a second conductive channel, the second insulating layer is provided with a fifth through hole, the second conductive channel is arranged in the fifth through hole, the second conductive channel is connected to the first conductive channel, and the second conductive channel is located between the first electrode and the second gate electrode, and the second conductive channel is insulated from the second gate electrode.
3. The array substrate according to claim 2, characterized in that: One end of the second conductive channel is connected to the first electrode; And / or, the other end of the second conductive channel is connected to the second electrode.
4. The array substrate according to claim 2, characterized in that: The first conductive channel and the second conductive channel are stacked.
5. The array substrate according to claim 2, characterized in that: The array substrate also includes a second connecting electrode, which is arranged on the first conductive channel, and the second electrode is arranged on the second connecting electrode, and the orthographic projection of the second gate electrode in the plane extension direction covers the orthographic projection of the second connecting electrode in the plane extension direction.
6. The array substrate according to claim 5, characterized in that: The second conductive channel is located between the second connecting electrode and the second gate electrode.
7. The array substrate according to claim 6, characterized in that: The second electrode covers the second conductive channel.
8. A display panel, characterized in that: The array substrate comprises the array substrate as claimed in any one of claims 1 to 7, and further comprises a pixel electrode, wherein the pixel electrode is arranged on the second electrode and the pixel electrode is connected to the second electrode.