Repair circuits and memory

Abstract

The embodiments of the present application relate to a repair circuit and a memory, wherein the repair circuit comprises: a plurality of redundant memory cells, each of which is configured with a state signal; a repair module, which is respectively connected to the plurality of redundant memory cells and is used to determine a target memory cell from the plurality of redundant memory cells according to the plurality of state signals, and repair the defective memory cell through the target memory cell; wherein the target memory cell corresponds to the defective memory cell one by one, and the repair module can repair different defective memory cells respectively in a plurality of repair stages, and a plurality of redundant memory cells are shared in a plurality of repair stages. By selecting a target memory cell in response to the state signal of the redundant memory cell, and sharing the redundant memory cell in a plurality of repair stages, the repair rate and repair flexibility of the defective memory cell are improved, that is, a repair circuit with higher repair flexibility and reliability is provided.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of semiconductor device technology, and in particular, to a repair circuit and a memory. Background Art

[0002] Semiconductor memory is a type of memory that uses semiconductor circuits for access. It is widely used in various fields due to its fast storage speed and high integration. In order to obtain higher flexibility and reliability, a certain number of redundant memory cells are usually set in the memory to serve as replacements when normal memory cells are damaged. However, as the number of normal memory cells continues to increase, the number of existing redundant memory cells can no longer meet the memory repair needs, resulting in an insufficient repair rate for defective memory cells. Summary of the invention

[0003] Based on this, it is necessary to provide a repair circuit and a memory to address the problem of insufficient repair rate of defective memory cells.

[0004] A repair circuit, comprising:

[0005] A plurality of redundant storage units, each of the redundant storage units being configured with a status signal;

[0006] a repair module, connected to the plurality of redundant storage units respectively, for determining a target storage unit from the plurality of redundant storage units according to the plurality of status signals, and repairing the defective storage unit through the target storage unit;

[0007] The target storage units correspond to the defective storage units one by one, the repair module can repair different defective storage units in multiple repair stages respectively, and the multiple repair stages share the multiple redundant storage units.

[0008] In one embodiment, the repair module includes:

[0009] A selection unit, configured to generate a unit selection signal according to a plurality of the state signals;

[0010] A storage repair unit is connected to the selection unit and the multiple redundant storage units respectively, and is used to receive the unit selection signal, determine the target storage unit according to the unit selection signal, and repair the defective storage unit through the target storage unit.

[0011] In one of the embodiments, the selection unit is used to generate the unit selection signal according to a preset repair order and a plurality of the status signals.

[0012] In one embodiment, the cell selection signal includes a plurality of enable signals, the plurality of enable signals correspond one-to-one to the plurality of redundant storage cells, and at most one of the plurality of enable signals is enabled at the same time;

[0013] The selection unit includes a plurality of generating circuits, each generating circuit is used to generate a corresponding enabling signal;

[0014] The storage repair unit is used to determine the redundant storage unit corresponding to the effective enable signal as the target storage unit.

[0015] In one embodiment, the state signal carries occupancy information of the corresponding redundant storage unit, the occupancy information includes occupied and unoccupied, the selection unit includes a first generation circuit, the first generation circuit is used to generate a first enable signal, and defines the redundant storage unit located in the first repair order as the first redundant storage unit; wherein,

[0016] When the first redundant storage unit is occupied, the first enable signal is invalid; when the first redundant storage unit is not occupied, the first enable signal is valid.

[0017] In one embodiment, the redundant storage unit located in the nth repair order is defined as the nth redundant storage unit, n is a positive integer greater than 1, and the selection unit further includes an nth generation circuit, and the nth generation circuit is used to generate an nth enable signal; wherein,

[0018] When at least one of all the redundant storage repair units whose repair order is located before the nth redundant storage unit is not occupied, the nth enable signal is invalid; when all the redundant storage repair units whose repair order is located before the nth redundant storage unit are occupied and the nth redundant storage unit is not occupied, the nth enable signal is valid.

[0019] In one embodiment, the nth generating circuit comprises:

[0020] n-1 first logic gates, wherein the n-1 first logic gates are used to receive the n-1 status signals in a one-to-one correspondence and perform logic calculations on the received status signals;

[0021] A second logic gate, wherein the second logic gate is configured with n input terminals and one output terminal, wherein the n-1 input terminals are respectively connected one-to-one with the n-1 output terminals of the first logic gate, and the remaining input terminals are used to receive the nth state signal, and the second logic gate is used to perform logic calculations on the multiple input signals to generate the nth enable signal.

[0022] In one embodiment, the first logic gate is a NOT gate, and the second logic gate is an AND gate.

[0023] In one embodiment, a plurality of the generating circuits share at least part of the first logic gates.

[0024] In one embodiment, the multiple repair stages include a first repair stage and a second repair stage, and the storage repair unit includes:

[0025] A first repair unit, connected to the selection unit and the plurality of redundant storage units, respectively, and configured to repair the defective storage unit in the first repair phase;

[0026] A second repair unit, connected to the selection unit and the plurality of redundant storage units, respectively, and configured to repair the defective storage unit in the second repair phase;

[0027] The first repair stage is earlier than the second repair stage, and the first repair unit occupies the redundant storage unit before the second repair unit.

[0028] In one embodiment, the first repair stage is a post-packaging repair stage, and the second repair stage is a self-repair stage.

[0029] In one embodiment, it also includes:

[0030] A detection module is connected to the plurality of normal storage cells, and is used to detect the operating status of the plurality of normal storage cells, and determine the defective storage cell from the plurality of normal storage cells according to the operating status.

[0031] A memory, comprising:

[0032] Multiple normal storage units;

[0033] As the aforementioned repair circuit, the repair circuit is respectively connected to a plurality of the normal storage cells;

[0034] The normal storage unit with abnormal operation status is used as the defective storage unit.

[0035] The above-mentioned repair circuit and memory, the repair circuit includes: a plurality of redundant storage units, each of which is configured with a state signal; a repair module, respectively connected to the plurality of redundant storage units, for determining a target storage unit from the plurality of redundant storage units according to the plurality of state signals, and repairing the defective storage unit through the target storage unit; wherein the target storage unit corresponds to the defective storage unit one by one, the repair module can repair different defective storage units respectively in a plurality of repair stages, and the plurality of redundant storage units are shared in a plurality of repair stages. By selecting a target storage unit in response to the state signal of the redundant storage unit, and sharing the redundant storage unit in a plurality of repair stages, the repair rate and repair flexibility of the defective storage unit are improved, that is, a repair circuit with higher repair flexibility and reliability is provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 is a schematic structural diagram of a repair circuit according to a first embodiment;

[0037] Figure 2 is a structural schematic diagram of a repair circuit according to a second embodiment;

[0038] Figure 3 is a schematic structural diagram of a repair circuit according to a third embodiment;

[0039] Figure 4 is a schematic structural diagram of a repair circuit according to a fourth embodiment;

[0040] Figure 5 is a structural schematic diagram of a repair circuit according to a fifth embodiment;

[0041] Figure 6 FIG. 4 is a schematic diagram of the structure of a repair circuit according to the sixth embodiment.

[0042] Component number description:

[0043] Redundant storage unit: 10; first redundant storage unit: 11; second redundant storage unit: 12; third redundant storage unit: 13; fourth redundant storage unit: 14; repair module: 20; selection unit: 100; generation circuit: 110; first generation circuit: 111; second generation circuit: 112; third generation circuit: 113; fourth generation circuit: 114; first logic gate: 1101; second logic gate: 1102; storage repair unit: 200; first repair unit: 210; detection module: 30. DETAILED DESCRIPTION

[0044] In order to facilitate understanding of the embodiments of the present application, the embodiments of the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the embodiments of the present application are given in the drawings. However, the embodiments of the present application can be implemented in many different forms and are not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the embodiments of the present application more thorough and comprehensive.

[0045] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those generally understood by those skilled in the art of the technical field of the embodiments of the present application. The terms used herein in the specification of the embodiments of the present application are only for the purpose of describing specific embodiments and are not intended to limit the embodiments of the present application. The term "and / or" used herein includes any and all combinations of one or more related listed items.

[0046] In the description of the embodiments of the present application, it should be understood that the terms "upper", "lower", "vertical", "horizontal", "inside", "outside", etc. indicate orientations or positional relationships based on the methods or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the embodiments of the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the embodiments of the present application.

[0047] Figure 1 Schematic diagram of the structure of the repair circuit of the first embodiment. The repair circuit of the embodiment of the present application is used to repair defective storage units in the memory. The memory may be a dynamic random access memory (DRAM), a static random access memory (SRAM), etc. The memory includes a plurality of normal storage units, each of which can store data, thereby realizing the storage function of the memory through the plurality of normal storage units.

[0048] However, it is understandable that during the manufacturing and use of the memory, there may be various situations such as poor manufacturing process or device aging, which may lead to abnormal operation status of normal memory cells. The abnormal operation status may include, for example, the inability to write data and the inability to read written data correctly. When the above problems occur in a normal memory cell, it can be identified as a defective memory cell. The defective memory cell cannot realize the access function, so it needs to be repaired by a repair circuit. Moreover, even if the normal memory cell is in a normal operation state at the factory, it may be damaged during use and thus turned into a defective memory cell. That is, multiple repair stages need to be set to repair the original and newly generated different defective memory cells respectively, so as to improve the operation efficiency and read and write accuracy of the memory. Reference Figure 1 In this embodiment, the repair circuit includes a repair module 20 and a plurality of redundant storage units 10 .

[0049] A plurality of redundant storage units 10, each of which is provided with a status signal. The status signal carries the occupancy information of the corresponding redundant storage unit 10, that is, the status signal corresponds to the occupancy information of the redundant storage unit 10, and the occupancy information includes occupied and unoccupied. Among them, occupation means repairing the defective storage unit by the redundant storage unit 10. Repair means that when reading and writing data, the defective storage unit is replaced by the redundant storage unit 10 to perform the data reading and writing functions that the defective storage unit should perform, and the defective storage unit is still set at the original address, but it is not required to perform the reading and writing operations. When a defective storage unit is found to exist, the redundant storage unit 10 can be used to replace the defective storage unit through the repair process, thereby realizing the repair of the defective storage unit. After the defective storage unit is repaired, the data to be stored in the defective storage unit will be stored in the redundant storage unit 10, and if the data in the defective storage unit needs to be read, it will be read from the corresponding redundant storage unit 10.

[0050] Exemplarily, the repair may include row repair and / or column repair, wherein row repair refers to replacing the row address corresponding to the defective memory cell with the row address of the redundant memory cell 10, and column repair refers to replacing the column address corresponding to the defective memory cell with the column address of the redundant memory cell 10.

[0051] Moreover, when the redundant storage unit 10 repairs the defective storage unit, there is a one-to-one mapping relationship, that is, each redundant storage unit 10 can only repair at most one defective storage unit. Therefore, by marking the occupancy information of the redundant storage unit 10, it is convenient to find the redundant storage unit 10 that has not been occupied during the repair process. Exemplarily, if a redundant storage unit 10 has been used to repair the defective storage unit, the occupancy information of the redundant storage unit 10 is occupied, and the corresponding status signal can be 0.

[0052] Furthermore, the normal memory cells and the redundant memory cells 10 are prepared at the same time, that is, the redundant memory cells 10 have the same hardware structure as the normal memory cells. Moreover, since the probability of occurrence of defective memory cells is low, usually only a small number of redundant memory cells 10 are set in the memory. Moreover, the number of redundant memory cells 10 is proportional to the number of normal memory cells and inversely proportional to the yield of the preparation process. That is, the more the number of normal memory cells, the lower the yield of the preparation process, and accordingly more redundant memory cells 10 need to be set.

[0053] The repair module 20 is connected to the plurality of redundant storage units 10 respectively, and is used to determine a target storage unit from the plurality of redundant storage units 10 according to the plurality of status signals, and repair the defective storage unit through the target storage unit. Furthermore, the repair module 20 can repair different defective storage units respectively in a plurality of repair stages, and the plurality of repair stages share the plurality of redundant storage units 10. In the existing memory, a corresponding redundant storage unit 10 is usually set for each repair stage, that is, each redundant storage unit 10 can only be used in the set repair stage. However, this method of use will result in insufficient utilization of the redundant storage unit 10, thereby causing insufficient repair rate of the defective storage unit.

[0054] Exemplarily, if the memory is configured with two repair stages, namely the first repair stage and the second repair stage, there is one defective memory cell that needs to be repaired in the first repair stage, and three defective memory cells that need to be repaired in the second repair stage. If the existing repair method is adopted, and two redundant memory cells 10 are correspondingly provided in each repair stage, then only two defective memory cells can be repaired in the second repair stage, that is, the defective memory cells cannot be completely repaired. However, if the method of sharing multiple redundant memory cells 10 in multiple repair stages of the embodiment of the present application is adopted, and a total of four redundant memory cells 10 are provided, then all defective memory cells can be repaired, thereby improving the repair rate and repair flexibility of the defective memory cells, providing a repair circuit with higher repair flexibility and reliability, and thereby improving the read and write accuracy of the memory.

[0055] In this embodiment, the repair circuit includes: a plurality of redundant storage cells 10, each of which is configured with a state signal; a repair module 20, which is respectively connected to the plurality of redundant storage cells 10, and is used to determine a target storage cell from the plurality of redundant storage cells 10 according to the plurality of state signals, and repair the defective storage cell through the target storage cell; wherein the target storage cell corresponds to the defective storage cell one by one, and the repair module 20 can repair different defective storage cells respectively in a plurality of repair stages, and the plurality of repair stages share the plurality of redundant storage cells 10. By selecting a target storage cell in response to the state signal of the redundant storage cell 10, and sharing the redundant storage cell 10 in a plurality of repair stages, the repair rate and repair flexibility of the defective storage cell are improved, that is, a repair circuit with higher repair flexibility and reliability is provided.

[0056] Further, the multiple repair stages include a first repair stage and a second repair stage, and the storage repair unit 200 includes a first repair unit 210 and a second repair unit. The first repair unit 210 is respectively connected to the selection unit 100 and the plurality of redundant storage units 10, and is used to repair the defective storage unit in the first repair stage; the second repair unit is respectively connected to the selection unit 100 and the plurality of redundant storage units 10, and is used to repair the defective storage unit in the second repair stage. Among them, the first repair stage is earlier than the second repair stage, and the first repair unit 210 takes precedence over the second repair unit in occupying the redundant storage unit 10. Further, the first repair stage is a post-packaging repair stage, and the second repair stage is a self-repair stage. It can be understood that, according to the repair requirements, three or more repair stages can also be set, and a larger number of repair units can be set accordingly, so as to correspond one to one to different repair stages, so as to provide more accurate and comprehensive repair, thereby improving the reliability and stability of the memory.

[0057] Figure 2 is a schematic diagram of the structure of the repair circuit of the second embodiment, referring to Figure 2 In this embodiment, the repair circuit includes a repair module 20 and a plurality of redundant storage units 10 , wherein the repair module 20 includes a selection unit 100 and a storage repair unit 200 .

[0058] The selection unit 100 is used to generate a unit selection signal according to the multiple state signals. Specifically, the selection unit 100 can be a digital logic circuit, that is, the selection unit 100 can include multiple logic gates, and the multiple logic gates perform logic operations according to the input state signals to generate unit selection signals. Among them, the number of state signals is the same as the number of redundant storage units 10, and they correspond one to one. Exemplarily, if four redundant storage units 10 are provided, the selection unit 100 will receive four state signals and perform logic operations on the four state signals.

[0059] The storage repair unit 200 is connected to the selection unit 100 and the plurality of redundant storage units 10, respectively, and is used to receive the unit selection signal, determine the target storage unit according to the unit selection signal, and repair the defective storage unit through the target storage unit.

[0060] In some embodiments, the cell selection signal may include only one signal, but the signal may output multiple bits of data in series, and the storage repair unit 200 may determine an unoccupied redundant storage unit 10 according to the received multiple bits of data, thereby repairing the defective storage unit. Exemplarily, taking the case where the repair circuit includes four redundant storage units 10, the cell selection signal may include two bits of data. If the cell selection signal is "00", the first redundant storage unit 11 is selected; if the cell selection signal is "01", the second redundant storage unit 12 is selected; if the cell selection signal is "10", the third redundant storage unit 13 is selected; if the cell selection signal is "11", the fourth redundant storage unit 14 is selected. The above-mentioned signal transmission method of serially outputting multiple bits of data requires a simpler hardware structure and fewer devices, so it is more suitable for small-volume memories with lower requirements for data read and write speeds.

[0061] In other embodiments, the unit selection signal includes multiple enable signals, and the multiple enable signals correspond to the multiple redundant storage units 10 one by one, and at most one of the multiple enable signals is enabled at the same time; the selection unit 100 includes multiple generation circuits 110, and each generation circuit 110 is used to generate one enable signal. Among them, the storage repair unit 200 is used to determine the redundant storage unit 10 corresponding to the enable signal that is enabled as the target storage unit. Exemplarily, taking the repair circuit including four redundant storage units 10 as an example, when the enable signal is in a high level state, the enable is valid. If the multiple enable signals include three low level signals and one high level signal, the redundant storage unit 10 corresponding to the high level signal is selected as the target storage unit to repair the defective storage unit. In this embodiment, the method of synchronously calculating and transmitting multiple signals is adopted, and the operation rate is faster, so it is more suitable for a memory with a large number of storage units, a large amount of data, and a high requirement for data reading and writing speed.

[0062] Further, the selection unit 100 is used to generate the unit selection signal according to a preset repair order and a plurality of the state signals. The redundant storage unit 10 located in the first repair order is defined as the first redundant storage unit 11, the redundant storage unit 10 located in the second repair order is defined as the second redundant storage unit 12, and so on. According to the preset repair order, when at least one of the redundant storage repair units 200 located before the nth redundant storage unit 10 in the repair order is not occupied, the nth enable signal is enable invalid; when all the redundant storage repair units 200 located before the nth redundant storage unit 10 in the repair order are occupied, and the nth redundant storage unit 10 is not occupied, the nth enable signal is enable valid. For example, when the first redundant storage unit 11 or the second redundant storage unit 12 is not occupied, the third enable signal corresponding to the third redundant storage unit 13 is enable invalid; when the first redundant storage unit 11 and the second redundant storage unit 12 are both occupied, and the third redundant storage unit 13 is not occupied, the corresponding third enable signal is enable valid.

[0063] Furthermore, the purpose of selecting redundant repair units according to the repair order can be achieved by selecting the circuit structure inside the unit 100, that is, the repair circuit of this embodiment can select the appropriate redundant repair unit for repair without external control signals. Specifically, Figure 3 FIG. 1 is a schematic diagram of the structure of the repair circuit of the third embodiment, referring to FIG. Figure 3In this embodiment, the selection unit 100 includes a first generation circuit 111, and the first generation circuit 111 is used to generate a first enable signal. When the first redundant storage unit 11 is occupied, the first enable signal is enable invalid; when the first redundant storage unit 11 is not occupied, the first enable signal is enable valid. Exemplarily, if the first state signal is at a high level, indicating that the first redundant storage unit 11 is not occupied, and the first enable signal is at a high level, indicating that the enable is valid, the level state of the first enable signal can follow the level state of the first state signal, that is, the signal output by the first generation circuit 111 is the same as the input signal. Therefore, there is no need to set additional logic gates in the first generation circuit 111, that is, the above-mentioned output function can be realized with a simple hardware structure.

[0064] Continue to refer Figure 3 In this embodiment, the selection unit 100 further includes an nth generation circuit 110, where n is an integer greater than 1. For example, Figure 3 In the embodiment, the selection unit 100 further includes a second generation circuit 112 , a third generation circuit 113 and a fourth generation circuit 114 , and the nth generation circuit 110 is used to generate an nth enable signal, that is, the nth enable signal corresponds to the nth generation circuit 110 one by one. Figure 4 FIG. 1 is a schematic diagram of the structure of the repair circuit of the fourth embodiment, referring to FIG. Figure 4 In this embodiment, the nth generating circuit 110 includes a second logic gate 1102 and n-1 first logic gates 1101 .

[0065] Among them, the n-1 first logic gates 1101 are used to receive the n-1 state signals in a one-to-one correspondence, and perform logic calculations on the received state signals, wherein the n-1 state signals are respectively the first state signal to the n-1th state signal. Further, the first logic gate 1101 can be a NOT gate. Exemplarily, taking the fourth generation circuit 114 as an example, the fourth generation circuit 114 includes 3 first logic gates 1101, and the 3 first logic gates 1101 are respectively used to receive the first state signal, the second state signal and the third state signal in a one-to-one correspondence, and the 3 first logic gates 1101 are all NOT gates, and the three first logic gates 1101 are respectively used to output the inverted first state signal, the inverted second state signal and the reversed third state signal in a one-to-one correspondence.

[0066] The second logic gate 1102 is configured with n input terminals and one output terminal, wherein n-1 of the input terminals are respectively connected to n-1 output terminals of the first logic gate 1101 in a one-to-one correspondence, and the remaining input terminals are used to receive the nth state signal, and the second logic gate 1102 is used to perform logic calculations on the input multiple signals to generate the nth enable signal. Further, the second logic gate 1102 can be an AND gate. Based on the above description, the second logic gate 1102 in the fourth generating circuit 114 is configured with 4 input terminals, wherein 3 of the input terminals are respectively used to receive the inverted first state signal, the inverted second state signal and the reversed third state signal in a one-to-one correspondence, and the remaining one input terminal is used to receive the fourth state signal, and the second logic gate 1102 performs a logic AND operation on the input multiple signals to generate the fourth enable signal.

[0067] It is understandable that the first logic gate 1101 of the embodiment of the present application is not limited to a NOT gate, and the second logic gate 1102 is not limited to an AND gate. For example, a NOT gate may be set in the first generating circuit 111, and the second logic gate 1102 may be set as an AND-NAND gate, and the storage repair unit may be controlled to select the redundant storage unit 10 corresponding to the enable signal in the low level state as the target storage unit to repair the defective storage unit. Therefore, as long as the circuit structure of selection and repair according to the preset repair order can be realized based on the multiple enable signals output by the selection unit 100, it belongs to the protection scope of the present application, and is not limited to the structure of the selection unit 100 in the aforementioned embodiment.

[0068] In one embodiment, a plurality of the generating circuits 110 share at least part of the first logic gates 1101. Specifically, Figure 5 is a schematic diagram of the structure of the repair circuit of the fifth embodiment, Figure 4 and Figure 5 In this embodiment, multiple logic gates for implementing the same function can be shared. Figure 4 , the second generating circuit 112, the third generating circuit 113 and the fourth generating circuit 114 all need to receive the inverted first state signal, accordingly, Figure 4 In the embodiment, each generating circuit 110 is provided with a NOT gate, and each NOT gate receives the first state signal independently and performs a negation operation. Figure 5 In the embodiment shown, the first state signal is first inverted, and the inverted signal is transmitted to each second logic gate 1102 respectively. Figure 4 Example, Figure 5The embodiment achieves the same technical effect with fewer logic devices, thereby providing a repair circuit with a simpler structure, which can effectively improve the integration of the memory. It is understandable that in other embodiments, only some logic gates used to achieve the same function can be shared, while some logic gates are not shared.

[0069] Figure 6 is a schematic diagram of the structure of the repair circuit of the sixth embodiment, referring to Figure 6 In this embodiment, the selection unit 100 is also used to receive an externally input repair phase signal, and output a unit selection signal according to the repair phase signal. Specifically, if the state signal is at a high level, it indicates that the corresponding redundant storage unit 10 is not occupied, and if the enable signal in the unit selection signal is at a high level, it indicates that the corresponding redundant storage unit 10 is selected for repair. In this embodiment, if at least two redundant storage units 10 need to be retained for repair in the second repair phase, the repair phase signal can be controlled to be always at a low level during the first repair phase. After calculation by the selection unit 100, the third enable signal and the fourth enable signal are always at a low level, that is, the third redundant storage unit 13 and the fourth redundant storage unit 14 cannot be occupied during the first repair phase, thereby achieving the purpose of retaining some redundant storage units 10, and realizing a more flexible repair circuit. In this embodiment, for another example, if only one redundant storage unit 10 is used in the first repair stage, for example, only the first redundant storage unit 11 is used, then in the second repair stage, three redundant storage units 10 may be available for use, for example, the second redundant storage unit 12, the second redundant storage unit 13, and the second redundant storage unit 14 may be available for use, which is equivalent to sharing the first redundant storage unit 11, the second redundant storage unit 12, the second redundant storage unit 13, and the second redundant storage unit 14 in the first repair stage and the second repair stage, thereby realizing a more flexible repair circuit.

[0070] In one of the embodiments, the repair circuit may further include a detection module 30 connected to a plurality of normal storage cells, wherein the detection module 30 is used to detect the operating status of the plurality of normal storage cells and determine the defective storage cell from the plurality of normal storage cells according to the operating status.

[0071] Specifically, the detection module 30 is connected to the normal storage unit to test the connected normal storage unit in the test mode. That is, when the memory is in the test mode, the detection module 30 performs the corresponding test function. The memory switches to the test mode in response to the test trigger signal. Exemplarily, the memory can automatically generate a test trigger signal to switch to the test mode each time it is powered on. The memory can also switch to the test mode in response to an externally input test trigger signal, and the test trigger signal can be, for example, a signal input by a user through an electronic device connected to the memory. The memory can also switch to the test mode in response to a test trigger signal output by a built-in controller, and the controller can output a test trigger signal after each preset time of the memory operation to achieve regular monitoring of normal storage units. It can be understood that a corresponding defect test can be set for each repair stage, and different test trigger signals can be set in different repair stages so that the detection module 30 can accurately distinguish between different repair stages.

[0072] The defect test method can be that the detection module 30 responds to the test trigger signal, automatically generates one or more test data, and writes the test data to each storage unit to be tested, and reads the data from the storage unit after a certain period of time, and compares the read data with the automatically generated test data to determine whether the storage function of the storage unit is normal. If the data read from a storage unit is different from the written data, the storage unit is a defective storage unit.

[0073] The embodiment of the present application also provides a memory, including: a repair circuit and a plurality of normal storage units, wherein the repair circuit is respectively connected to the plurality of normal storage units; wherein the normal storage unit with abnormal operation status is used as the defective storage unit. It is understandable that the specific structure of the repair circuit of this embodiment can refer to the aforementioned embodiment, and will not be described in detail in this embodiment. This embodiment realizes a memory with higher reliability and flexibility based on the repair circuit with flexible repair function.

[0074] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0075] The above-described embodiments only express several implementation methods of the embodiments of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the embodiments of the present application, and these all belong to the protection scope of the embodiments of the present application. Therefore, the protection scope of the patent of the embodiments of the present application shall be subject to the attached claims.

Claims

1. A repair circuit, characterized in that: include: A plurality of redundant storage units, each of the redundant storage units being configured with a status signal; a repair module, connected to the plurality of redundant storage units respectively, for determining a target storage unit from the plurality of redundant storage units according to the plurality of status signals, and repairing the defective storage unit through the target storage unit; The target storage unit corresponds to the defective storage unit one by one, the repair module can repair different defective storage units in multiple repair stages respectively, and the multiple repair stages share the multiple redundant storage units; The repair module comprises: A selection unit, configured to generate a unit selection signal according to a plurality of the state signals; a storage repair unit, connected to the selection unit and the plurality of redundant storage units, respectively, for receiving the unit selection signal, determining the target storage unit according to the unit selection signal, and repairing the defective storage unit through the target storage unit; The unit selection signal includes a plurality of enable signals, the plurality of enable signals correspond to the plurality of redundant storage units one by one, and at the same time at most one of the plurality of enable signals is enabled; The selection unit includes a plurality of generating circuits, each generating circuit is used to generate a corresponding enabling signal; The storage repair unit is used to determine the redundant storage unit corresponding to the effective enable signal as the target storage unit.

2. The repair circuit according to claim 1, characterized in that: The selection unit is used to generate the unit selection signal according to a preset repair order and a plurality of the status signals.

3. The repair circuit according to claim 1, characterized in that: The state signal carries the occupancy information of the corresponding redundant storage unit, the occupancy information includes occupied and unoccupied, the selection unit includes a first generation circuit, the first generation circuit is used to generate a first enable signal, and defines the redundant storage unit located in the first repair order as the first redundant storage unit; wherein, When the first redundant storage unit is occupied, the first enable signal is invalid; when the first redundant storage unit is not occupied, the first enable signal is valid.

4. The repair circuit according to claim 1, characterized in that: The redundant storage unit located in the nth repair order is defined as the nth redundant storage unit, n is a positive integer greater than 1, and the selection unit further includes an nth generation circuit, and the nth generation circuit is used to generate an nth enable signal; wherein, When at least one of all the redundant storage repair units whose repair order is located before the nth redundant storage unit is not occupied, the nth enable signal is invalid; when all the redundant storage repair units whose repair order is located before the nth redundant storage unit are occupied and the nth redundant storage unit is not occupied, the nth enable signal is valid.

5. The repair circuit according to claim 4, characterized in that: The nth generating circuit comprises: n-1 first logic gates, wherein the n-1 first logic gates are used to receive the n-1 status signals in a one-to-one correspondence and perform logic calculations on the received status signals; A second logic gate, wherein the second logic gate is configured with n input terminals and one output terminal, wherein the n-1 input terminals are respectively connected one-to-one with the n-1 output terminals of the first logic gate, and the remaining input terminals are used to receive the nth state signal, and the second logic gate is used to perform logic calculations on the multiple input signals to generate the nth enable signal.

6. The repair circuit according to claim 5, characterized in that: The first logic gate is a NOT gate, and the second logic gate is an AND gate.

7. The repair circuit according to claim 5, characterized in that: A plurality of the generating circuits share at least a portion of the first logic gates.

8. The repair circuit according to claim 2, characterized in that: The multiple repair stages include a first repair stage and a second repair stage, and the storage repair unit includes: A first repair unit, connected to the selection unit and the plurality of redundant storage units, respectively, and configured to repair the defective storage unit in the first repair phase; A second repair unit, connected to the selection unit and the plurality of redundant storage units, respectively, and configured to repair the defective storage unit in the second repair phase; The first repair stage is earlier than the second repair stage, and the first repair unit occupies the redundant storage unit before the second repair unit.

9. The repair circuit according to claim 8, characterized in that: The first repair stage is a post-packaging repair stage, and the second repair stage is a self-repair stage.

10. The repair circuit according to claim 1, characterized in that: Also includes: A detection module is connected to the plurality of normal storage cells, and is used to detect the operating status of the plurality of normal storage cells, and determine the defective storage cell from the plurality of normal storage cells according to the operating status.

11. A memory, characterized in that: include: Multiple normal storage units; The repair circuit according to any one of claims 1 to 10, wherein the repair circuit is respectively connected to a plurality of the normal storage cells; The normal storage unit with abnormal operation status is used as the defective storage unit.

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