Delay circuit unit layout, delay circuit layout, and semiconductor memory

Abstract

The disclosed embodiment discloses a layout of a delay circuit unit, a layout of a delay circuit, and a semiconductor memory, wherein the layout of the delay circuit unit includes a plurality of layout units, the layout units are used to form a NAND gate circuit, and the layout units are arranged in an array; wherein, in the first row of the array, a plurality of layout units conforming to a first layout mode are sequentially arranged; and in the second row of the array, a plurality of layout units conforming to a second layout mode are sequentially arranged; wherein, the first layout mode is different from the second layout mode, and the first layout mode and the second layout mode make the first row and the second row present a central symmetrical structure. In this way, it is not only conducive to achieving the consistency of delay between signals of different phases, but also the overall layout of the delay circuit unit is compact, and the layout area can be saved.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuits, and in particular to a layout of a delay circuit unit, a layout of a delay circuit, and a semiconductor memory. Background Art

[0002] A semiconductor device (eg, a semiconductor memory or a controller for controlling the semiconductor memory, etc.) transmits output data using a clock signal (eg, a data strobe signal DQS) synchronized with the output data.

[0003] Semiconductor devices can adjust the phase of a clock signal to a desired value and output data in synchronization with the clock signal. For example, in a delay locked loop (DLL), the delay locked loop outputs a clock signal with a desired phase by adjusting the delay time, and outputs data in synchronization with the clock signal. Among them, the coarse delay adjustment circuit (CDL) in the delay locked loop delays the reference clock signal through multiple delay stages to output two phase signals with a delay stage phase difference. Summary of the invention

[0004] The present disclosure provides a layout of a delay circuit unit, a layout of a delay circuit, and a semiconductor memory, which can achieve delay consistency of signals with different phases.

[0005] The technical solution of the present disclosure is achieved as follows:

[0006] In a first aspect, an embodiment of the present disclosure provides a layout of a delay circuit unit, the layout comprising a plurality of layout units, the layout units are used to form a NAND gate circuit, and the layout units are arranged in an array; wherein,

[0007] In the first row of the array, a plurality of layout units conforming to a first layout manner are sequentially arranged;

[0008] In the second row of the array, a plurality of layout units conforming to the second layout mode are sequentially arranged;

[0009] The first layout manner is different from the second layout manner, and the first layout manner and the second layout manner make the first row and the second row present a central symmetrical structure.

[0010] In some embodiments, the layout unit includes at least a first input signal line, a second input signal line and an output signal line; wherein,

[0011] In the first layout mode, the arrangement order of the signal lines of the layout unit from right to left is: the second input signal line, the output signal line, and the first input signal line;

[0012] In the second layout manner, the arrangement order of the signal lines of the layout unit from right to left is: the first input signal line, the output signal line, and the second input signal line.

[0013] In some embodiments, the layout is divided into at least a first metal layer and a second metal layer, and the second metal layer is located on the first metal layer; wherein,

[0014] The first metal layer is used for laying out the first input signal line, the second input signal line, the output signal line and the first layer signal line;

[0015] The second metal layer is used for laying out the second layer of signal lines;

[0016] The first input signal line, the second input signal line, the output signal line and the first layer signal line are all wired along a first direction, the second layer signal line is wired along a second direction, and the angle between the first direction and the second direction is 90 degrees.

[0017] In some embodiments, the first layer of signal lines includes at least: a first signal line, a second signal line, a third signal line, a fourth signal line, a fifth signal line, and a sixth signal line;

[0018] The second layer of signal lines at least includes: a first input interface signal line, a first output interface signal line, a second input interface signal line, a second output interface signal line, a third input interface signal line and a third output interface signal line.

[0019] In some embodiments, the first layer of signal lines is arranged on both sides of each of the layout units; wherein,

[0020] The arrangement order of the first layer of signal lines from right to left is: the first signal line, the second signal line, the third signal line, the fourth signal line, the fifth signal line and the sixth signal line.

[0021] In some embodiments, the first layer of signal lines further includes a plurality of redundant signal lines, wherein:

[0022] The first layer of signal lines are arranged in the order from right to left: the first signal line, the second signal line, the third signal line, the fourth signal line, the fifth signal line, the sixth signal line and the plurality of redundant signal lines.

[0023] In some embodiments, in the first metal layer, a plurality of first-layer signal lines have the same width, and a spacing between every two adjacent signal lines is the same.

[0024] In some embodiments, the second layer of signal lines further includes a plurality of intermediate connecting lines, and each of the intermediate connecting lines is provided with a connection point; wherein,

[0025] The plurality of intermediate connection lines are used to connect the signal lines provided with connection points in the first metal layer, so as to transmit the target signal to the corresponding NAND gate circuit.

[0026] In some embodiments, the plurality of layout units include a first layout unit, a second layout unit, a third layout unit, a fourth layout unit, a fifth layout unit, a sixth layout unit, a seventh layout unit and an eighth layout unit, and are arranged in a 2×4 array on the first metal layer; wherein,

[0027] In the first row of the array, the fourth layout unit, the second layout unit, the third layout unit and the first layout unit are sequentially arranged from right to left; wherein the fourth layout unit is used to form a fourth NAND gate circuit, the second layout unit is used to form a second NAND gate circuit, the third layout unit is used to form a third NAND gate circuit, and the first layout unit is used to form a first NAND gate circuit;

[0028] In the second row of the array, the eighth layout unit, the sixth layout unit, the seventh layout unit and the fifth layout unit are arranged in sequence from right to left; wherein the eighth layout unit is used to form an eighth NAND gate circuit, the sixth layout unit is used to form a sixth NAND gate circuit, the seventh layout unit is used to form a seventh NAND gate circuit; and the fifth layout unit is used to form a fifth NAND gate circuit.

[0029] In some embodiments, redundant signal lines are arranged on the left and right sides of the first layout unit and the fifth layout unit;

[0030] The sixth signal line and the fifth signal line are sequentially arranged on the left side and the right side of the third layout unit and the seventh layout unit;

[0031] The fourth signal line and the third signal line are sequentially arranged on the left and right sides of the second layout unit and the sixth layout unit;

[0032] The second signal line and the first signal line are arranged in sequence on the left side and the right side of the fourth layout unit and the eighth layout unit.

[0033] In some embodiments, the plurality of intermediate connecting lines are divided into a first group of intermediate connecting lines and a second group of intermediate connecting lines; wherein,

[0034] In the second metal layer, the first group of intermediate connection lines, the first input interface signal line, and the first output interface signal line are arranged corresponding to the positions of the fourth layout unit, the second layout unit, the third layout unit, and the first layout unit;

[0035] In the second metal layer, corresponding to the positions of the eighth layout unit, the sixth layout unit, the seventh layout unit and the fifth layout unit, the second group of intermediate connecting lines and the second input interface signal line, the second output interface signal line, the third input interface signal line and the third output interface signal line are arranged.

[0036] In some embodiments, it is characterized in that the first group of intermediate connection lines is used to connect part of the signal lines in the fourth layout unit, the second layout unit, the third layout unit and the first layout unit correspondingly in the first metal layer;

[0037] The second group of intermediate connection lines is used to connect part of the signal lines in the eighth layout unit, the sixth layout unit, the seventh layout unit and the fifth layout unit correspondingly on the first metal layer.

[0038] In some embodiments, the NAND gate circuit includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a second NMOS transistor; the second metal layer also includes a power line and a ground line; wherein,

[0039] The power lines are respectively connected to the source electrodes of the first PMOS tube and the second PMOS tube;

[0040] The grounding line is connected to the source of the first NMOS tube;

[0041] The first input signal line is connected to the gate of the second PMOS transistor and the gate of the second NMOS transistor respectively;

[0042] The second input signal line is connected to the gate of the first PMOS transistor and the gate of the first NMOS transistor respectively;

[0043] The output signal line is connected to the drain of the first PMOS tube, the drain of the second PMOS tube, and the drain of the second NMOS tube respectively.

[0044] In a second aspect, an embodiment of the present disclosure provides a layout of a delay circuit, which includes N delay circuit units, each of which corresponds to the layout as described in any one of the first aspects; wherein N is an integer greater than zero.

[0045] In some embodiments, the layout of the delay circuit is composed of N layouts of the delay circuit units cascaded; wherein,

[0046] The first input interface signal input by the first layout is the first output interface signal output by the second layout;

[0047] The second input interface signal input by the second layout is the second output interface signal output by the first layout;

[0048] The third input interface signal input by the second layout is the third output interface signal output by the first layout;

[0049] The first layout and the second layout represent the layouts of two adjacent delay circuit units in the layout of the delay circuit.

[0050] In a third aspect, an embodiment of the present disclosure provides a semiconductor memory, comprising a delay circuit corresponding to the layout of the delay circuit as described in any one of the second aspects.

[0051] The embodiments of the present disclosure provide a layout of a delay circuit unit, a layout of a delay circuit, and a semiconductor memory, wherein the layout of the delay circuit unit includes a plurality of layout units, the layout units are used to form a NAND gate circuit, and the layout units are arranged in an array; wherein, in the first row of the array, a plurality of layout units conforming to a first layout mode are sequentially arranged; and in the second row of the array, a plurality of layout units conforming to a second layout mode are sequentially arranged; wherein, the first layout mode is different from the second layout mode, and the first layout mode and the second layout mode make the first row and the second row present a central symmetrical structure. In this way, the plurality of layout units in the layout are arranged in an array, which is not only conducive to achieving delay consistency between signals of different phases, but also makes the overall layout of the delay circuit unit compact, and can also save layout area. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] Figure 1 A schematic diagram of the structure of a delay circuit provided by an embodiment of the present disclosure;

[0053] Figure 2 A schematic diagram of a circuit structure of a delay circuit unit provided in an embodiment of the present disclosure;

[0054] Figure 3 A schematic diagram of the composition structure of a layout of a delay circuit unit provided in an embodiment of the present disclosure;

[0055] Figure 4 A schematic diagram of a circuit structure of a NAND gate circuit provided in an embodiment of the present disclosure;

[0056] Figure 5 A detailed structural diagram of a layout of a delay circuit unit provided in an embodiment of the present disclosure;

[0057] Figure 6 A detailed structural diagram of another layout of a delay circuit unit provided in an embodiment of the present disclosure;

[0058] Figure 7 A schematic diagram of a layout structure of a gate-source layer provided in an embodiment of the present disclosure;

[0059] Figure 8 A schematic diagram of the composition structure of a layout unit provided in an embodiment of the present disclosure;

[0060] Fig. 9 A partially enlarged schematic diagram of a layout of a delay circuit unit provided in an embodiment of the present disclosure;

[0061] Fig.10 A simplified structural schematic diagram of a layout of a delay circuit unit provided in an embodiment of the present disclosure;

[0062] Fig.11 A partially enlarged schematic diagram of a layout of another delay circuit unit provided in an embodiment of the present disclosure;

[0063] Fig.12 A detailed structural diagram of a layout of another delay circuit unit provided in an embodiment of the present disclosure;

[0064] Fig.13 A simplified structural diagram of another layout of a delay circuit unit provided in an embodiment of the present disclosure;

[0065] Fig.14 A simplified structural schematic diagram of a layout of another delay circuit unit provided in an embodiment of the present disclosure;

[0066] Fig.15 A schematic diagram of the layout structure of a delay circuit provided in an embodiment of the present disclosure;

[0067] Fig.16 A schematic diagram of the layout structure of another delay circuit provided in an embodiment of the present disclosure;

[0068] Fig.17 A schematic diagram of the composition structure of a semiconductor memory provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0069] The following will be combined with the drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. It is understood that the specific embodiments described herein are only used to explain the relevant disclosure, rather than to limit the disclosure. It should also be noted that, for the convenience of description, only the parts related to the relevant disclosure are shown in the drawings.

[0070] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0071] In the following description, reference is made to “some embodiments”, which describe a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0072] It should be pointed out that the terms "first\second\third" involved in the embodiments of the present disclosure are merely used to distinguish similar objects and do not represent a specific ordering of the objects. It can be understood that "first\second\third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of the present disclosure described here can be implemented in an order other than that illustrated or described here.

[0073] The semiconductor device transmits output data using a clock signal synchronized with the output data. The semiconductor device can adjust the phase of the clock signal to a desired value and output data synchronously with the clock signal. For example, in a delay locked loop, the delay locked loop outputs a clock signal with a desired phase by adjusting the delay time, and outputs data synchronously with the clock signal. Among them, the coarse delay adjustment circuit (referred to as the coarse delay circuit) in the delay locked loop delays the reference clock signal through multiple delay stages to output two phase signals with a delay stage phase difference.

[0074] The disclosed embodiment provides a layout of a delay circuit unit, the layout includes a plurality of layout units, the layout units are used to form a NAND gate circuit, and the layout units are arranged in an array; wherein, in the first row of the array, a plurality of layout units conforming to a first layout mode are sequentially arranged; in the second row of the array, a plurality of layout units conforming to a second layout mode are sequentially arranged; wherein, the first layout mode is different from the second layout mode, and the first layout mode and the second layout mode make the first row and the second row present a central symmetric structure. In this way, it is not only conducive to achieving the consistency of delay between signals of different phases, but also the overall layout of the delay circuit unit is compact, and the layout area can be saved.

[0075] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0076] See also Figure 1 , which shows a schematic diagram of the composition structure of a delay circuit provided by an embodiment of the present disclosure, and the delay circuit can be a coarse delay circuit in a DLL. Figure 1 As shown, the delay circuit includes several delay circuit units (for the coarse delay circuit, the delay circuit unit is a CDL unit). For each CDL unit, the first input interface signal (INF signal) is input from the left side of the CDL unit, and the second input interface signal (INE signal) and the third input interface signal (INO signal) are input from the right side of the CDL unit. After the delay processing of the CDL unit, the first output interface signal (OUTF signal) is obtained and output from the right side of the CDL unit, and the second output interface signal (OUTE signal) and the third output interface signal (OUTO) are obtained and output from the left side of the CDL unit.

[0077] That is to say, Figure 1 In the delay circuit shown, for each CDL unit, from right to left, the INE signal and the INO signal are input signals, and the OUTE signal and the OUTO signal obtained after the delay processing are output signals; for two adjacent CDL units, the OUTE signal output by the right CDL unit is the INE signal input by the left CDL unit, and the OUTO signal output by the right CDL unit is the INO signal input by the left CDL unit. From left to right, the INF signal is the input signal, and the OUTF signal obtained after the delay processing is the output signal, and for two adjacent CDL units, the OUTF signal output by the left CDL unit is the INF signal input by the right CDL unit; in this way, a plurality of CDL units are cascaded to form a delay circuit, and the delay circuit realizes the delay processing of the signal through the cooperation of a plurality of CDL units.

[0078] For each CDL unit, see Figure 2 , which shows a circuit structure diagram of a delay circuit unit provided by an embodiment of the present disclosure. Figure 2 As shown, for each CDL unit, it can include eight NAND gate circuits: a first NAND gate circuit ND1, a second NAND gate circuit ND2, a third NAND gate circuit ND3, a fourth NAND gate circuit ND4, a fifth NAND gate circuit ND5, a sixth NAND gate circuit ND6, a seventh NAND gate circuit ND7, and an eighth NAND gate circuit ND8.

[0079] like Figure 2 As shown, in the CDL unit, each NAND gate circuit includes two input terminals and one output terminal.

[0080] For the first NAND gate circuit ND1, the two input ends are respectively connected to the first input interface 201 and the first NAND gate input interface 202, and the two input signals are: the first input interface signal (INF signal) from the first input interface 201 and the first NAND gate input signal (INFENE signal) from the first NAND gate input interface 202; the output signal of the first NAND gate circuit ND1 is the first NAND gate output signal (NET12 signal), and the output end of the first NAND gate circuit ND1 is respectively connected to the input ends of the second NAND gate circuit ND2 and the third NAND gate circuit ND3.

[0081] For the second NAND gate circuit ND2, the two input ends are respectively connected to the output end of the first NAND gate circuit ND1 and the second NAND gate input interface 203, and the two input signals are: the first NAND gate output signal (NET12 signal) and the second NAND gate input signal (INFENO signal) from the first NAND gate circuit ND1; the output signal of the second NAND gate circuit ND2 is the first output interface signal (OUTF signal), and the output end of the second NAND gate circuit ND2 is connected to the input end of the fourth NAND gate circuit ND4 and the first output interface 204.

[0082] For the third NAND gate circuit ND3, the two input ends are respectively connected to the third NAND gate input interface 205 and the output end of the first NAND gate circuit ND1, and the two input signals are: the third NAND gate input signal (SELE signal) from the third NAND gate input interface 205 and the first NAND gate output signal (NET12 signal) from the first NAND gate circuit ND1; the output signal of the third NAND gate circuit ND3 is the third NAND gate output signal (NET37 signal), and the output end of the third NAND gate circuit ND3 is connected to the input end of the seventh NAND gate circuit ND7.

[0083] For the fourth NAND gate circuit ND4, the two input terminals are respectively connected to the fourth NAND gate input interface 206 and the output terminal of the second NAND gate circuit ND2, and the two input signals are: the fourth NAND gate input signal (SELO signal) and the first output interface signal (OUTF signal) from the fourth NAND gate input interface 206; the output signal of the fourth NAND gate circuit ND4 is the fourth NAND gate output signal (NET46 signal), and the output terminal of the fourth NAND gate circuit ND4 is connected to the input terminal of the sixth NAND gate circuit ND6.

[0084] For the fifth NAND gate circuit ND5, the two input terminals are respectively connected to the power supply terminal 207 and the output terminal of the sixth NAND gate circuit ND6, and the two input signals are: the power supply signal (vdd signal) from the power supply terminal 207 and the sixth NAND gate output signal (NET56 signal); the output signal of the fifth NAND gate circuit ND5 is the third output interface signal (OUTO signal), and the output terminal of the fifth NAND gate circuit ND5 is connected to the third output interface 208.

[0085] For the sixth NAND gate circuit ND6, the two input terminals are respectively connected to the third input interface 209 and the output terminal of the fourth NAND gate circuit ND4, and the two input signals are: the third input interface signal (INO signal) from the third input interface 209 and the fourth NAND gate output signal (NET46 signal); the output signal of the sixth NAND gate circuit ND6 is the sixth NAND gate output signal (NET56 signal), and the output terminal of the sixth NAND gate circuit ND6 is connected to the input terminal of the fifth NAND gate circuit ND5.

[0086] For the seventh NAND gate circuit ND7, the two input terminals are respectively connected to the output terminal of the third NAND gate circuit ND3 and the output terminal of the eighth NAND gate circuit ND8, and the two input signals are: the third NAND gate output signal (NET37 signal) and the eighth NAND gate output signal (NET78 signal); the output signal of the seventh NAND gate circuit ND7 is the second output interface signal (OUTE signal), and the output terminal of the seventh NAND gate circuit ND7 is connected to the second output interface 2010.

[0087] For the eighth NAND gate circuit ND8, the two input terminals are respectively connected to the power supply terminal 207 and the second input interface 2011, and the two input signals are respectively: the power supply signal (vdd signal) and the second input interface signal (INE signal); the output signal of the eighth NAND gate circuit ND8 is the eighth NAND gate output signal (NET78 signal), and the output terminal of the eighth NAND gate circuit ND8 is connected to the input terminal of the seventh NAND gate circuit ND7.

[0088] It should be noted that the above letters are only shorthand for the signals and do not constitute a specific limitation on the signal types. In practice, each signal may also be described in other ways, and the embodiments of the present disclosure do not specifically limit this.

[0089] It should also be noted that after the first input interface signal (INF signal) is input into the CDL unit, it passes through the first NAND gate circuit ND1, the third NAND gate circuit ND3 and the seventh NAND gate circuit ND7, and is delayed together with other signals to obtain the second output interface signal (OUTE signal); or, after the first input interface signal (INF signal) is input into the CDL unit, it passes through the first NAND gate circuit ND1, the second NAND gate circuit ND2, the fourth NAND gate circuit ND4, the sixth NAND gate circuit ND6 and the fifth NAND gate circuit ND5, and is delayed together with other signals to obtain the third output interface signal (OUTO signal). That is to say, for the first input interface signal (INF signal), two signal lines, INF-OUTE and INF-OUTO, will be formed inside the CDL unit, wherein the signal line of INF-OUTE will pass through three NAND gate circuits to delay the signal, and the signal line of INF-OUTO will pass through five NAND gate circuits to delay the signal. Then, for the second output interface signal (OUTE signal) and the third output interface signal (OUTO signal), there will be a difference of two delay times of NAND gate circuits when they are output, that is, a difference of two clock cycles.

[0090] In this way, the signal delay processing is realized through the cooperation of eight NAND gate circuits. Figure 2 It can be seen that due to the disorder of the distribution of each NAND gate circuit and the influence of the wiring layout of the line, it is difficult to ensure that the output delay of the second output interface signal (OUTE signal) and the third output interface signal (OUTO signal) is the delay time of two NAND gate circuits; in addition, when the output signal of the NAND gate circuit is transmitted to the next NAND gate circuit, the path length passed by the signal may be different, and the layout of the entire circuit lacks neatness, which affects the uniformity of the delay between signals and is not conducive to the delay work of the CDL unit and the delay circuit.

[0091] In the design of delay circuits (such as DLL), since each delay stage requires the same time delay, a layout design with the same time delay is very important. The current layout design makes it difficult to ensure that the time delay of each delay stage is the same. Therefore, on this basis, the embodiment of the present disclosure designs the specific arrangement of the CDL unit to improve the non-uniformity of delay during signal transmission and increase the integration of the circuit.

[0092] In one embodiment of the present disclosure, see Figure 3 , which shows a schematic diagram of the composition structure of a layout 30 of a delay circuit unit provided by an embodiment of the present disclosure. Figure 3As shown, the layout 30 includes a plurality of layout units, the layout units are used to form a NAND gate circuit, and the layout units are arranged in an array; wherein,

[0093] In the first row of the array, a plurality of layout units 301 conforming to the first layout mode are sequentially arranged;

[0094] In the second row of the array, a plurality of layout units 302 conforming to the second layout mode are sequentially arranged;

[0095] The first layout mode is different from the second layout mode, and the first layout mode and the second layout mode make the first row and the second row present a central symmetrical structure.

[0096] It should be noted that Figure 3 The figure shows the layout structure corresponding to a delay circuit unit in the delay circuit. The delay circuit is composed of a plurality of delay circuit units in cascade. The delay circuit can be a coarse delay circuit in a DLL or other types of delay circuits. The embodiments of the present disclosure do not specifically limit this.

[0097] exist Figure 3 The layout 30 shown includes a plurality of layout units, each of which is used to form a corresponding NAND gate circuit. The plurality of layout units are arranged in an array, that is, in the delay circuit unit, the plurality of NAND gate circuits formed by the plurality of layout units are arranged in an array.

[0098] like Figure 3 As shown, in an array composed of a plurality of layout units (since the layout units are used to form NAND gate circuits, the array can also be called an array composed of a plurality of NAND gate circuits), at least a first row and a second row are included. Since the layout modes of the layout units in the first row and the second row are different, the layout units arranged in the first row are recorded as layout units 301, and the layout units arranged in the second row are recorded as layout units 302; wherein, in the first row, the layout mode of the plurality of layout units 301 conforms to the first layout mode; in the second row, the layout mode of the plurality of layout units 302 conforms to the second layout mode, and the first layout mode and the second layout mode are different layout modes.

[0099] Based on the different layout modes of the two rows of the array, the first row and the second row of the array are centrally symmetrical, wherein the central symmetric point is the geometric center of the layout 30, as shown in FIG. Figure 3 As shown by the black dots in FIG. In this way, the overall layout of the delay circuit unit is compact and the layout area can be saved.

[0100] For the first layout mode and the second layout mode, if Figure 3As shown, in some embodiments, the layout unit may include at least a first input signal line A, a second input signal line B and an output signal line Z; wherein,

[0101] In the first layout mode, the arrangement order of the signal lines of the layout unit 301 from right to left is: the second input signal line B, the output signal line Z, the first input signal line A;

[0102] In the second layout mode, the signal lines of the layout unit 302 are arranged in the order from right to left: first input signal line A, output signal line Z, second input signal line B.

[0103] It should be noted that if Figure 3 As shown, for the NAND gate circuit formed by each layout unit in the layout 30, the layout unit includes a first input signal line A, a second input signal line B and an output signal line Z, and in the direction from left to right or from right to left, the arrangement order of the three signal lines in the layout unit 301 of the first row and the layout unit 302 of the second row is opposite, forming a central symmetrical structure between the two rows.

[0104] That is to say, Figure 3 In the figure, two input terminals (ie, the first input signal line A and the second input signal line B) and one output terminal (ie, the output signal line Z) corresponding to the NAND gate circuit formed by the layout unit are mainly shown.

[0105] Further, for each NAND gate circuit formed in layout 30, see Figure 4 , which shows a schematic diagram of the circuit structure of a NAND gate circuit provided by an embodiment of the present disclosure. Figure 4 As shown, in some embodiments, the NAND gate circuit may include a first PMOS transistor P1, a second PMOS transistor P2, a first NMOS transistor N1, and a second NMOS transistor N2.

[0106] It should be noted that if Figure 4As shown, for any NAND gate circuit in the embodiment of the present disclosure, the NAND gate circuit can be composed of two P-channel metal oxide semiconductor field effect transistors (P-type channel Metal Oxide Semiconductor, PMOS tube) P1 and P2, and two N-type channel Metal Oxide Semiconductor field effect transistors (N-type channel Metal Oxide Semiconductor, NMOS tube) N1 and N2. Wherein, A represents the first input signal line, B represents the second input signal line, Z represents the output signal line, two P-channel MOS tubes (i.e., the first PMOS tube P1 and the second PMOS tube P2) are connected in parallel, and two N-channel MOS tubes (i.e., the first NMOS tube N1 and the second NMOS tube N2) are connected in series.

[0107] In some embodiments, the layout 30 can be divided into at least a first metal layer and a second metal layer, and the second metal layer is located on the first metal layer; wherein,

[0108] A first metal layer, used for laying out a first input signal line, a second input signal line, an output signal line and a first layer signal line;

[0109] The second metal layer is used to layout the second layer signal lines;

[0110] The first input signal line, the second input signal line, the output signal line and the first layer signal line are all wired along the first direction, the second layer signal line is wired along the second direction, and the angle between the first direction and the second direction is 90 degrees.

[0111] It should be noted that, for the layout 30 provided in the embodiment of the present disclosure, it can be divided into at least a first metal layer (also called Metal 0) and a second metal layer (also called Metal 1), and the second metal layer is located on the upper layer of the first metal layer.

[0112] The first input signal line, the second input signal line and the output signal line in the layout unit are arranged in the first metal layer, and the first metal layer is also arranged with the first layer signal line; the second metal layer is arranged with the second layer signal line. The first input signal line, the second input signal line, the output signal line and the first layer signal line are wired along the first direction, and the second layer signal line is wired along the second direction, and the angle between the first direction and the second direction is 90 degrees.

[0113] For the first metal layer, see Figure 5 , which shows a detailed structural diagram of a layout 30 of a delay circuit unit provided by an embodiment of the present disclosure. Among them, Figure 5 (a) shows the overall wiring arrangement schematic diagram of the first metal layer; Figure 5(b) shows a schematic diagram of the wiring arrangement of the signal lines in the NAND gate circuit corresponding to the layout unit 301 arranged in the first layout manner in the first row of the first metal layer; Figure 5 (c) in the figure shows a schematic diagram of the wiring arrangement of the signal lines in the NAND gate circuit corresponding to the layout unit 302 arranged in the second layout manner in the second row of the first metal layer.

[0114] like Figure 5 As shown, among the wirings of the first metal layer, all wirings except the signal lines of the NAND gate circuits included in (b) and (c) are referred to as first-layer signal lines.

[0115] For the second metal layer, see Figure 6 , which shows a detailed structural schematic diagram of another delay circuit unit layout 30 provided by an embodiment of the present disclosure, which shows a schematic diagram of the overall wiring arrangement of the second metal layer. Figure 6 As shown, the metal wiring inside the dotted frame represents the second layer signal line, and the second layer signal line extends along the second direction.

[0116] It should be noted that if Figure 5 and Figure 6 As shown, in the first metal layer, the first layer signal lines and the signal lines of the NAND gate circuit extend along the first direction; in the second metal layer, the second layer signal lines extend along the second direction, and the angle between the first direction and the second direction is 90 degrees. Since the second metal layer is located on the upper layer of the first metal layer, the second layer signal lines can be connected across the first metal layer to connect the non-adjacent signal lines in the first metal layer, thereby realizing signal transmission.

[0117] Furthermore, in some embodiments, Figure 6 As shown, the second metal layer may further include a power line 606 and a ground line 607; wherein,

[0118] The power line 606 is connected to the source of the first PMOS tube and the second PMOS tube respectively;

[0119] The ground line 607 is connected to the source of the first NMOS tube;

[0120] The first input signal line A is connected to the gate of the second PMOS tube and the gate of the second NMOS tube respectively;

[0121] The second input signal line B is connected to the gate of the first PMOS tube and the gate of the first NMOS tube respectively;

[0122] The output signal line Z is connected to the drain of the first PMOS tube, the drain of the second PMOS tube, and the drain of the second NMOS tube respectively.

[0123] It should be noted that if Figure 6 As shown, in the second metal layer, there are two power lines 606 and two ground lines 607. Connection points 303B can be set on the power lines 606 and the ground lines 607, and each connection point 303B can include a plurality of contact points 303C. Figure 6 In the embodiment, each connection point 303B includes three contact points 303C. The specific number of the contact points is not specifically limited in the embodiment of the present disclosure. Figure 5 As shown, the signal line of the first metal layer is provided with connection points 303B corresponding to the positions and the number in the second metal layer. Here, the connection between the connection point 303B in the first metal layer and the connection point 303B in the second metal layer can be connected by a contact plug, and the contact point 303C included therein can be a contact hole.

[0124] Specifically, for each NAND gate circuit, the power line 606 can be connected to the source of the first PMOS transistor P1 and the second PMOS transistor P2 through the connection point 303B; the ground line 607 can be connected to the source of the first NMOS transistor N1 through the connection point 303B.

[0125] It should also be noted that the layout 30 may also include a gate-source layer for providing a gate and an active region of a transistor (including an NMOS transistor and a PMOS transistor) in a NAND gate circuit. Figure 7 , which shows a schematic diagram of the layout structure of a gate source layer provided by an embodiment of the present disclosure, such as Figure 7 As shown in (a), the gate-source layer is arranged with active areas and gates of multiple transistors, and the gate-source layer may also include a first isolation structure 703 and a second isolation structure 704. The first isolation structure 703 can isolate the NAND gate circuits and transistors in the first row and the second row to avoid mutual crosstalk, and the second isolation structure 704 can isolate the NAND gate circuits and transistors shown in the figure from other structures in the circuit (such as the layout of adjacent delay circuit units) to avoid adverse effects caused by mutual crosstalk between circuits. The first isolation structure 703 may be an N-well region, and the second isolation structure 704 may be a P-well region.

[0126] In the first row of the gate-source layer, active regions and gates corresponding to four NAND gate circuits arranged in a first layout manner are arranged in sequence from left to right. Figure 7 (b) corresponds to the active area and gate of the NAND gate circuit arranged in the first layout. Figure 7As shown in (b), the active area 7022 can represent the active areas of the first NMOS tube N1 and the second NMOS tube N2, and the active area 7022 can be an N-type doped active area; the active area 7021 can represent the active areas of the first PMOS tube P1 and the second PMOS tube P2, and the active area 7021 can be a P-type doped active area; the gate 7011 can represent the gate of the first NMOS tube N1, the gate 7012 can represent the gate of the second NMOS tube N2, the gate 7013 can represent the gate of the first PMOS tube P1, and the gate 7014 can represent the gate of the second PMOS tube P2.

[0127] A connection point 303D may be provided on each gate. Figure 5 As shown, in the first metal layer, each first input signal line A and each first input signal line B are also provided with corresponding positions and corresponding numbers of connection points 303D, so that each gate and each input signal line can be connected through the connection points 303D.

[0128] Specifically, for each NAND gate circuit formed by the layout unit, the first input signal line A is connected to the gate of the second PMOS tube P2 and the gate of the second NMOS tube N2 through the connection point 303D; the second input signal line B is connected to the gate of the first PMOS tube P1 and the gate of the first NMOS tube N1 through the connection point 303D.

[0129] See also Figure 8 , which shows a schematic diagram of the composition structure of a layout unit provided by an embodiment of the present disclosure. Figure 8 As shown, it is a schematic diagram showing the superimposed connection of a layout unit 301 in the first row of the layout 30, Figure 8 and Figure 4The circuit structure diagram of the NAND gate circuit in FIG. 1 is corresponding. Here, the gate-source layer, the first metal layer and the second metal layer are sequentially stacked and connected according to the connection points at corresponding positions. The first metal layer is located on the upper layer of the gate-source layer, and the second metal layer is located on the upper layer of the first metal layer. The lower end of the first input signal line A is connected to the gate 7012 of the second NMOS tube N2 through the connection point 303D, and the upper end of the first input signal line A is connected to the gate 7014 of the second PMOS tube P2 through the connection point 303D. The lower end of the second input signal line B is connected to the gate 7014 of the first NMOS tube N1 through the connection point 303D. The upper end of the second input signal line B is connected to the gate 7011 of the first PMOS tube through the connection point 303D; the output signal line Z is respectively connected to the drain of the first PMOS tube, the drain of the second PMOS tube and the drain of the second N-type transistor (not shown in the figure); the power line 606 is respectively connected to the gate 7013 of the first PMOS tube and the gate 7014 of the second PMOS tube through the connection point 303B; the ground line 607 is connected to the gate 7011 of the first NMOS tube through the connection point 303B.

[0130] In addition, if Figure 7 or Figure 8 As shown, two redundant signal lines (dummy) are also included on both sides of gate 7011 and gate 7012, and on both sides of gate 7013 and gate 7014, which are used to maintain the symmetry and neatness of the layout, ensure the manufacturability of the chip, improve the accuracy of the process, and avoid etching failure.

[0131] That is, in the layout of the delay circuit unit provided in the embodiment of the present disclosure, the gate source layer, the first metal layer and the second metal layer may be included in sequence from the bottom layer to the top layer. Figure 4 and Figure 8 As shown, the gate-source layer is used to form the gate and active area of ​​the transistor; the first metal layer is used to form the first input signal line A, the second input signal line B and the output signal line Z; the second metal layer is used to form the power line and the ground line. The gate-source layer, the first metal layer and the second metal layer are superimposed and connected through the connection points at the corresponding positions to form a NAND gate circuit.

[0132] in addition, Figure 7 (c) shows a schematic diagram of the arrangement of the gate and active area of ​​the NAND gate circuit corresponding to the layout unit 302 arranged in the second layout mode in the second row of the layout 30, which is similar to Figure 7 (b) is centrally symmetrically distributed, and the connection method of the two is the same, which will not be repeated here.

[0133] For the first layer of signal lines and the second layer of signal lines, in some embodiments, the first layer of signal lines may include at least: a first signal line 3021, a second signal line 3022, a third signal line 3023, a fourth signal line 3024, a fifth signal line 3025 and a sixth signal line 3026;

[0134] The second layer of signal lines may include at least: a first input interface signal line 6011 , a first output interface signal line 6012 , a second input interface signal line 6021 , a second output interface signal line 6022 , a third input interface signal line 6031 and a third output interface signal line 6032 .

[0135] It should be noted that see Fig. 9 , which shows a partially enlarged schematic diagram of a layout 30 of a delay circuit unit provided in an embodiment of the present disclosure, which shows a partially enlarged schematic diagram of the first metal layer, that is, Figure 5 The dotted line frame part at the bottom.

[0136] like Fig. 9 As shown, in the first metal layer, the first layer signal lines may include at least the following six types: a first signal line 3021 , a second signal line 3022 , a third signal line 3023 , a fourth signal line 3024 , a fifth signal line 3025 and a sixth signal line 3026 .

[0137] The first signal line 3021 is used to transmit a first signal, the second signal line 3022 is used to transmit a second signal, the third signal line 3023 is used to transmit a third signal, the fourth signal line 3024 is used to transmit a fourth signal, the fifth signal line 3025 is used to transmit a fifth signal, and the sixth signal line 3026 is used to transmit a sixth signal. The first signal, the second signal, the third signal, the fourth signal, the fifth signal, and the sixth signal are different signals.

[0138] Here, the first signal can be the aforementioned fourth NAND gate input signal (SELO signal), the second signal can be the aforementioned second NAND gate input signal (INFENO signal), the third signal can be the aforementioned fourth NAND gate output signal (NET46 signal), the fourth signal can be the aforementioned third NAND gate output signal (NET37 signal), the fifth signal can be the aforementioned third NAND gate input signal (SELE signal), and the sixth signal can be the aforementioned first NAND gate input signal (INFENE signal).

[0139] Among them, the SELO signal and the SELE signal correspond to two selection signals with different phases, the INFENO signal and the INFENE signal correspond to two enable signals of the input clock signal, and the NET37 signal and the NET46 signal correspond to the internal node signals of the delay circuit unit.

[0140] It should also be noted that in the second metal layer, the second layer signal line can at least include a first input interface signal line 6011, a first output interface signal line 6012, a second input interface signal line 6021, a second output interface signal line 6022, a third input interface signal line 6031 and a third output interface signal line 6032.

[0141] Among them, the first input interface signal line 6011 is used to transmit the first input interface signal (INF signal), the first output interface signal line 6012 is used to transmit the first output interface signal (OUTF signal), the second input interface signal line 6021 is used to transmit the second input interface signal (INE signal), the second output interface signal line 6022 is used to transmit the second output interface signal (OUTE signal), the third input interface signal line 6031 is used to transmit the third input interface signal (INO signal), and the third output interface signal line 6032 is used to transmit the third output interface signal (OUTO signal).

[0142] In some embodiments, the first layer of signal lines may be arranged on both sides of each layout unit; wherein,

[0143] The arrangement order of the first layer of signal lines from right to left is: a first signal line 3021 , a second signal line 3022 , a third signal line 3023 , a fourth signal line 3024 , a fifth signal line 3025 and a sixth signal line 3026 .

[0144] It should be noted that see Fig.10 , which shows a simplified structural schematic diagram of a layout 30 of a delay circuit unit provided by an embodiment of the present disclosure, which can represent a simplified enlargement of the first row in the array shown in the first metal layer, and can also be used to represent a simplified enlargement of the second row. Figure 5 , 9 As shown in FIG. 10 , a first-layer signal line is arranged on the left and right sides of each layout unit, and for the upper and lower layout units, the first-layer signal line on the left and right sides is the same. In the first metal layer, the arrangement order of the first-layer signal lines from right to left is the first signal line 3021, the second signal line 3022, the third signal line 3023, the fourth signal line 3024, the fifth signal line 3025 and the sixth signal line 3026.

[0145] Furthermore, in some embodiments, the first layer of signal lines may also include a plurality of redundant signal lines 3027, wherein:

[0146] The arrangement order of the first layer of signal lines from right to left is: a first signal line 3021 , a second signal line 3022 , a third signal line 3023 , a fourth signal line 3024 , a fifth signal line 3025 , a sixth signal line 3026 and the plurality of redundant signal lines 3027 .

[0147] It should be noted that if Figure 5 , 9 As shown in FIG. 10 , in the first metal layer, the first layer signal line may further include a plurality of redundant signal lines 3027, wherein the redundant signal lines 3027 are not used to transmit signals. Figure 6 , in the ground line 607, in order from left to right, the first and third connection points 303B are used to connect the redundant signal line 3027 to the ground line. Here, only two redundant signal lines 3027 and two connection points 303B for connecting the redundant signal lines to the ground line are shown. In practice, the number of redundant signal lines can be set according to process requirements, and the embodiment of the present disclosure is not specifically limited.

[0148] The redundant signal line 3027 can ensure the neat arrangement of the entire layout, and can ensure the manufacturability of the circuit during the manufacturing process, prevent etching failure due to excessive or insufficient exposure, and avoid the influence of light reflection and diffraction on the accuracy of the physical graphics of key components during the photolithography process.

[0149] In some embodiments, in the first metal layer, the widths of a plurality of first-layer signal lines are the same, and the spacings between every two adjacent signal lines are the same.

[0150] It should be noted that see Fig.11 , which shows a partially enlarged schematic diagram of a layout 30 of another delay circuit unit provided in an embodiment of the present disclosure, which shows a partially enlarged schematic diagram of the first metal layer, that is, Figure 5 The upper dotted line frame. Fig.11 As shown, for the signal lines in the first metal layer (including the first layer signal lines and the signal lines of the NAND gate circuit), the width of each signal line is the same, and the spacing between any two adjacent signal lines is the same. Fig.11 In the example, the sum of the width of each signal line and the distance between two adjacent signal lines is a.

[0151] In this way, in the first metal layer, the same spacing and signal line width are maintained between the first-layer metal lines and the signal lines of the NAND gate circuits, which is not only conducive to maintaining the uniformity of the delay of different signals during the transmission process, but also can keep the overall layout of the circuit neat, making the circuit layout compact and saving layout area.

[0152] In some embodiments, the second layer of signal lines may further include a plurality of intermediate connecting lines, and each intermediate connecting line is provided with a connecting point; wherein,

[0153] A plurality of intermediate connection lines are used to connect the signal lines provided with connection points in the first metal layer, so as to transmit the target signal to the corresponding layout unit NAND gate circuit.

[0154] It should be noted that if Figure 5 As shown, in the first metal layer, each layout unit and the first layer signal line are provided with a connection point 303A; Figure 6 As shown, in the second metal layer, the second layer signal lines are also provided with connection points 303A. Figure 6 The second layer signal lines in the dotted box except the aforementioned first input interface signal line 6011, first output interface signal line 6012, second input interface signal line 6021, second output interface signal line 6022, third input interface signal line 6031 and third output interface signal line 6032 are called intermediate connection lines.

[0155] Based on the connection points 303A set on the signal lines of the first metal layer and the second metal layer, the signal lines in the first metal layer and the signal lines in the second metal layer can be connected to achieve signal transmission.

[0156] See also Figures 12-14 ,in, Fig.12 It shows a detailed structural schematic diagram of a layout 30 of another delay circuit unit provided in an embodiment of the present disclosure; Fig.13 A simplified structural schematic diagram of another layout 30 of a delay circuit unit provided by an embodiment of the present disclosure is shown; Fig.14 A simplified structural diagram of a layout 30 of another delay circuit unit provided in an embodiment of the present disclosure is shown.

[0157] like Fig.12 As shown, after the first metal layer is connected to the second metal layer, the connection point 303A in the first metal layer is connected to the connection point 303A in the second metal layer correspondingly, thereby connecting the signal line of the first metal layer and the signal line of the second metal layer.

[0158] In addition, the connection points 303A, 303B, 303D, etc. involved in the embodiments of the present disclosure may be connected in the same manner or in different manners to achieve conductive connection and signal transmission between different signal lines. For example, the connection manner may be connected through contact plugs, and the corresponding connection points may be contact holes, so that two signal lines can be connected through the contact plugs and the contact holes.

[0159] That is to say, the signal lines in the first metal layer are connected through the signal lines in the second metal layer, so as to transmit the target signal to the corresponding NAND gate circuit. The target signal includes the first signal, the second signal, the third signal, the fourth signal, the fifth signal and the sixth signal.

[0160] In some embodiments, Fig.13 As shown, the plurality of layout units may include a first layout unit 3011, a second layout unit 3012, a third layout unit 3013, a fourth layout unit 3014, a fifth layout unit 3015, a sixth layout unit 3016, a seventh layout unit 3017 and an eighth layout unit 3018, and are arranged in a 2×4 array on the first metal layer; wherein,

[0161] In the first row of the array, the fourth layout unit 3014, the second layout unit 3012, the third layout unit 3013 and the first layout unit 3011 are arranged in sequence from right to left; wherein the fourth layout unit 3014 is used to form a first NAND gate circuit ND1, the second layout unit 3012 is used to form a second NAND gate circuit ND2, the third layout unit 3013 is used to form a third NAND gate circuit ND3, and the first layout unit 3011 is used to form a first NAND gate circuit ND1;

[0162] In the second row of the array, the eighth layout unit 3018, the sixth layout unit 3016, the seventh layout unit 3017 and the fifth layout unit 3015 are arranged in sequence from right to left; wherein the eighth layout unit 3018 is used to form an eighth NAND gate circuit ND8, the sixth layout unit 3016 is used to form a sixth NAND gate circuit ND6, the seventh layout unit 3017 is used to form a seventh NAND gate circuit ND7, and the fifth layout unit 3015 is used to form a fifth NAND gate circuit ND5.

[0163] It should be noted that if Fig.13 As shown, in the layout 30 provided in the embodiment of the present disclosure, eight layout units can be formed, and in the first metal layer, the eight layout units are arranged in a 2×4 array. Among them, the layout units 301 arranged in the first row in the first layout mode are, from right to left, the fourth layout unit 3014, the second layout unit 3012, the third layout unit 3013 and the first layout unit 3011; the layout units 302 arranged in the second row in the second layout mode are, from right to left, the eighth layout unit 3018, the sixth layout unit 3016, the seventh layout unit 3017 and the fifth layout unit 3015.

[0164] It should be noted that, in conjunction with the reference Figure 2The first layout unit 3011 is used to form a first NAND gate circuit ND1, the second layout unit 3012 is used to form a second NAND gate circuit ND2, the third layout unit 3013 is used to form a third NAND gate circuit ND3, the fourth layout unit 3014 is used to form a fourth NAND gate circuit ND4, the fifth layout unit 3015 is used to form a fifth NAND gate circuit ND5, the sixth layout unit 3016 is used to form a sixth NAND gate circuit ND6, the seventh layout unit 3017 is used to form a seventh NAND gate circuit ND7, and the eighth layout unit 3018 is used to form an eighth NAND gate circuit ND8.

[0165] Furthermore, in some embodiments, Fig.14 As shown, redundant signal lines 3027 are arranged on the left and right sides of the first layout unit 3011 and the fifth layout unit 3015;

[0166] The sixth signal line 3026 and the fifth signal line 3025 are arranged in sequence on the left and right sides of the third layout unit 3013 and the seventh layout unit 3017;

[0167] The fourth signal line 3024 and the third signal line 3023 are arranged in sequence on the left and right sides of the second layout unit 3012 and the sixth layout unit 3016;

[0168] The second signal line 3022 and the first signal line 3021 are arranged in sequence on the left and right sides of the fourth layout unit 3014 and the eighth layout unit 3018 .

[0169] It should be noted that, in the first metal layer, the first layer of metal wires are distributed on both sides of each layout unit in a symmetrical structure, so that the layout is arranged neatly, which is conducive to the unified transmission of signals.

[0170] In some embodiments, the plurality of intermediate connecting lines can be divided into a first group of intermediate connecting lines and a second group of intermediate connecting lines; wherein,

[0171] In the second metal layer, corresponding to the positions of the fourth layout unit 3014, the second layout unit 3012, the third layout unit 3013 and the first layout unit 3011, a first group of intermediate connection lines and a first input interface signal line 6011 and a first output interface signal line 6012 are arranged;

[0172] In the second metal layer, corresponding to the positions of the eighth layout unit 3018, the sixth layout unit 3016, the seventh layout unit 3017 and the fifth layout unit 3015, a second group of intermediate connecting lines and a second input interface signal line 6021, a second output interface signal line 6022, a third input interface signal line 6031 and a third output interface signal line 6033 are arranged.

[0173] It should be noted that if Fig.12 and Fig.14 As shown, in the second metal layer at the corresponding positions of the fourth layout unit 3014, the second layout unit 3012, the third layout unit 3013 and the first layout unit 3011, a first group of intermediate connecting lines and a first input interface signal line 6011 and a first output interface signal line 6012 are arranged; wherein the first group of intermediate connecting lines may include a second signal transfer line 6041, a third signal transfer line one 6042, a fourth signal transfer line one 6043, a first NAND gate output signal transfer line 6044 and a sixth signal transfer line 6045.

[0174] In the first group of intermediate connecting lines, the second signal transfer line 6041 is used to transmit the second signal, the third signal transfer line 6042 is used to transmit the output signal of the fourth NAND gate circuit ND4, wherein the output signal of the fourth NAND gate circuit ND4 is the third signal; the fourth signal transfer line 6043 is used to transmit the output signal of the third NAND gate circuit ND3, wherein the output signal of the third NAND gate circuit ND3 is the fourth signal; the first NAND gate output signal transfer line 6044 is used to transmit the output signal of the first NAND gate circuit ND1, and the sixth signal transfer line 6045 is used to transmit the sixth signal.

[0175] It should also be noted that if Fig.12 As shown, since the third signal transmitted by the third signal line 3023 is the output signal of the fourth NAND gate circuit ND4, and the fourth signal line 3024 transmits the output signal of the third NAND gate circuit ND3. That is, the third signal line 3023 and the fourth signal line 3024 transmit the signal generated by the NAND gate circuit formed inside the layout 30, rather than the signal from the outside of the layout 30, so the third signal line 3023 and the fourth signal line 3024 are shorter in the figure, that is, they do not need to be connected to the external circuit not shown in the figure.

[0176] It should also be noted that if Fig.12 As shown, in the second metal layer at the corresponding positions of the eighth layout unit 3018, the sixth layout unit 3016, the seventh layout unit 3017 and the fifth layout unit 3015, a second group of intermediate connecting lines, a second input interface signal line 6021, a second output interface signal line 6022, a third input interface signal line 6031 and a third output interface signal line 6032 are arranged; wherein the second group of intermediate connecting lines may include an eighth NAND gate output signal transfer line 6051, a third signal transfer line 6052, a sixth NAND gate output signal transfer line 6053 and a fourth signal transfer line 6054.

[0177] In the second group of intermediate connecting lines, the eighth NAND gate output signal adapter line 6051 is used to transmit the output signal of the eighth NAND gate circuit ND8; the third signal adapter line 6052 is used to transmit the third signal transmitted by the third signal line 3023; the sixth NAND gate output signal adapter line 6053 is used to transmit the output signal of the sixth NAND gate circuit ND6; the fourth signal adapter line 6054 is used to transmit the fourth signal transmitted by the fourth signal line 3024.

[0178] In this way, the signals of the first metal layer are switched and transmitted through the first group of intermediate connecting lines and the second group of intermediate connecting lines.

[0179] It should also be noted that for Figures 5 to 14 In the figure, the signal lines that are not described in detail are other signal lines in the layout of the delay circuit unit, which are used to implement other functions of the circuit. Their specific functions are the same as the common understanding of those skilled in the art, and are not described in detail here.

[0180] In some embodiments, Fig.12 As shown, the first group of intermediate connection lines are used to connect part of the signal lines in the fourth layout unit 3014, the second layout unit 3012, the third layout unit 3013 and the first layout unit 3011 correspondingly on the first metal layer;

[0181] The second group of intermediate connection lines is used to connect part of the signal lines in the eighth layout unit 3018, the sixth layout unit 3016, the seventh layout unit 3017 and the fifth layout unit 3015 correspondingly on the first metal layer.

[0182] It should be noted that if Fig.12As shown, for the first group of intermediate connection lines, the specific connection method between them and the layout unit can be: the two connection points of the second signal adapter line 6041 are respectively connected to the connection point of the second signal line 3022 and the connection point of the second input signal line of the second layout unit 3012, so that the second signal can enter the second NAND gate circuit ND2 via the second signal line 3022 and the second signal adapter line 6041; the two connection points of the third signal adapter line 6042 are respectively connected to the connection point of the output signal line of the fourth layout unit 3014 and the connection point of the third signal line 3023, so that the third signal can be transmitted via the third signal adapter line 6042 and the third signal line 3023; The two connection points of the fourth signal transfer line 6043 are respectively connected to the connection point of the output signal line of the third layout unit 3014 and the connection point of the fourth signal line 3024, so that the fourth signal can be transmitted via the fourth signal transfer line 6043 and the fourth signal line 3024; the three connection points of the first NAND gate output signal transfer line 6044 are respectively connected to the connection point of the output signal line of the first layout unit 3011, the connection point of the first input signal line of the third layout unit 3013 and the connection point of the first input signal line of the second layout unit 3012, so that the output signal of the first NAND gate circuit ND1 is transmitted to the third NAND gate circuit ND3 and the second NAND gate circuit ND2.

[0183] The output signal of the first NAND gate circuit ND1 may be the aforementioned first NAND gate output signal NET12.

[0184] In addition, combined with reference Figure 5 For the first signal transmitted by the first signal line 3021 and the fifth signal transmitted by the fifth signal line 3025, since the first signal is transmitted to the second input signal line of the fourth layout unit 3014, and in the first metal layer, the second input signal line of the fourth layout unit 3014 is adjacent to the first signal line 3021; ​​therefore, for the simplicity and convenience of wiring, a first adjacent signal line 3031 extending along the second direction can be set in the first metal layer at this time, and the first signal line 3021 and the second input signal line of the fourth layout unit 3014 are connected through the first adjacent signal line 3031, so that the first signal is transmitted to the fourth NAND gate circuit ND4.

[0185] Similarly, since the fifth signal is transmitted to the second input signal line of the third NAND gate circuit 3013, and in the first metal layer, the second input signal line of the third layout unit 3013 is adjacent to the fifth signal line 3025; therefore, for the simplicity and convenience of wiring, a second adjacent signal line 3032 extending along the second direction can be set in the first metal layer at this time, and the fifth signal line 3025 and the second input signal line of the third layout unit 3013 are connected through the second adjacent signal line 3032, so that the fifth signal is transmitted to the third NAND gate circuit ND3.

[0186] That is to say, for the signal transmission between two adjacent signal lines in the first metal layer, there is no need to connect and transmit through the intermediate connection line in the second metal layer, but it can be realized by directly setting adjacent connection lines in the first metal layer. This not only makes the overall circuit layout simple and convenient, easy to process, but also avoids crosstalk between circuits.

[0187] It should also be noted that if Fig.12 As shown, for the second group of intermediate connecting lines, the specific connection method between them and each layout unit can be: the two connection points of the eighth NAND gate output signal adapter line 6051 are respectively connected to the connection point of the output signal line of the eighth layout unit 3018 and the connection point of the first input signal line of the seventh layout unit 3017, so that the output signal of the eighth NAND gate circuit ND8 is transmitted to the seventh NAND gate circuit ND7; the two connection points of the third signal adapter line 6052 are respectively connected to the connection point of the third signal line 3023 and the second signal output end of the sixth layout unit 3016, so that the third signal line 3023 and the third signal adapter line 6052 transmit the output signal of the eighth NAND gate circuit ND8 to the seventh NAND gate circuit ND7. The signal is transmitted to the sixth NAND gate circuit ND6; the two connection points of the sixth NAND gate output signal adapter line 6053 are respectively connected to the connection point of the output signal line of the sixth layout unit 3016 and the connection point of the second output signal line of the fifth layout unit 3015, thereby transmitting the output signal of the sixth NAND gate circuit ND6 to the fifth NAND gate circuit ND5; the two connection points of the fourth signal adapter line 6054 are respectively connected to the connection point of the fourth signal line 3024 and the second input signal line of the seventh layout unit 3017, thereby transmitting the fourth signal to the seventh NAND gate circuit ND7 through the fourth signal line 3024 and the fourth signal adapter line 6054.

[0188] The output signal of the eighth NAND gate circuit ND8 may be the aforementioned eighth NAND gate output signal NET78, and the output signal of the sixth NAND gate circuit ND6 may be the aforementioned sixth NAND gate output signal NET56.

[0189] In this way, the signal lines of the first metal layer and the second metal layer are connected correspondingly based on each connection point, thereby realizing signal transmission.

[0190] That is to say, for each NAND gate circuit formed by the layout unit in the layout 30, Fig.12 As shown, for the first layout unit 3011, its first input signal line is used to receive the first input interface signal (INF signal) transmitted by the first input interface signal line 6011; its second input signal line is used to receive the sixth signal transmitted via the sixth signal line 3026 and the sixth signal adapter line 6045; its output signal line is used to output the output signal of the first NAND gate circuit ND1.

[0191] For the third layout unit 3013, its first input signal line is used to receive the output signal of the first NAND gate circuit ND1 transmitted via the first NAND gate output signal adapter line 6044; its second input signal line is used to receive the fifth signal transmitted via the fifth signal line 3025 and the second adjacent signal line 3032; its output signal line is used to output the fourth signal; and the second adjacent signal line 3032 is laid out on the first metal layer.

[0192] For the second layout unit 3012, its first input signal line is used to receive the output signal of the first NAND gate circuit ND1 transmitted via the first NAND gate output signal adapter line 6044; its second input signal line is used to receive the second signal transmitted via the second signal line 3022 and the second signal adapter line 6041; its output signal line is used to output the first output interface signal (OUTF signal).

[0193] For the fourth layout unit 3014, its first input signal line is used to receive the first output interface signal (OUTF signal) transmitted via the first output interface signal line 6012, and the first output interface signal (OUTF signal) is the output signal of the second NAND gate circuit ND2; its second input signal line is used to receive the first signal transmitted via the first signal line 3021 and the first adjacent signal line 3031; its output signal line is used to output a third signal; wherein, the first adjacent signal line 3031 is laid out on the first metal layer.

[0194] For the eighth layout unit 3018, its first input signal line is used to receive the third input interface signal (INE signal) transmitted by the third input interface signal line 6031; its second input signal line is connected to the power supply terminal vdd to receive the power supply signal (vdd signal); its output signal line is used to output the output signal of the eighth NAND gate circuit ND8.

[0195] For the sixth layout unit 3016, its first input signal line is used to receive the second input interface signal (INE signal) transmitted by the second input interface signal line 6021; its second input signal line is used to receive the third signal transmitted via the third signal adapter line 6042, the third signal line and the third signal adapter line 6052; its output signal line is used to output the output signal of the sixth NAND gate circuit ND6.

[0196] For the seventh layout unit 3017, its first input signal line is used to receive the output signal of the eighth NAND gate circuit ND8 transmitted by the eighth NAND gate output signal adapter line 6051; its second input signal line is used to receive the fourth signal transmitted via the fourth signal adapter line 6043, the fourth signal line 3024 and the fourth signal adapter line 6054; its output signal line is used to output the first output interface signal (OUTE signal).

[0197] For the fifth layout unit 3015, its first input signal line is used to receive the sixth NAND gate output signal transmitted by the sixth NAND gate output signal adapter line 6053; its second input signal line is connected to the power supply terminal vdd to receive the power supply signal (vdd signal); its output signal line is used to output the third output interface signal (OUTO signal).

[0198] In this way, the first metal layer and the second metal layer are connected through the signal lines in the first metal layer and the second metal layer, so that each input signal can be transmitted to the first input signal line or the second input signal line of the NAND gate circuit of the delay circuit unit, and the output signal of each NAND gate circuit can be transmitted to other NAND gate circuits, or directly output. The entire circuit layout is compact, highly integrated, and simple and easy to process.

[0199] The disclosed embodiment provides a layout of a delay circuit unit, the layout includes a plurality of layout units, the layout units are used to form a NAND gate circuit, and the layout units are arranged in an array; wherein, in the first row of the array, a plurality of layout units conforming to a first layout mode are sequentially arranged; in the second row of the array, a plurality of layout units conforming to a second layout mode are sequentially arranged; wherein, the first layout mode is different from the second layout mode, and the first layout mode and the second layout mode make the first row and the second row present a central symmetric structure. In this way, it is not only conducive to achieving the consistency of delay between signals of different phases, but also the overall layout of the delay circuit unit is compact, and the layout area can be saved.

[0200] In another embodiment of the present disclosure, see Fig.15 , which shows a schematic diagram of a layout structure of a delay circuit provided by an embodiment of the present disclosure, the delay circuit may include the aforementioned first metal layer and second metal layer, Fig.15FIG. 3 is a schematic diagram showing the overall arrangement of the first metal layer. The delay circuit includes N delay circuit units, each of which corresponds to the layout 30 described in the above embodiment. Fig.11 As shown, the layout of the delay circuit includes the layouts 30 of several aforementioned delay circuit units, wherein N is an integer greater than zero.

[0201] The delay circuit may be, for example, a delay phase-locked loop circuit.

[0202] In some embodiments, the layout of the delay circuit is composed of layouts of N delay circuit units cascaded; wherein,

[0203] The first input interface signal input by the first layout is the first output interface signal output by the second layout;

[0204] The second input interface signal input by the second layout is the second output interface signal output by the first layout;

[0205] The third input interface signal input by the second layout is the third output interface signal output by the first layout;

[0206] The first layout and the second layout represent the layouts of two adjacent delay circuit units in the layout of the delay circuit.

[0207] It should be noted that see Fig.16 , which shows a schematic diagram of the layout structure of another delay circuit provided by an embodiment of the present disclosure, and shows a schematic diagram of the overall arrangement of the second metal layer. Fig.16 As shown, for the delay circuit, the first input interface signal (INF signal), the first output interface signal (OUTF signal), the second input interface signal (INE signal), the second output interface signal (OUTE signal), the third input interface signal (INO signal) and the third output interface signal (OUTO signal) of each delay circuit unit (CDL unit) are all input and output through the second-layer signal line, and each CDL unit maintains the same signal line layout and spacing, thereby achieving unified signal delay.

[0208] It should also be noted that if Fig.16As shown, taking the first CDL unit from the left as the second layout and the second CDL unit from the left as the first layout as an example; the first input interface signal (INF signal) input by the first layout is the first output interface signal (OUTF signal) output by the second layout; the second input interface signal (INE signal) input by the second layout is the second output interface signal (OUTE signal) output by the first layout; the third input interface signal (INO signal) input by the second layout is the third output interface signal (OUTO signal) output by the first layout; through this signal transmission method, the layouts 30 of N delay circuit units are cascaded to form a layout of a delay circuit.

[0209] As for the layout of the delay circuit, since it is composed of N cascaded layouts 30, it can not only achieve the uniform delay of signal transmission within the layout 30, but also achieve the uniform delay between the N layouts 30, so that all signal lengths on the entire delay chain are consistent in the layout.

[0210] In another embodiment of the present disclosure, see Fig.17 , which shows a schematic diagram of the composition structure of a semiconductor memory 130 provided by an embodiment of the present disclosure, such as Fig.17 As shown, the semiconductor memory 130 includes a delay circuit corresponding to the layout of the delay circuit described in any of the aforementioned embodiments.

[0211] Among them, the semiconductor memory may include a dynamic random access memory (DRAM), a static random access memory (SRAM), a magnetic random access memory (MRAM), etc., and the embodiments of the present disclosure do not specifically limit this. The embodiments of the present disclosure do not specifically limit this. For the semiconductor memory 130, since the semiconductor memory can include a delay circuit corresponding to the layout of the aforementioned delay circuit, it can not only achieve the delay uniformity of the signal transmission within the layout of the delay circuit unit, but also achieve the delay uniformity between the layouts of N delay circuit units.

[0212] The above description is only a preferred embodiment of the present disclosure and is not intended to limit the protection scope of the present disclosure.

[0213] It should be noted that in the present disclosure, the terms "include", "comprises" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "includes a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0214] The serial numbers of the above-mentioned embodiments of the present disclosure are only for description and do not represent the advantages or disadvantages of the embodiments.

[0215] The methods disclosed in several method embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0216] The features disclosed in several product embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new product embodiments.

[0217] The features disclosed in several method or device embodiments provided in the present disclosure may be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0218] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A layout of a delay circuit unit, characterized in that: The layout includes a plurality of layout units, the layout units are used to form a NAND gate circuit, and the layout units are arranged in an array; wherein, In the first row of the array, a plurality of layout units conforming to a first layout manner are sequentially arranged; In the second row of the array, a plurality of layout units conforming to the second layout mode are sequentially arranged; The first layout is different from the second layout, and the first layout and the second layout make the first row and the second row present a central symmetrical structure; Wherein, the layout unit at least includes a first input signal line, a second input signal line and an output signal line; wherein, In the first layout mode, the arrangement order of the signal lines of the layout unit from right to left is: the second input signal line, the output signal line, and the first input signal line; In the second layout manner, the arrangement order of the signal lines of the layout unit from right to left is: the first input signal line, the output signal line, and the second input signal line.

2. The layout according to claim 1, characterized in that The layout is divided into at least a first metal layer and a second metal layer, and the second metal layer is located on the first metal layer; wherein, The first metal layer is used for laying out the first input signal line, the second input signal line, the output signal line and the first layer signal line; The second metal layer is used for laying out the second layer of signal lines; The first input signal line, the second input signal line, the output signal line and the first layer signal line are all wired along a first direction, the second layer signal line is wired along a second direction, and the angle between the first direction and the second direction is 90 degrees.

3. The layout according to claim 2, characterized in that The first layer of signal lines at least includes: a first signal line, a second signal line, a third signal line, a fourth signal line, a fifth signal line and a sixth signal line; The second layer of signal lines at least includes: a first input interface signal line, a first output interface signal line, a second input interface signal line, a second output interface signal line, a third input interface signal line and a third output interface signal line.

4. The layout according to claim 3, characterized in that The first layer of signal lines are arranged on both sides of each of the layout units; wherein, The arrangement order of the first layer of signal lines from right to left is: the first signal line, the second signal line, the third signal line, the fourth signal line, the fifth signal line and the sixth signal line.

5. The layout according to claim 4, characterized in that The first layer of signal lines also includes a number of redundant signal lines, wherein: The first layer of signal lines are arranged in the order from right to left: the first signal line, the second signal line, the third signal line, the fourth signal line, the fifth signal line, the sixth signal line and the plurality of redundant signal lines.

6. The layout according to claim 3, characterized in that In the first metal layer, a plurality of first-layer signal lines have the same width, and a distance between every two adjacent signal lines is the same.

7. The layout according to claim 3, characterized in that The second layer of signal lines also includes a plurality of intermediate connecting lines, and each of the intermediate connecting lines is provided with a connecting point; wherein, The plurality of intermediate connection lines are used to connect the signal lines provided with connection points in the first metal layer, so as to transmit the target signal to the corresponding NAND gate circuit.

8. The layout according to claim 7, characterized in that The plurality of layout units include a first layout unit, a second layout unit, a third layout unit, a fourth layout unit, a fifth layout unit, a sixth layout unit, a seventh layout unit and an eighth layout unit, and are arranged in a 2×4 array on the first metal layer; wherein, In the first row of the array, the fourth layout unit, the second layout unit, the third layout unit and the first layout unit are sequentially arranged from right to left; wherein the fourth layout unit is used to form a fourth NAND gate circuit, the second layout unit is used to form a second NAND gate circuit, the third layout unit is used to form a third NAND gate circuit, and the first layout unit is used to form a first NAND gate circuit; In the second row of the array, the eighth layout unit, the sixth layout unit, the seventh layout unit and the fifth layout unit are arranged in sequence from right to left; wherein the eighth layout unit is used to form an eighth NAND gate circuit, the sixth layout unit is used to form a sixth NAND gate circuit, the seventh layout unit is used to form a seventh NAND gate circuit; and the fifth layout unit is used to form a fifth NAND gate circuit.

9. The layout according to claim 8, characterized in that Redundant signal lines are arranged on the left and right sides of the first layout unit and the fifth layout unit; The sixth signal line and the fifth signal line are sequentially arranged on the left side and the right side of the third layout unit and the seventh layout unit; The fourth signal line and the third signal line are sequentially arranged on the left and right sides of the second layout unit and the sixth layout unit; The second signal line and the first signal line are arranged in sequence on the left side and the right side of the fourth layout unit and the eighth layout unit.

10. The layout according to claim 9, characterized in that The plurality of intermediate connecting lines are divided into a first group of intermediate connecting lines and a second group of intermediate connecting lines; wherein, In the second metal layer, the first group of intermediate connection lines, the first input interface signal line, and the first output interface signal line are arranged corresponding to the positions of the fourth layout unit, the second layout unit, the third layout unit, and the first layout unit; In the second metal layer, corresponding to the positions of the eighth layout unit, the sixth layout unit, the seventh layout unit and the fifth layout unit, the second group of intermediate connecting lines and the second input interface signal line, the second output interface signal line, the third input interface signal line and the third output interface signal line are arranged.

11. The layout according to claim 10, characterized in that The first group of intermediate connection lines is used to connect the fourth layout unit, the second layout unit, the third layout unit and some signal lines in the first layout unit correspondingly on the first metal layer; The second group of intermediate connection lines is used to connect part of the signal lines in the eighth layout unit, the sixth layout unit, the seventh layout unit and the fifth layout unit correspondingly on the first metal layer.

12. A layout according to any one of claims 2 to 11, characterized in that The NAND gate circuit includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor and a second NMOS transistor; the second metal layer also includes a power line and a ground line; wherein, The power lines are respectively connected to the source electrodes of the first PMOS tube and the second PMOS tube; The grounding line is connected to the source of the first NMOS tube; The first input signal line is connected to the gate of the second PMOS transistor and the gate of the second NMOS transistor respectively; The second input signal line is connected to the gate of the first PMOS transistor and the gate of the first NMOS transistor respectively; The output signal line is connected to the drain of the first PMOS tube, the drain of the second PMOS tube, and the drain of the second NMOS tube respectively.

13. A layout of a delay circuit, characterized in that: The delay circuit includes N delay circuit units, each of which corresponds to the layout according to any one of claims 1 to 12; wherein N is an integer greater than zero.

14. The layout of the delay circuit according to claim 13, characterized in that: The layout of the delay circuit is composed of N layouts of the delay circuit units cascaded; wherein, The first input interface signal input by the first layout is the first output interface signal output by the second layout; The second input interface signal input by the second layout is the second output interface signal output by the first layout; The third input interface signal input by the second layout is the third output interface signal output by the first layout; The first layout and the second layout represent the layouts of two adjacent delay circuit units in the layout of the delay circuit.

15. A semiconductor memory, characterized in that: A delay circuit corresponding to the layout of the delay circuit as claimed in any one of claims 13 to 14.

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