A silicon-based fan-out wafer-level packaging method and packaging structure

Abstract

The present invention discloses a silicon-based fan-out wafer-level packaging method and packaging structure, which belongs to the field of integrated circuit packaging. A silicon base is provided, and a trench groove and a large cavity are formed in sequence on the front side thereof; the back side of the silicon base is ground to form a through groove in the large cavity; the silicon base and the embedded chip are fixed on the plastic encapsulation carrier in sequence through temporary bonding glue by using a facedown process; the embedded chip, the silicon base gap and the trench groove are filled with plastic encapsulation material by using a plastic encapsulation process; the plastic encapsulation carrier is removed and the temporary bonding glue is cleaned to form a reconstructed wafer; a passivation layer, a multi-layer wiring layer and a solder mask layer are sequentially made on the front side of the wafer; the back side of the wafer is ground, thinned and laser marked; micro bumps are made on the front side of the wafer, and then the wafer is cut into single packaged chips to complete the packaging. The use of through grooves solves the problem of chip cracks or silicon-based fragments caused by silicon protrusions at the bottom of the grooves in the existing patch process; the wafer uses silicon as the matrix, which can improve the warping and offset problems in the tape-out process and improve the wiring density.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit packaging, and in particular to a silicon-based fan-out wafer-level packaging method and packaging structure. Background Art

[0002] As chip manufacturing nodes continue to decrease and Moore's Law approaches its limit, microsystem technology based on high-performance wafer-level packaging is an inevitable choice in the post-Moore era. Packaging is becoming increasingly important for improving the overall performance of chips, and is also an important component in promoting the development of miniaturization, intelligence, multi-functions and low power consumption of electronic devices. In the post-Moore era, the prospect of advanced packaging is to achieve heterogeneous chip integration, but there is still a long way to go to achieve this goal.

[0003] Among them, fan-out wafer-level packaging can realize heterogeneous / heterogeneous chip integration, while reducing the package size and improving the performance of microsystem components with high integration. Mainstream fan-out packages mainly include resin fan-out packages and silicon-based fan-out packages. Resin fan-out packages use epoxy mold compounds (EMC) to reconstruct wafers and are currently the most widely used fan-out solution. Silicon-based fan-out packages have the advantages of low cost, small warpage, high wiring density, good heat dissipation and simple process compared to resin fan-out packages, making it easier to achieve system integration of large chips. However, from the perspective of dry etching, the silicon protrusions at the bottom of the grooves of existing silicon-based fan-out packages cause cracks or silicon-based fragments when the die attach process embeds the chip. At the same time, the etching morphology, etching depth uniformity and footing affect the dry film filling quality, and the bubble problem will cause stratification abnormalities. The dry etching morphology, especially the etching angle process window, is extremely small, and debugging is difficult and the cycle is long. The existing silicon-based fan-out package has insufficient integration capabilities for chips with different depths. Although multiple dry etchings can solve this problem, it will increase the packaging process, delivery time and cost, and different depths will also expand the dry film filling quality problem. Summary of the invention

[0004] The purpose of the present invention is to provide a silicon-based fan-out wafer-level packaging method and packaging structure to solve the problems of warping and offset of existing resin fan-out packaging, inability to perform high-density wiring, and chip cracks or silicon-based fragments caused by silicon protrusions at the bottom of the groove during the patch process.

[0005] In order to solve the above technical problems, the present invention provides a silicon-based fan-out wafer-level packaging method, comprising:

[0006] Providing a silicon base, and sequentially forming a trench and a large cavity on the front side thereof;

[0007] Grinding the back side of the silicon substrate to form a through-groove with a large cavity;

[0008] The silicon-based and embedded chips are fixed on the plastic package carrier in turn by temporary bonding adhesive using a face-down process;

[0009] The plastic encapsulation process is used to fill the plastic encapsulation material into the embedded chip, silicon base gap and trench;

[0010] Remove the plastic-encapsulated carrier and clean the temporary bonding adhesive to form a reconstructed wafer;

[0011] A passivation layer, multi-layer wiring, and solder mask layer are sequentially fabricated on the front side of the wafer;

[0012] Grinding, thinning and laser marking on the back of the wafer;

[0013] Micro-bumps are made on the front side of the wafer, and then the wafer is cut into single packaged chips to complete the packaging.

[0014] Optionally, two dry etching processes are performed on the front side of the silicon substrate to form a trench and a large cavity in sequence; wherein,

[0015] The trench groove is etched in sections, and the width, length and depth of the groove body are not less than 10 μm; the opening of the trench groove is chamfered at 45°-60°, and the chamfer is not less than 3 μm; the trench grooves are interconnected, and there is not less than one interconnection channel between adjacent trench grooves.

[0016] Optionally, the large cavity is made at the bottom of the trench groove, the large cavity is etched in segments, the depth of the large cavity is not less than 50 μm, and the number of the large cavity is 1 or more; the side wall profile of the large cavity is a straight line, and the angle with the horizontal plane is 87±3°; the upper opening of the large cavity is chamfered at 45°-60°, and the chamfer height is not less than 3 μm.

[0017] Optionally, the silicon-based, embedded chip is fixed on the plastic package carrier by a face down process through temporary bonding adhesive, including:

[0018] The trench forms a bridge between the silicon base and the temporary bonding adhesive, and serves as an interconnection channel for subsequent plastic encapsulation, glue injection, and exhaust.

[0019] The embedded chip is located in the through groove of the silicon base and is fixed on the plastic package carrier by temporary bonding glue.

[0020] Optionally, the temporary bonding adhesive is a polymer material with a thickness of not less than 1 μm.

[0021] Optionally, the molding compound is epoxy resin, or other resin-based or polyimide-based polymer materials.

[0022] The present invention also provides a silicon-based fan-out wafer-level packaging structure, which is manufactured by the silicon-based fan-out wafer-level packaging method.

[0023] The silicon-based fan-out wafer-level packaging method and packaging structure provided by the present invention have the following beneficial effects:

[0024] (1) The use of through-grooves solves the problem of chip cracks or silicon-based fragments caused by silicon protrusions at the bottom of the grooves during the existing silicon-based fan-out packaging process; the trench bridge structure makes the plastic encapsulation process feasible; the trench bridge structure serves as an interconnection channel to achieve plastic encapsulation glue injection and exhaust functions, effectively reducing or even avoiding the generation of cavities and bubbles, and reducing the risk of package delamination and cracking;

[0025] (2) The embedded chip and silicon substrate are fixed on the same horizontal plane through a temporary bonding film using the Face down process, which solves the problems of silicon protrusions in grooves, uniformity of groove depth, etching morphology, and flattening caused by footing in existing silicon-based fan-out packaging. From the perspective of dry etching process, the embedded chip and silicon substrate are fixed on the plastic encapsulation carrier through a temporary bonding film using the Face down process and the plastic encapsulation is completed. The process window of the angle of the silicon substrate through the side wall of the groove is significantly increased, which reduces the debugging cycle and debugging cost, and further improves the process stability.

[0026] (3) Using a plastic encapsulation process, epoxy resin is filled into the embedded chip, silicon-based gaps, and trenches to reconstruct the wafer; the wafer is based on silicon, which can improve the warping and offset problems that exist during the tape-out process and increase the wiring density;

[0027] (4) Segmented etching forms chamfers, effectively reducing the risk of cracking caused by stress concentration at sharp corners; using plastic encapsulation technology to replace the dry film filling commonly used in existing silicon-based fan-out packaging with epoxy resin, greatly reducing packaging costs;

[0028] (5) The present invention provides a silicon-based fan-out wafer-level packaging method, which has a simple process, low cost, and is suitable for large-scale mass production. The packaging body uses silicon as the base, and the heat dissipation capacity is significantly enhanced. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 It is a schematic diagram of the process flow of the silicon-based fan-out wafer-level packaging method provided by the present invention;

[0030] Figure 2 It is a schematic diagram of etching trenches in sections on the front side of the silicon substrate;

[0031] Figure 3 It is a schematic diagram of forming a large cavity in the trench by segmented etching;

[0032] Figure 4It is a schematic diagram of the trench and the chamfer of the large cavity;

[0033] Figure 5 It is a schematic diagram of grinding and thinning the back side of the silicon substrate to form a through groove with a large cavity;

[0034] Figure 6 It is a schematic diagram of the front side of the silicon substrate being bonded to the plastic package carrier and the chip being embedded;

[0035] Figure 7 It is a schematic diagram of epoxy resin filling the gap between the embedded chip and the silicon substrate and the trench;

[0036] Figure 8 is a schematic diagram of removing the plastic-sealed carrier and cleaning the residual temporary bonding film;

[0037] Fig. 9 It is a schematic diagram of manufacturing a passivation layer, multi-layer wiring and solder mask layer on the front side of a reconstructed wafer;

[0038] Fig.10 It is a schematic diagram of grinding and thinning the back side of the reconstructed wafer without exposing the silicon base;

[0039] Fig.11 It is a schematic diagram of grinding and thinning the back side of the reconstructed wafer to expose the silicon base but not the chip;

[0040] Fig.12 It is a schematic diagram of grinding and thinning the back side of the reconstructed wafer to the chip sacrificial layer;

[0041] Fig.13 It is a schematic diagram of making micro bumps on the front side by ball planting or printing;

[0042] Fig.14 It is a schematic diagram of the packaging structure of a single packaged chip. DETAILED DESCRIPTION

[0043] The following is a further detailed description of a silicon-based fan-out wafer-level packaging method and packaging structure proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description and claims. It should be noted that the drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0044] Embodiment 1

[0045] The present invention provides a silicon-based fan-out wafer-level packaging method, the process of which is as follows: Figure 1 As shown, the following steps are included:

[0046] Step S01, providing a silicon substrate, and performing two dry etching processes on the front surface thereof to sequentially form a trench and a large cavity;

[0047] Step S02, grinding and thinning the back of the silicon substrate to form a through groove with a large cavity;

[0048] Step S03, the silicon-based and embedded chips are fixed on the plastic package carrier in sequence by temporary bonding adhesive using a face down process;

[0049] Step S04, using a plastic encapsulation process to fill the embedded chip, silicon-based gaps and trenches with epoxy resin, extending beyond the plastic encapsulation carrier, to form a reconstructed wafer;

[0050] Step S05, sequentially manufacturing a passivation layer, a multi-layer wiring layer, and a solder resist layer on the front side of the reconstructed wafer;

[0051] Step S06, grinding, thinning, and laser marking are sequentially performed on the back side of the reconstructed wafer;

[0052] Step S07: making micro bumps on the front side of the reconstructed wafer, and then cutting it into single packaged chips.

[0053] A silicon substrate 101 is provided, and trenches 102 are etched in sections on the front surface of the silicon substrate 101, such as Figure 2 As shown, the length, width and depth of the trench groove 102 are not less than 10 μm, the upper opening of the trench groove 102 is chamfered at 45°-60°, and the chamfer height is not less than 3 μm. Figure 4 shown.

[0054] Then, a segmented etching is performed in the trench 102 to form Figure 3 The large cavity 201 shown in the figure has a depth of not less than 50 μm and a number of one or more large cavities; the sidewall profile of the large cavity 201 is straight and is at an angle of 87±3° to the horizontal plane; the upper opening of the large cavity 201 is chamfered at 45°-60°, and the chamfer height is not less than 3 μm, as shown in FIG. Figure 4 Finally, the back of the silicon substrate 101 is ground and thinned to a target thickness so that the large cavity 201 forms a through groove 103, and then cleaned. Figure 5 As shown;

[0055] Then, the front side of the thinned silicon substrate 101 is bonded to the plastic package carrier 203 through a temporary bonding film 202. Figure 6 As shown;

[0056] Then, the embedded chips 301 and 302 are loaded into the through grooves 103, and the embedded chips 301 and 302 are fixed on the plastic package carrier 203 in the through grooves 103 by means of temporary bonding adhesive 202. Figure 6As shown; the embedded chip can be a heterogeneous or heterogeneous chip such as FPGA, DSP, GPU, CPU, bridge chip, etc. The number of embedded chips in the through groove 103 is 1 or more, and embedded chips with the same thickness or different thicknesses can be loaded, and the thickness of the embedded chip is required to be less than the thickness of the reconstructed wafer; the embedded chip can be preset with a sacrificial layer according to the packaging size requirements.

[0057] Using a resin-based molding process, epoxy resin 104 is used to fill the gaps between the embedded chips 301, 302 and the silicon substrate 101 and the trench 102. Figure 7 As shown; then the bonded plastic carrier 203 is released by thermal debonding, and the residual temporary bonding film 202 is cleaned and the wafer is reconstructed, as shown Figure 8 shown.

[0058] like Fig. 9 A passivation layer 105 is formed on the front side of the reconstructed wafer by spin coating, and a hole is opened at the chip pad 303 by photolithography; and then the multi-layer wiring 106 and the solder mask 107 are formed by photolithography, physical vapor deposition, electroplating and chemical plating in sequence.

[0059] After that, the back of the reconstructed wafer is ground and thinned, and then laser marking is completed in sequence. After grinding and thinning, the back of the wafer may not expose the silicon base, such as Fig.10 As shown; after grinding and thinning, the back of the wafer can expose the silicon base but not the chip, as shown Fig.11 As shown; after grinding and thinning, the back side of the wafer can also be ground to the chip sacrificial layer (i.e., non-functional area), such as Fig.12 As shown; the specific method can be selected according to the silicon base thickness, embedded chip size and customer packaging size requirements.

[0060] Next, micro bumps 108 are formed on the front side by ball planting or printing. Fig.13 As shown; the packaging structure of a single packaged chip, such as Fig.14 shown.

[0061] Embodiment 2

[0062] The second embodiment provides a silicon-based fan-out wafer-level packaging structure, which is manufactured by the method of the first embodiment. Fig.14 The silicon-based fan-out wafer-level packaging structure includes a silicon base 101, a through groove is formed in the silicon base 101, and a plastic encapsulation material 104 is filled in the gap between the chip and the silicon base 101; a passivation layer 105, a multi-layer wiring 106, a solder mask 107 and micro bumps 108 are sequentially formed on the front side.

[0063] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A silicon-based fan-out wafer-level packaging method, characterized in that: include: Providing a silicon base, and sequentially forming a trench and a large cavity on the front side thereof; Grinding the back side of the silicon substrate to form a through-groove with a large cavity; The silicon-based and embedded chips are fixed on the plastic package carrier in turn by temporary bonding adhesive using a face-down process; The plastic encapsulation process is used to fill the plastic encapsulation material into the embedded chip, silicon base gap and trench; Remove the plastic-encapsulated carrier and clean the temporary bonding adhesive to form a reconstructed wafer; A passivation layer, multi-layer wiring, and solder mask layer are sequentially fabricated on the front side of the wafer; Grinding, thinning and laser marking on the back of the wafer; Make micro bumps on the front side of the wafer, then cut the wafer into individual packaged chips to complete the packaging; Two dry etchings are performed on the front side of the silicon substrate to form trenches and large cavities in sequence; The trench groove is etched in sections, and the width, length and depth of the groove body are not less than 10 μm; the upper opening of the trench groove is chamfered at 45°-60°, and the chamfer is not less than 3 μm; The large cavity is made at the bottom of the trench groove, and the large cavity is etched in sections, with a depth of not less than 50 μm and one or more large cavities; the sidewall profile of the large cavity is a straight line, and is at an angle of 87±3° to the horizontal plane; the upper opening of the large cavity is chamfered at 45°-60°, and the chamfer height is not less than 3 μm.

2. The silicon-based fan-out wafer-level packaging method according to claim 1, characterized in that: The silicon-based, embedded chip is fixed on the plastic package carrier by temporary bonding adhesive using the face down process, including: The trench forms a bridge between the silicon base and the temporary bonding adhesive, and serves as an interconnection channel for subsequent plastic encapsulation, glue injection, and exhaust; The embedded chip is located in the through groove of the silicon base and is fixed on the plastic package carrier by temporary bonding glue.

3. The silicon-based fan-out wafer-level packaging method according to claim 2, characterized in that: The temporary bonding glue is a polymer material with a thickness of not less than 1 μm.

4. The silicon-based fan-out wafer-level packaging method according to claim 1, characterized in that: The plastic encapsulation material is epoxy resin, or other resin-based or polyimide-based polymer materials.

5. A silicon-based fan-out wafer-level packaging structure, characterized in that: It is manufactured by the silicon-based fan-out wafer-level packaging method described in any one of claims 1-4.

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