Method for manufacturing semiconductor element packaging structure

Abstract

The present invention discloses a semiconductor element packaging structure and a manufacturing method thereof. In the manufacturing method, a wafer is provided, which defines a plurality of semiconductor elements and a plurality of mutually staggered cutting areas. Each semiconductor element includes at least one pad arranged on an active surface. The wafer is arranged on a temporary adhesive layer, and the wafer is cut along the plurality of cutting areas to form a plurality of semiconductor elements separated from each other. The spacing between the plurality of semiconductor elements is expanded, and the plurality of expanded semiconductor elements are all arranged on a carrier board. A molding material is formed to cover the plurality of semiconductor elements to form an initial packaging body. The molding material is filled between the plurality of semiconductor elements to connect the plurality of semiconductor elements. The initial packaging body is separated from the carrier board and a cutting step is performed on the initial packaging body to form a plurality of semiconductor element packaging structures. The above method can reduce manufacturing costs and reduce packaging volume.

Description

Technical Field

[0001] The invention relates to a method for manufacturing a semiconductor element packaging structure, and in particular to a method for manufacturing a semiconductor element packaging structure without a substrate. Background Art

[0002] In the existing packaging technology, the chip is usually placed on a lead frame or a packaging substrate by wire bonding technology or surface-mount technology, and then the chip and the lead frame or the packaging substrate are packaged together with a molding compound to form an electronic component packaging structure, such as a Quad Flat None-lead Package (QFN) structure or a Dual Flat No-lead Package (DFN) structure. However, the volume of the electronic packaging structure with a lead frame or a packaging substrate is difficult to further reduce.

[0003] In order to further reduce the volume of electronic component packaging structures, the Wafer Level Chip Scale Package (WLCSP) process and the Fan-Out WLP process have become commonly used technical means for packaging chips. In the wafer level chip scale packaging process or the fan-out wafer level packaging process, in order to minimize the volume of the chip after packaging, the entire wafer will be thinned first, and then the thinned wafer will be cut. After forming multiple separate chips, the multiple chips are packaged again.

[0004] In one of the conventional chip package manufacturing methods, the upper surface of the wafer is first cut to form a plurality of grooves, a patterned photoresist layer is then formed in the grooves, and then the lower surface of the wafer is thinned. After that, an insulating layer is formed on the lower surface of the wafer, and then the patterned photoresist layer and the insulating layer are cut along the grooves to form a plurality of chip packages.

[0005] However, when using the above process to make chip packages, the width of the groove needs to be greater than the width of the cutting tool to avoid damaging the chip when cutting the patterned photoresist layer and the insulating layer. In addition, the width of the wafer's cutting path must be wider than the width of the groove to avoid damaging the chip when forming the groove. In other words, when using the above process to package chips, the width of the wafer's cutting path will be limited by subsequent processes and cannot be reduced. In this way, a portion of the wafer area will be reserved as a cutting path and cannot be used to make components, resulting in a reduction in the number of chips that can be produced on a wafer, which is not conducive to reducing process costs. Summary of the invention

[0006] The technical problem to be solved by the present invention is to provide a semiconductor element packaging structure and a manufacturing method thereof in view of the shortcomings of the prior art, which can form a protective layer on the side surface of the chip after cutting, and form a protective layer on at least one of the front and back sides of the chip, thereby forming an electronic element package. In addition, the width of the cutting path can be further reduced, thereby increasing the area of ​​the wafer used for making components, thereby reducing the manufacturing cost.

[0007] In order to solve the above-mentioned technical problems, one of the technical solutions adopted by the present invention is to provide a method for manufacturing a semiconductor element packaging structure, which includes: providing a wafer, wherein the wafer defines a plurality of semiconductor elements and a plurality of mutually staggered cutting areas, wherein each semiconductor element includes at least one pad arranged on an active surface; placing the wafer on a temporary adhesive layer, and cutting the wafer along the plurality of cutting areas to form a plurality of semiconductor elements separated from each other; expanding the spacing between the plurality of semiconductor elements; placing all the expanded plurality of semiconductor elements on a carrier board; forming a molding material to cover the plurality of semiconductor elements to form an initial packaging body, wherein the molding material is filled between the plurality of semiconductor elements to connect the plurality of semiconductor elements, the initial packaging body having a first side and a second side, and the active surface and a bottom surface of each semiconductor element correspond to the first side and the second side respectively; separating the initial packaging body from the carrier board; and performing a cutting step on the initial packaging body to form a plurality of semiconductor element packaging structures.

[0008] Furthermore, in the step of placing all the expanded semiconductor components on the carrier, the active surface of each semiconductor component faces the carrier, and the molding material covers the bottom surface of each semiconductor component but does not cover the active surface of each semiconductor component.

[0009] Furthermore, the method for manufacturing the semiconductor device package structure further comprises: after separating the initial package body and the carrier board, performing a thinning step from the second side of the initial package body to expose each semiconductor device on the second side of the initial package body.

[0010] Furthermore, the method for manufacturing the semiconductor device package structure further comprises: after performing a thinning step on the second side of the initial package body, forming a conductive and thermally conductive layer on the second side of the initial package body, wherein the conductive and thermally conductive layer directly contacts the bottom surface of each semiconductor device.

[0011] Furthermore, the cutting step is directly performed after the thinning step is performed from the second side of the initial package.

[0012] Furthermore, the width of the cutting area is 40 μm to 80 μm, and after the expanded plurality of semiconductor elements are disposed on the carrier board, the interval between any two semiconductor elements is 100 μm to 200 μm.

[0013] Furthermore, in the step of forming the initial package, all of the multiple semiconductor elements are set on a carrier board, and the step of forming the initial package includes: sandwiching the multiple semiconductor elements between a first sheet molding material and a second sheet molding material, wherein the first sheet molding material, the second sheet molding material and any two semiconductor elements together define a gap; and setting the first sheet molding material, the multiple semiconductor elements and the second sheet molding material on the carrier board, and pressing the first sheet molding material and the second sheet molding material to form a molding material that fills the gap and completely covers each semiconductor element.

[0014] Furthermore, after forming the initial package, the molding material covers the active surface and bottom surface of each semiconductor element, so that each semiconductor element is completely buried in the molding material, and the manufacturing method further includes: performing a thinning step from the first side of the initial package to expose at least one pad of each semiconductor element.

[0015] Furthermore, after the thinning step is performed on the first side of the initial package, a first surface of the molding material is flush with at least one pad surface of each semiconductor element.

[0016] Furthermore, before performing the cutting step, it further includes: performing another thinning step from the second side of the initial package to expose the bottom surface of each semiconductor element; and forming a conductive and thermally conductive layer on the second side of the initial package, wherein the conductive and thermally conductive layer covers and contacts the bottom surface of each semiconductor element.

[0017] In order to solve the above-mentioned technical problems, another technical solution adopted by the present invention is to provide a semiconductor element packaging structure without a substrate, which includes a semiconductor element, a molding layer and a conductive and thermally conductive layer. The semiconductor element has an active surface, a bottom surface opposite to the active surface, and a side surface connected between the active surface and the bottom surface. The semiconductor element includes at least one pad, which is arranged on the active surface. The molding layer covers the side surface of the semiconductor element and exposes the bottom surface of the semiconductor element. The molding layer has two opposite first surfaces and a second surface, and the second surface is coplanar with the bottom surface of the semiconductor element. The conductive and thermally conductive layer is arranged on the bottom surface of the semiconductor element and the second surface of the molding layer.

[0018] Furthermore, the total thickness of the semiconductor device package structure is between 25 μm and 150 μm.

[0019] Furthermore, the active surface of the semiconductor element is flush with a first surface of the molding layer.

[0020] Furthermore, the thickness of at least one pad is 5μm to 100μm, the encapsulation layer covers the active surface but exposes at least one pad, a height difference between the first surface and the active surface of the semiconductor element is between 10μm and 80μm, and the first surface is flush with the surface of at least one pad.

[0021] Furthermore, the thickness of the conductive and thermally conductive layer is between 1 μm and 5 μm, and the thickness of the semiconductor element is between 25 and 75 μm.

[0022] In order to solve the above technical problems, another technical solution adopted by the present invention is to provide a substrate-free semiconductor element packaging structure, which includes a semiconductor element and a mold encapsulation layer. The semiconductor element has an active surface, a bottom surface opposite to the active surface, and a side surface connected between the active surface and the bottom surface. The semiconductor element includes at least one pad, which is arranged on the active surface. The mold encapsulation layer covers the side surface of the semiconductor element and the bottom surface of the semiconductor element. The thickness of the mold encapsulation layer is between 10 and 50 μm, and has two opposite first surfaces and a second surface.

[0023] Furthermore, the active surface of the semiconductor element is flush with a first surface of the molding layer.

[0024] Furthermore, the thickness of at least one pad is 5μm to 100μm, the encapsulation layer covers the active surface of the semiconductor element but exposes at least one pad, a height difference between the first surface and the active surface of the semiconductor element is between 10μm and 80μm, and the first surface is flush with the surface of at least one pad.

[0025] One of the beneficial effects of the present invention is that the semiconductor element packaging structure and the manufacturing method provided by the present invention can further reduce the width of the cutting area, increase the number of semiconductor elements manufactured in the wafer, and thus reduce the manufacturing cost through the technical solutions of "setting the wafer on a temporary adhesive layer and cutting the wafer along multiple cutting areas to form multiple semiconductor elements separated from each other", "expanding the spacing between multiple semiconductor elements", "setting all the expanded multiple semiconductor elements on a carrier board" and "forming a molding material to cover the multiple semiconductor elements to form an initial package body". In addition, the semiconductor element packaging structure formed by the above method does not have a substrate, a lead frame or wire bonding, so it can have a smaller volume.

[0026] To further understand the features and technical contents of the present invention, please refer to the following detailed description and drawings of the present invention. However, the drawings provided are only for reference and description and are not intended to limit the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 The present invention is a flowchart of a method for manufacturing a semiconductor device packaging structure according to an embodiment of the present invention.

[0028] Figure 2 FIG. 1 is a schematic diagram of a method for manufacturing a semiconductor device packaging structure according to an embodiment of the present invention before step S100 .

[0029] Figure 3 for Figure 2 Schematic diagram of the local section along line III-III.

[0030] Figure 4 FIG. 1 is a schematic diagram of step S120 of the method for manufacturing a semiconductor device package structure according to an embodiment of the present invention.

[0031] Figure 5 FIG. 1 is a schematic diagram of a method for manufacturing a semiconductor device package structure in step S120 according to another embodiment of the present invention.

[0032] Figure 6 FIG. 1 is a schematic diagram of step S130 of the method for manufacturing a semiconductor device package structure according to an embodiment of the present invention.

[0033] Figure 7 FIG. 1 is a schematic diagram of step S140 of the method for manufacturing a semiconductor device package structure according to an embodiment of the present invention.

[0034] Figure 8 FIG. 1 is a schematic diagram of step S160 of the method for manufacturing a semiconductor device package structure according to an embodiment of the present invention.

[0035] Fig. 9FIG. 4 is a cross-sectional diagram of a semiconductor device packaging structure according to a first embodiment of the present invention.

[0036] Fig.10 The flowchart is a method for manufacturing a semiconductor device packaging structure according to another embodiment of the present invention.

[0037] Fig.11 The manufacturing method of the semiconductor device packaging structure according to the embodiment of the present invention is Fig.10 Schematic diagram of step S170.

[0038] Fig.12 FIG. 4 is a cross-sectional schematic diagram of a semiconductor device packaging structure according to a second embodiment of the present invention.

[0039] Fig.13 The manufacturing method of the semiconductor device packaging structure according to the embodiment of the present invention is Fig.10 Schematic diagram of step S180.

[0040] Fig.14 FIG. 4 is a cross-sectional view of a semiconductor device packaging structure according to a third embodiment of the present invention.

[0041] Fig.15 The flowchart is a method for manufacturing a semiconductor device packaging structure according to another embodiment of the present invention.

[0042] Fig.16 A method for manufacturing a semiconductor device packaging structure according to another embodiment of the present invention is Fig.15 Schematic diagram of step S230.

[0043] Fig.17 A method for manufacturing a semiconductor device packaging structure according to another embodiment of the present invention is Fig.15 Schematic diagram of step S230.

[0044] Fig.18 A method for manufacturing a semiconductor device packaging structure according to another embodiment of the present invention is Fig.15 Schematic diagram of step S250.

[0045] Fig.19 A method for manufacturing a semiconductor device packaging structure according to another embodiment of the present invention is Fig.15 Schematic diagram of step S280.

[0046] Fig. 20 FIG. 4 is a cross-sectional view of a semiconductor device packaging structure according to a fourth embodiment of the present invention.

[0047] Fig.21 A method for manufacturing a semiconductor device packaging structure according to another embodiment of the present invention is Fig.15 Schematic diagram of step S260.

[0048] Fig. 22 A method for manufacturing a semiconductor device packaging structure according to another embodiment of the present invention is Fig.15 Schematic diagram of step S270.

[0049] Fig.23 FIG. 5 is a cross-sectional view of a semiconductor device packaging structure according to a fifth embodiment of the present invention. DETAILED DESCRIPTION

[0050] The following is a specific example. To illustrate the implementation method of the "semiconductor element packaging structure and its manufacturing method" disclosed in the present invention, those skilled in the art can understand the advantages and effects of the present invention from the content disclosed in this specification. The present invention can be implemented or applied through other different specific embodiments, and the details in this specification can also be modified and changed in various ways based on different viewpoints and applications without departing from the concept of the present invention. In addition, the drawings of the present invention are only simple schematic illustrations and are not depicted according to actual dimensions. It is stated in advance. The following implementation methods will further explain the relevant technical content of the present invention in detail, but the disclosed content is not intended to limit the scope of protection of the present invention. In addition, the term "or" used in this article may include any one or more combinations of the associated listed items depending on the actual situation.

[0051] See also Figure 1 , which shows a flow chart of a method for manufacturing a semiconductor device packaging structure according to an embodiment of the present invention. The method for manufacturing a semiconductor device packaging structure according to an embodiment of the present invention can be used to package different types of chips, such as power chips or diode chips.

[0052] like Figure 1 As shown, in step S100, a wafer is provided, wherein the wafer defines a plurality of semiconductor elements and a plurality of mutually staggered cutting areas, wherein each semiconductor element includes at least one pad disposed on the active surface. Figure 2 and Figure 3 , Figure 2 is a schematic diagram of step S100 of the method for manufacturing a chip packaging component according to an embodiment of the present invention, Figure 3 for Figure 2 Schematic diagram of the local section along line III-III.

[0053] In the embodiment of the present invention, the wafer 1 has completed the device manufacturing process, and a plurality of semiconductor devices 10 and a plurality of mutually interlaced cutting areas 11 are defined on the upper surface 1a of the wafer 1. The material constituting the wafer 1 is usually silicon, but it can also be other semiconductor materials, such as gallium arsenide or gallium nitride.

[0054] In detail, the plurality of cutting regions 11 include a plurality of cutting regions 11 extending in different directions, and the plurality of cutting regions 11 are interlaced with each other. The plurality of semiconductor elements 10 are arranged in an array. Any two adjacent semiconductor elements 10 in the same column (i.e., arranged in the first direction D1) or any two adjacent semiconductor elements 10 in the same row (i.e., arranged in the second direction D2) are separated from each other by the cutting regions 11.

[0055] In addition, in this embodiment, the width w1 of the dicing region 11 (in the first direction D1 or the second direction D2 ) is approximately between 40 μm and 100 μm. In this embodiment, the dicing region 11 has a smaller width w1 , which allows the wafer 1 to have more semiconductor devices 10 .

[0056] like Figure 3 As shown, in the embodiment of the present invention, each semiconductor element 10 has an active surface 10a, a bottom surface 10b opposite to the active surface 10a, and a side surface 10c connected between the active surface 10a and the bottom surface 10b. In addition, each semiconductor element 10 has at least one pad 100 ( Figure 2 It is worth mentioning that the redistribution circuit structure of the semiconductor device 10 can be pre-formed at the wafer stage, that is, before the wafer is cut.

[0057] The redistribution circuit structure may include a patterned dielectric layer (not shown) and at least one pad 100. The patterned dielectric layer may cover the active surface 10a of the semiconductor element 10 and have at least one opening. At least one pad 100 is formed in the opening to be electrically connected to the end point of the semiconductor element 10.

[0058] In one embodiment, the material of the pad 100 is, for example, titanium, copper, silver, nickel, tin, gold or any combination thereof, but the present invention is not limited to the aforementioned examples. In addition, in one embodiment, the thickness of each pad 100 is about 5 μm to 100 μm. It should be noted that before the wafer is cut, the thickness of the wafer can be thinned to 100 μm to 250 μm. Therefore, the thickness of the semiconductor element 10 of the embodiment of the present invention is also about 100 μm to 250 μm.

[0059] In this embodiment, a portion of the plurality of semiconductor devices 10 is taken as an example to illustrate the method for manufacturing the semiconductor device packaging structure of the embodiment of the present invention. Figure 1 In step S110, a wafer is placed on a temporary adhesive layer, and the wafer is cut along a plurality of cutting regions to form a plurality of semiconductor elements separated from each other. In step S120, the spacing between the plurality of semiconductor elements is expanded.

[0060] Please refer to Figure 4, which is a method for manufacturing a semiconductor device packaging structure according to an embodiment of the present invention, in step S120. It should be noted that, in one embodiment, when the wafer 1 is placed on the temporary adhesive layer P11, the bottom surface of the wafer 1 is placed toward the temporary adhesive layer P11. Figure 4 As shown, the active surface 10 a of each semiconductor element 10 faces upward, and the bottom surface 10 b is adhered to the temporary adhesive layer P11 .

[0061] In addition, when the wafer 1 is cut, the entire cutting area 11 is not removed due to the limitation of the cutting width. Therefore, after cutting the wafer 1, the distance d1 between any two adjacent semiconductor elements 10 is substantially smaller than the width w1 of the cutting area 11. Further, the distance d1 between any two adjacent semiconductor elements 10 is approximately between 40 μm and 80 μm.

[0062] like Figure 4 As shown, after the wafer is cut into a plurality of separated semiconductor devices 10, the temporary adhesive layer P11 is applied in a horizontal direction (i.e., along the Figure 2 The tensile force is applied in the first direction D1 and the second direction D2 to expand the interval d1 between the plurality of semiconductor elements 10. In one embodiment, after the expansion, the interval d1' between any two semiconductor elements 10 is about 100 μm to 200 μm.

[0063] In another embodiment, before the wafer 1 is cut, the wafer 1 may be placed on the temporary adhesive layer P11 with the lower surface 1b facing upward. Figure 5 When the plurality of semiconductor elements 10 are disposed on the temporary adhesive layer P11, the active surface 10a is disposed toward the temporary adhesive layer P11. Then, an expansion step is performed to increase the distance d1 between two adjacent semiconductor elements 10.

[0064] Please refer to Figure 1 In step S130, all the expanded semiconductor components are placed on the carrier board. Figure 6 , which is a schematic diagram of the method for manufacturing a semiconductor device packaging structure according to an embodiment of the present invention in step S130. Figure 6 As shown, the active surface 10a of each semiconductor element 10 faces the carrier P1. It is worth noting that in the embodiment of the present invention, after the spacing d1' of the plurality of semiconductor elements 10 is expanded, no special step of selecting the semiconductor elements 10 is performed, but all the semiconductor elements 10 are transferred and disposed on the carrier P1.

[0065] Please refer to Figure 6, a plurality of semiconductor elements 10 are disposed on the carrier plate P1. In one embodiment, in this embodiment, the carrier plate P1 has a base plate P10 and another temporary adhesive layer P11, and the material of the base plate P10 is, for example, silicon wafer, glass, ceramic, polymer or metal, and the present invention is not limited thereto.

[0066] If, during expansion, multiple semiconductor components 10 are disposed on the temporary adhesive layer P11 with the active surface 10a facing upward, after the expansion is performed, a carrier plate P1 having another temporary adhesive layer P11 may be disposed facing the active surfaces 10a of the multiple semiconductor components 10 so that the active surfaces 10a of the multiple semiconductor components 10 are adhered to the temporary adhesive layer P11 of the carrier plate P1.

[0067] Afterwards, the temporary adhesive layer P11 originally adhered to the bottom surface 10b of the plurality of semiconductor elements 10 is debonded. The debonding method can be selected according to the material of the temporary adhesive layer P11, such as heating, irradiation with ultraviolet light or laser light, to remove the viscosity of the temporary adhesive layer P11. For example, if the temporary adhesive layer is a UV debonding layer, the adhesion of the temporary adhesive layer can be reduced by irradiation with ultraviolet light, but the present invention is not limited to this. Accordingly, when the plurality of semiconductor elements 10 are arranged on the carrier board P1, they are arranged with the active surface 10a facing the carrier board P1.

[0068] In another embodiment, when expansion is performed, Figure 5 As shown, the plurality of semiconductor elements 10 are disposed with the active surface 10a facing the temporary adhesive layer P11. After expansion, the temporary adhesive layer P11 together with the plurality of semiconductor elements 10 adhered thereto can be directly disposed on the base plate P10.

[0069] Please refer to Figure 1 In step S140, a molding material is formed to cover the plurality of semiconductor devices to form an initial package. Figure 7 , Figure 7 The schematic diagram of the manufacturing method of the semiconductor element packaging structure of the embodiment of the present invention in step S140. The molding material 2 is filled between the plurality of semiconductor elements 10 to connect the plurality of semiconductor elements 10. The molding material 2 and the plurality of semiconductor elements 10 together form an initial package body M1. The molding material 2 is, for example, a polymer material or a composite material, wherein the polymer material is, for example, polyimide (PI), benzocyclobutene (BCB), epoxy resin or silicone, and the composite material is, for example, glass fiber reinforced thermosetting plastic, bulk molding material and other insulating materials or dielectric materials with adhesion. The molding material 2 can be formed by compression molding or injection molding.

[0070] In this embodiment, the molding material 2 covers the bottom surface 10 b of each semiconductor element 10 , but does not cover the active surface 10 a of each semiconductor element 10 . In other words, the molding material 2 covers the side surface 10 c and the bottom surface 10 b of each semiconductor element 10 .

[0071] like Figure 7 As shown, the initial package M1 has a first side and a second side, and the active surface 10a and the bottom surface 10b of each semiconductor element 10 correspond to the first side and the second side respectively. Figure 5 As shown, the active surface 10a of each semiconductor element 10 corresponds to the first side of the initial package M1, and the initial package M1 contacts the temporary adhesive layer P11 of the carrier P1 with the first side. Further, the molding material 2 has a first surface 2a and a second surface 2b opposite to the first surface 2a. In this embodiment, the first surface 2a of the molding material 2 and the active surface 10a of the semiconductor element 10 will contact the temporary adhesive layer P11 of the carrier P1 together.

[0072] Please refer to Figure 1 In step S150, the initial package body and the carrier board are separated. In step S160, a cutting step is performed on the initial package body to form a plurality of semiconductor device package structures. Figure 8 , Figure 8 Schematic diagram of the method for manufacturing a semiconductor device packaging structure according to an embodiment of the present invention in step S160. Separate the initial package M1 from the carrier P1. In detail, when the temporary adhesive layer P11 is a UV debonding layer, the removable adhesive layer can be irradiated with ultraviolet light (UV light) to reduce the adhesion between the removable adhesive layer P11 and the initial package M1, so that the initial package M1 can be detached from the removable adhesive layer P11 of the carrier P1.

[0073] like Figure 8 As shown, after the carrier plate P1 is separated from the initial package body M1, a cutting step L1 is performed on the initial package body M1 to form a plurality of semiconductor device package structures m1. Fig. 9 , Fig. 9 FIG. 1 is a cross-sectional view of a semiconductor device packaging structure according to a first embodiment of the present invention. The semiconductor device packaging structure m1 of this embodiment includes a semiconductor device 10 and a molding layer 2A.

[0074] As mentioned above, the semiconductor element 10 has an active surface 10a, a bottom surface 10b opposite to the active surface 10a, and a side surface 10c connected between the active surface 10a and the bottom surface 10b. The semiconductor element 10 is, for example, a power chip or other types of chips, and the present invention is not limited thereto. The semiconductor element 10 also has at least one pad 100 located on the active surface 10a.

[0075] After the initial package M1 is cut, the molding material 2 surrounding each semiconductor element 10 is formed. Fig. 9 The encapsulation layer 2A is formed. Accordingly, the encapsulation layer 2A covers the side surface 10c and the bottom surface 10b of the semiconductor element 10, and can provide protection for the semiconductor element 10. In this embodiment, the thickness T1 of the encapsulation layer 2A is between 10 and 50 μm. In addition, the encapsulation layer 2A has two opposite first surfaces 2a and a second surface 2b. Figure 7 As shown, the active surface 10a of the semiconductor element 10 and the pad 100 are exposed on the first surface 2a of the encapsulation layer 2A. In this embodiment, the active surface 10a of the semiconductor element 10 is flush with the first surface 2a of the encapsulation layer 2A. In addition, the pad 100 has a thickness of about 5 μm to 100 μm and protrudes from the active surface 10a, so that the top surface of the pad 100 is higher than the first surface 2a of the encapsulation layer 2A.

[0076] Please refer to Fig.10 , showing a flow chart of a method for manufacturing a semiconductor package component according to another embodiment of the present invention. Figure 1 The same steps of the manufacturing method are not repeated. In this embodiment, after the initial package and the carrier are separated, step S170 is further performed. In step S170, a thinning step is performed on the second side of the initial package to expose each semiconductor element on the second side of the initial package.

[0077] Please refer to Fig.11 , a schematic diagram showing a semiconductor element packaging structure in step S170 according to another embodiment of the present invention. In detail, when the thinning step is performed on the initial package M1, the initial package M1 is thinned from the second surface 2b of the molding material 2 toward the first surface 2a to remove a portion of the molding material 2 and thin each semiconductor element 10. In this way, the semiconductor element 10 has a thinner thickness t2. In one embodiment, the thickness of the initial package M1 can be thinned to 25μm to 75μm. In other words, the thickness t2 of each semiconductor element 10 in the initial package M1 is also thinned to 25μm to 75μm. In addition, in the thinned initial package M1, the bottom surface 10b' of each semiconductor element 10 will be exposed to the second surface 2b' of the molding material 2', and will be flush with the second surface 2b' of the molding layer 2'.

[0078] It should be noted that, since the semiconductor element 10 is encapsulated in the molding material 2, when the initial package M1 is thinned, the molding material 2 can provide protection for the semiconductor element 10 to prevent the semiconductor element 10 from being damaged during the thinning process. In other words, the method provided by the embodiment of the present invention can not only make the thickness of the semiconductor element 10 thinner, but also reduce the breakage rate of the semiconductor element 10.

[0079] Please refer to Fig.12 After executing step S170, step S160 may be directly executed to form a plurality of semiconductor device packaging structures. Fig.11 and Fig.12 , in the right Fig.11 After the initial package M1 is cut into pieces in the step L1, the following Fig.12 The semiconductor device packaging structure m2 is shown.

[0080] In the semiconductor device packaging structure m2 of the present embodiment, the encapsulation layer 2B only covers the side surface 10c of the semiconductor device 10, and does not cover the active surface 10a and the bottom surface 10b' of the semiconductor device 10. In other words, the active surface 10a of the semiconductor device 10 will be exposed on the first surface 2a of the encapsulation layer 2B, and the first surface 2a of the encapsulation layer 2B will be flush with the active surface 10a of the semiconductor device 10. In addition, the bottom surface 10b' of the semiconductor device 10 will be exposed on the second surface 2b' of the encapsulation layer 2B.

[0081] It should be noted that, compared with the previous embodiment, the total thickness of the semiconductor device package structure m2 manufactured by the manufacturing method of the embodiment of the present invention can be thinner. Specifically, the total thickness of the semiconductor device package structure m2 can be between 25 μm and 75 μm.

[0082] Please refer to Fig.10 After executing step S170, the manufacturing method of this embodiment may further execute step S180. In step S180, a conductive and thermally conductive layer is formed on the second side of the initial package body, wherein the conductive and thermally conductive layer directly contacts the bottom surface of each semiconductor element.

[0083] Please refer to Fig.13 , which is a schematic diagram of step S170 of the method for manufacturing a semiconductor device packaging structure according to the third embodiment of the present invention. Fig.13 The step S170 is followed by forming a conductive and thermally conductive layer 3 on the second side of the initial package M1 after thinning the initial package M1. Specifically, the conductive and thermally conductive layer 3 is formed on the second surface 2b' of the molding material 2' and the bottom surface 10b' of each semiconductor element 10.

[0084] The material of the conductive and thermally conductive layer 3 is, for example, titanium, copper, silver, nickel, tin, gold or any combination thereof. In addition, each conductive and thermally conductive layer 3 may have a laminated structure, such as a laminated structure of titanium / copper, titanium / nickel / silver, titanium / copper / nickel / tin or titanium / copper / nickel / gold. The thickness of the conductive and thermally conductive layer 3 is about 1 μm to 5 μm. Fig.11 As shown, a cutting step L1 is performed on the initial package body M1 and the electrical and thermal conductive layer 3 .

[0085] Please refer to Fig.14 , Fig.14 FIG. 1 is a cross-sectional view of a semiconductor device packaging structure according to a third embodiment of the present invention. Fig.10 The semiconductor device packaging structure m2 of this embodiment further includes a conductive and thermally conductive layer 3, and the conductive and thermally conductive layer 3 is disposed on the bottom surface 10b' of the semiconductor device 10 and the second surface 2b' of the molding layer 2B. The conductive and thermally conductive layer 3 can provide protection for the semiconductor device 10 and can be used to dissipate heat from the semiconductor device 10.

[0086] It should be noted that in Fig.14 In the embodiment of the present invention, the conductive junction of the semiconductor element 10 is located at the active surface 10a of the semiconductor element 10. However, in other embodiments, the conductive junction of the semiconductor element 10 may also be located at the bottom surface 10b thereof. Accordingly, the number and position of the conductive junctions of the semiconductor element 10 are determined according to the type of the semiconductor element 10, and the present invention is not limited thereto. Accordingly, when the bottom of the semiconductor element 10 has a conductive junction for electrically connecting to the outside, the conductive and heat-conductive layer 3 can be used as a pad so that the semiconductor element 10 can be electrically connected to another electronic device or a circuit board.

[0087] In addition, in the semiconductor device package structure m3 of the present embodiment, the thickness of the semiconductor device 10 is between 25 and 75 μm, and the thickness of the conductive and thermal conductive layer 3 is about 1 μm to 5 μm, so the total thickness of the semiconductor device package structure m3 can be less than 100 μm. Figure 7 In the embodiment of the present invention, the total thickness of the semiconductor device package structures m2 and m3 can be thinner. Specifically, the total thickness of the semiconductor device package structures m2 and m3 can be between 25 μm and 100 μm.

[0088] In addition, it should be noted that the step of forming the molding material 2 can also be performed before the plurality of semiconductor devices 10 are disposed on the carrier board P1. Fig.15 , which is a flow chart of a method for manufacturing a semiconductor element packaging structure according to another embodiment of the present invention.

[0089] Steps S200 to S220 of this embodiment are respectively Fig.10Steps S100 to S120 are the same as those of the embodiment and are not described in detail here. In step S230, a molding material is formed to cover the plurality of semiconductor elements to form an initial package, and the plurality of semiconductor elements are all placed on the carrier board. Fig.16 as well as Fig.17 , which shows Fig.15 A schematic diagram of a method for manufacturing a semiconductor device packaging structure in step S230.

[0090] like Fig.16 As shown, in this embodiment, a plurality of semiconductor elements 10 are sandwiched between a first sheet molding material 21 and a second sheet molding material 22 , and a gap H1 is defined between the first sheet molding material 21 , the second sheet molding material 22 and any two semiconductor elements 10 .

[0091] Furthermore, after the wafer is cut into a plurality of separated semiconductor devices 10, the plurality of semiconductor devices 10 may be arranged in a manner such as Figure 4 or Figure 5 The first sheet-shaped molding material 21 is disposed on the temporary adhesive layer P11. Since the first sheet-shaped molding material 21 also has adhesiveness and can fix the plurality of semiconductor elements 10, after the first sheet-shaped molding material 21 is disposed, the temporary adhesive layer P11 can be removed first, and then the second sheet-shaped molding material 22 can be disposed, so that the plurality of semiconductor elements 10 are sandwiched between the first sheet-shaped molding material 21 and the second sheet-shaped molding material 22.

[0092] Please refer to Fig.16 The first sheet molding material 21 and the second sheet molding material 22 are pressed together from two opposite sides of the semiconductor element 10 to form a molding material 2 that fills the gap H1 and completely covers each semiconductor element 10. In this embodiment, the second sheet molding material 22, a plurality of semiconductor elements 10, and the first sheet molding material 21 are first placed on the carrier board P1 and then pressed together.

[0093] Please refer to Fig.17 Through the above steps, a plurality of semiconductor elements 10 are embedded in the molding material 2 to form an initial package M2. Fig.17 As shown, in this embodiment, the molding material 2 covers the bottom surface 10b and the active surface 10a of each semiconductor element 10. The initial package M2 has a first side and a second side, and the active surface 10a and the bottom surface 10b of each semiconductor element 10 located in the molding material 2 are respectively facing the first side and the second side. In this embodiment, the first surface 2a of the molding material 2 is located on the first side of the initial package M2, and the second surface 2b of the molding material 2 is located on the second side of the initial package M2.

[0094] Please refer to Fig.15In step S240, the initial package body and the carrier board are separated; in step S250, a thinning step is performed on the first side of the initial package body. Fig.18 In this embodiment, a thinning step is performed on the initial package M2 from the first side of the initial package M2 to expose the pads 100 of each semiconductor element 10. That is, a portion of the molding material 2 covering the pads 100 of the semiconductor element 10 will be removed. Fig.19 After the initial package M2 is thinned, the first surface 2a' of the molding material 2' is flush with the surface of the pad 100 of the semiconductor device 10. It should be noted that when the initial package M2 is thinned, a portion of the pad 100 may also be removed.

[0095] Please refer to Fig.15 In one embodiment, after executing step S250, step S280 may be directly executed. Fig.19 As shown, after the initial package body M2 is cut into pieces in the cutting step L1 , a plurality of semiconductor device package structures can be formed.

[0096] Please refer to Fig. 20 , is a cross-sectional schematic diagram of the semiconductor element packaging structure of the fourth embodiment of the present invention. The semiconductor element packaging structure m4 includes a semiconductor element 10 and a molding layer 2C. In the present embodiment, the molding layer 2C covers the active surface 10a, the side surface 10c and the bottom surface 10b of the semiconductor element 10, but exposes the pad 100 of the semiconductor element 10. In one embodiment, the thickness of the molding layer 2C is between 10 and 50 μm. Accordingly, in the semiconductor element packaging structure m4 of the present embodiment, all surfaces of the semiconductor element 10 (including the active surface 10a, the side surface 10c and the bottom surface 10b) are covered by the molding layer 2C and are more completely protected.

[0097] In addition, the encapsulation layer 2C has two opposite first surfaces 2a' and a second surface 2b. A height difference h1 is formed between the first surface 2a' and the active surface 10a of the semiconductor element 10, and the height difference h1 is between 10 μm and 80 μm. Fig.18 As shown, the first surface 2 a ′ is aligned with the surface of the pad 100 .

[0098] Please refer to Fig.15 After executing step S250, the manufacturing method of the embodiment of the present invention may further execute steps S260 and S270, and then execute step S280. Specifically, in step S260, a thinning step is performed on the second side of the initial package so that each semiconductor element is exposed on the second side of the initial package. In step S270, a conductive and thermally conductive layer is formed on the second side of the initial package, wherein the conductive and thermally conductive layer covers and contacts the bottom surface of each semiconductor element.

[0099] Please refer to Fig.21 , which shows a schematic diagram of the method for manufacturing a semiconductor device packaging structure according to an embodiment of the present invention in step S260. It should be noted that, Fig.21 The step may be followed by step S250 (see Fig.18 ). That is to say, after the initial package M2 is thinned from the first side thereof, another thinning step is performed on the initial package M2 from the second side thereof to expose the bottom surface 10b' of each semiconductor element 10. Accordingly, in the present embodiment, the initial package M2 undergoes two-stage thinning steps. In the thinned initial package M2, the bottom surface 10b' of each semiconductor element 10 will be exposed to the second surface 2b' of the molding material 2", and will be flush with the second surface 2b' of the molding layer 2".

[0100] Please refer to Fig. 22 , Fig. 22 Schematic diagram of a method for manufacturing a semiconductor device package structure according to another embodiment of the present invention in step S270. After thinning the initial package M2, a conductive and thermally conductive layer 3 is formed on the second side of the initial package M1. Further, the conductive and thermally conductive layer 3 is formed on the second surface 2b' of the molding material 2' and the bottom surface 10b' of each semiconductor device 10.

[0101] The material of the conductive and thermally conductive layer 3 is, for example, titanium, copper, silver, nickel, tin, gold or any combination thereof. In addition, each conductive and thermally conductive layer 3 may have a laminated structure, such as a laminated structure of titanium / copper, titanium / nickel / silver, titanium / copper / nickel / tin or titanium / copper / nickel / gold. The thickness of the conductive and thermally conductive layer 3 is about 1 μm to 5 μm. Fig. 20 As shown, a cutting step L1 is performed on the initial package body M1 and the electrical and thermal conductive layer 3 .

[0102] Please refer to Fig.23 , Fig.23 It is a cross-sectional schematic diagram of the semiconductor element packaging structure of the fifth embodiment of the present invention. The semiconductor element packaging structure m5 of this embodiment includes a semiconductor element 10, a molding layer 2″ and a conductive and thermally conductive layer 3. The molding layer 2D of this embodiment covers the active surface 10a and the side surface 10c of the semiconductor element 10, but does not cover the bottom surface 10b' of the semiconductor element 10. The molding layer 2D has a first surface 2a' and a second surface 2b'. The first surface 2a' of the molding layer 2D will form a height difference h1 with the active surface 10a of the semiconductor element 10, but the first surface 2a' will be flush with the surface of the pad 100.

[0103] In addition, the second surface 2b' of the encapsulation layer 2D is flush with the bottom surface 10b' of the semiconductor element 10. The conductive and thermally conductive layer 3 is disposed on the second surface 2b' of the encapsulation layer 2D and the bottom surface 10b' of the semiconductor element 10. Further, in the present embodiment, the conductive and thermally conductive layer 3 is in direct contact with the bottom surface 10b' of the semiconductor element 10 and the second surface 2b' of the encapsulation layer 2D. The conductive and thermally conductive layer 3 can provide protection for the semiconductor element 10 and can be used to dissipate heat from the semiconductor element 10. When the bottom of the semiconductor element 10 has a conductive junction for electrically connecting to the outside, the conductive and thermally conductive layer 3 can be used as a soldering pad so that the semiconductor element 10 can be electrically connected to another electronic device or a circuit board.

[0104] In addition, in the semiconductor device package structure m3 of the present embodiment, the thickness of the semiconductor device 10 is between 25 and 75 μm, and the thickness of the conductive and thermal conductive layer 3 is about 1 μm to 5 μm, so the total thickness of the semiconductor device package structure m3 can be less than 100 μm.

[0105] It should be noted that in another embodiment of the manufacturing method, step S270 may also be omitted. Fig.15 The semiconductor device package structure formed by the above manufacturing method does not have the conductive and thermal conductive layer 3, and the mold layer covers the active surface 10a and the side surface 10c of the semiconductor device 10, but exposes the bottom surface 10b' of the semiconductor device 10.

[0106] [Beneficial Effects of Embodiments]

[0107] One of the beneficial effects of the present invention is that the semiconductor element packaging structure and the manufacturing method thereof provided by the present invention can further reduce the width w1 of the cutting area 11, increase the number of semiconductor elements 10 in the wafer 1, and thus reduce the manufacturing cost through the technical solutions of "setting the wafer on a temporary adhesive layer and cutting the wafer along multiple cutting areas to form multiple semiconductor elements separated from each other", "expanding the spacing between the multiple semiconductor elements", "setting all the expanded multiple semiconductor elements on a carrier board" and "forming a molding material to cover the multiple semiconductor elements to form an initial packaging body".

[0108] Furthermore, in the manufacturing method of the embodiment of the present invention, after cutting the wafer 1, the spacing between the plurality of semiconductor elements 10 can be expanded first, and then all the semiconductor elements 10 can be set on the carrier plate P1 for molding. In this way, the width w1 of the cutting area 11 will not be limited by the subsequent molding process and the width of the cutting tool, but can be further reduced. In this way, the area of ​​the wafer 1 that can be used to make the semiconductor element 10 can be increased, and the number of semiconductor elements 10 in the same wafer 1 can be increased, thereby reducing the manufacturing cost.

[0109] In addition, the manufacturing method provided by the embodiment of the present invention can form semiconductor element packaging structures m1-m5 without substrate, lead frame, and wire bonding, and the molding material 2 (2', 2") can also provide protection for the semiconductor element 10, thereby improving the yield of the semiconductor element packaging structures m1-m5.

[0110] On the other hand, the present embodiment does not reduce the volume by thinning the wafer at the wafer stage, but directly thins the initial package M1 (M2) after the wafer is cut into a plurality of semiconductor elements 10 and a molding material 2 (2', 2") is formed to cover the semiconductor elements 10. Accordingly, the thickness t1 of the semiconductor element 10 in the semiconductor element packaging structure m1~m5 can be determined in the step of thinning the initial package M1 (M2) instead of in the step of thinning the wafer. Compared with the existing technical means of controlling the thickness by thinning the entire wafer, thinning the initial package M1 (M2) can more accurately control the thickness t1, t2 of the semiconductor element 10 or the total thickness of the semiconductor element packaging structure m1~m5. In addition, the technical means adopted in the embodiment of the present invention are less likely to cause damage to the semiconductor element 10, which can reduce the difficulty and cost of the thinning process.

[0111] In addition, the semiconductor element 10 can be further thinned to less than 100 μm by using the manufacturing method of the semiconductor element packaging structure provided by the embodiment of the present invention, so that the size of the semiconductor element packaging structure m1~m5 can be further reduced. In general, compared with the existing packaging technology, the semiconductor element packaging structure m1~m5 manufactured by the manufacturing method of the embodiment of the present invention does not have a packaging substrate, a lead frame and wire bonding, so the total thickness of the semiconductor element packaging structure m1~m5 can be thinner and have a smaller volume. In other words, the volume of the semiconductor element packaging structure m1~m5 is very close to the size of the unpackaged chip.

[0112] The contents disclosed above are only preferred feasible embodiments of the present invention, and are not intended to limit the protection scope of the claims of the present invention. Therefore, all equivalent technical changes made using the contents of the present invention description and drawings are included in the protection scope of the claims of the present invention.

Claims

1. A method for manufacturing a semiconductor element packaging structure, characterized in that: The manufacturing method of the semiconductor element packaging structure comprises: A wafer is provided, wherein the wafer defines a plurality of semiconductor elements and a plurality of mutually staggered dicing regions, wherein each of the semiconductor elements includes at least one pad disposed on an active surface; Placing the wafer on a temporary adhesive layer, and cutting the wafer along a plurality of cutting regions to form a plurality of semiconductor elements separated from each other; Expanding the spacing between the plurality of semiconductor elements; Placing all of the expanded semiconductor elements on a carrier board; Forming a molding material to cover the plurality of semiconductor elements to form an initial package, wherein the molding material is filled between the plurality of semiconductor elements to connect the plurality of semiconductor elements, the initial package having a first side and a second side, the active surface and a bottom surface of each of the semiconductor elements corresponding to the first side and the second side respectively; separating the initial package body from the carrier board; and Performing a cutting step on the initial package body to form a plurality of semiconductor device package structures; Wherein, in the step of forming the initial package, all of the plurality of semiconductor elements are disposed on the carrier board, and the step of forming the initial package includes: The plurality of semiconductor elements are sandwiched between a first sheet-shaped molding material and a second sheet-shaped molding material, wherein a gap is defined between the first sheet-shaped molding material, the second sheet-shaped molding material and any two of the semiconductor elements; and The first sheet molding material, the plurality of semiconductor elements and the second sheet molding material are arranged on the carrier board, and the first sheet molding material and the second sheet molding material are pressed together to form a molding material that fills the gap and completely covers each semiconductor element.

2. The method for manufacturing a semiconductor device packaging structure according to claim 1, characterized in that: The width of the cutting area is 40 μm to 80 μm. After the expanded plurality of semiconductor elements are disposed on the carrier board, the distance between any two semiconductor elements is 100 μm to 200 μm.

3. The method for manufacturing a semiconductor device packaging structure according to claim 1, wherein: After forming the initial package, the molding material covers the active surface and the bottom surface of each semiconductor element, so that each semiconductor element is completely buried in the molding material, and the manufacturing method further includes: performing a thinning step from the first side of the initial package to expose at least one pad of each semiconductor element.

4. The method for manufacturing a semiconductor device packaging structure according to claim 3, characterized in that: After performing the thinning step on the first side of the initial package, a first surface of the molding material is flush with at least one pad surface of each of the semiconductor devices.

5. The method for manufacturing a semiconductor device packaging structure according to claim 4, characterized in that: Before performing the cutting step, the method further comprises: performing another thinning step from the second side of the initial package to expose the bottom surface of each of the semiconductor elements; and A conductive and thermally conductive layer is formed on the second side of the initial package, wherein the conductive and thermally conductive layer covers and contacts the bottom surface of each of the semiconductor elements.

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