A low power consumption dimming circuit and power supply method thereof

Abstract

The present invention discloses a low-power dimming circuit and a power supply method thereof, which includes a startup circuit, a power supply circuit, a power control chip, a dimming input optical coupler, and a second NMOS tube; the present invention adopts an active trigger chip overvoltage and undervoltage protection function to reduce the loss of the MOS tube in the output circuit and the loss of the chip. The startup circuit adds a MOS tube to prevent the chip from directly taking power from the bus voltage after startup, which causes loss on the voltage divider resistor.

Description

Technical Field

[0001] The invention relates to the technical field of switching power supplies, and in particular to a low-power dimming circuit and a power supply method thereof. Background Art

[0002] In the 21st century, with the rapid increase in the number of intelligent lighting devices, more and more manufacturers have joined the research and development of intelligent LED driver power supplies. At present, most intelligent LED drivers have the functions of wired (such as 0-10V, DALI, etc.) dimming mode and wireless intelligent dimming mode (such as wifi, zigbeed, etc.). Mainly, when the dimming signal turns off the LED, the LED driver will enter the light load working state or the standby state, and wait for the PWM dimming signal to adjust the duty cycle of the switch tube again to adjust the output power.

[0003] When the power supply is lightly loaded or in standby mode, the LED driver loss mainly includes three aspects: the loss of the transformer, the loss of the switch tube, and the loss of the chip's own circuit. This is also a common phenomenon in the existing intelligent LED drivers on the market. This is because the current LED driver power supply is mostly powered by connecting several large-resistance resistors to the DC bus voltage and then to the power supply end of the control module. However, when the DC bus voltage is full voltage input, the startup speed of the LED driver power supply will be affected. If it is under the same input voltage, the startup speed can be increased by reducing the resistance of the resistor connected to the DC bus voltage. When the resistance of the resistor decreases, the power consumption of the resistor will increase, which will affect the standby power consumption.

[0004] Therefore, how to reduce the power consumption of the chip startup resistor, and when the intelligent dimming PWM is adjusted to the lowest, the duty cycle fed back from the secondary end is the lowest, the chip output power is the lowest, but the output is not turned off, and there is still no-load voltage, so there is still loss of the secondary freewheeling diode, loss of the primary switch tube, and loss of the transformer, which will cause huge unnecessary losses. In order to solve the standby power consumption, technicians in this field thought of adjusting a secondary transformer to couple a voltage feedback to the primary to power the chip, so as to reduce the standby power consumption of the bus drive circuit. However, this method increases the complexity of the drive circuit, and changing the secondary transformer will also lead to electromagnetic compatibility, loss and other problems, making circuit development more difficult.

[0005] In summary, designing a low-power dimming circuit and a power supply method thereof to control the loss of the driving power supply at low load or no load has become a technical problem that needs to be urgently solved by technicians in the relevant technical field. Summary of the invention

[0006] The object of the present invention is to provide a low power consumption dimming circuit and a power supply method thereof to solve the problems raised in the above background technology.

[0007] To achieve the above object, the present invention provides the following technical solutions:

[0008] A low-power dimming circuit comprises a startup circuit, a power supply circuit, a power control chip, a dimming input optocoupler, and a second NMOS tube. The startup circuit and the power supply circuit are respectively connected to the power supply pin of the power control chip and the positive electrode of the dimming input optocoupler, the positive electrode of the dimming input optocoupler is connected to the PWM pin of the power control chip, the drain of the second NMOS is connected to the input end of the power supply circuit, the gate of the second NMOS is connected to the GATE pin of the power control chip, and the source of the second NMOS is connected to the CS sampling pin of the power control chip U1.

[0009] As a further technical solution of the present invention: the startup circuit includes a first resistor R1, a first diode D1, a third resistor R3, a fourth resistor R4, a second voltage regulator tube Z2 and a first NMOS tube Q1.

[0010] As a further technical solution of the present invention: the power supply circuit includes a second diode D2, a first filter inductor L1, a first filter capacitor C1, a second filter capacitor C2, a second energy storage inductor L2 and a linear regulator.

[0011] As a further technical solution of the present invention: the linear regulator includes a second resistor R2, a second transistor Q3, a third transistor Q4, a first voltage regulator Z1, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7 and a fifth transistor Q5.

[0012] As a further technical solution of the present invention: the base of the fifth transistor Q5 is connected to the PWM pin of the power control chip U1.

[0013] As a further technical solution of the present invention: the circuit connected to the FB pin of the power control chip U1 includes a sixth resistor R6, a seventh resistor R7 and a fourth transistor Q4.

[0014] As a further technical solution of the present invention: the base of the fourth transistor Q4 is connected to the PWM pin of the power control chip U1.

[0015] A power supply method with an auxiliary optocoupler circuit is characterized in that the above-mentioned circuit is adopted, including an overvoltage protection method for entering a low-power power supply method and an undervoltage protection method for entering a low-power power supply method. The overvoltage protection method for entering a low-power power supply method is specifically: a fourth transistor Q4 and a sixth resistor R6 and a seventh resistor R7 are connected in parallel to the FB pin of the power control chip U1 to form a resistance-dividing circuit, the transistor receives a PWM signal synchronized with the power control chip, when the PWM signal received by the power control chip changes from full load to light load, the voltage detected by the FB pin continues to decrease, and when the PWM signal is at a 100% duty cycle, the voltage of the FB pin triggers the overvoltage protection threshold of the chip, the chip shuts off the output, and waits for the dimming signal to change again to achieve overvoltage protection reset.

[0016] As a further technical solution of the present invention: the method for entering low power consumption power supply under undervoltage protection is specifically: the power supply circuit and the power control chip U1 output adopt synchronous PWM signals, when the PWM signal received by the power control chip changes from full load to light load, the power supply circuit also synchronously receives the PWM signal so that the voltage of the power control chip U1 gradually decreases; when the duty cycle of the PWM signal is 100%, the voltage of the power supply circuit decreases to 0.1~0.8V below the undervoltage start threshold of the power control chip U1 and triggers the undervoltage protection function of the power control chip, resulting in the shutdown of part of the circuit inside the power control chip U1 to achieve low power consumption and shut down the secondary output; at this time, the voltage of the power supply pin of the power control chip just triggers the conduction voltage drop threshold of the first NMOS tube Q1, at this time, the startup circuit supplies power to the power control chip U1 and the third energy storage capacitor C3, the power control chip releases the undervoltage protection function and enters normal operation, and when the voltage of the third energy storage capacitor C3 gradually drops to the undervoltage start threshold of the power control chip U1, the power control chip U1 enters undervoltage protection.

[0017] Compared with the prior art, the present invention has the following beneficial effects:

[0018] 1. In the QR flyback LED driver, the switch tube loss caused by the chip's excessively high frequency at light load can be avoided. In the current continuous conduction mode or intermittent conduction mode, this method can also reduce the light load loss and no-load loss of the switch at light load.

[0019] 2. Use active trigger chip overvoltage and undervoltage protection functions to reduce the loss of MOS tubes in the output circuit and the loss of chips.

[0020] 3. Add MOS tubes to the startup circuit to prevent the chip from taking power directly from the bus voltage after startup, which will cause losses in the voltage divider resistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1This is a schematic diagram of a low-power dimming circuit of a switching power supply according to Embodiment 1 of the present invention;

[0022] Figure 2 This is a schematic diagram of a low-power dimming circuit of a switching power supply according to Embodiment 2 of the present invention. DETAILED DESCRIPTION

[0023] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0024] See also Figure 1 , Example 1: A low-power dimming circuit, which includes a startup circuit, a power supply circuit, a power control chip U1, a dimming input optocoupler, a second NMOS tube Q2;

[0025] The startup circuit and the power supply circuit are respectively connected to the power supply pin of the power control chip U1 and the positive electrode of the dimming input optocoupler U2B, the positive electrode of the dimming input optocoupler is connected to the PWM pin of the power control chip U1, the drain of the second NMOS is connected to the input end of the power supply circuit, the gate of the second NMOS is connected to the GATE pin of the power control chip U1, and the source of the second NMOS is connected to the CS sampling pin of the power control chip U1.

[0026] The startup circuit includes a first resistor R1, a first diode D1, a third resistor R3, a fourth resistor R4, a second voltage regulator tube Z2, and a first NMOS tube Q1;

[0027] The power supply circuit includes a second diode D2, a first filter inductor L1, a first filter capacitor C1, a second filter capacitor C2, a second energy storage inductor L2, and a linear regulator;

[0028] The power control chip U1 includes a third input bypass capacitor C3 and a fourth filter capacitor C4;

[0029] The dimming input optocoupler U2B includes a tenth pull-up resistor R10.

[0030] Please refer to Figure 1 ,

[0031] In the startup circuit, one end of the first resistor R1 is connected to one end of the circuit bus voltage, and the other end is connected to the positive electrode of the first diode D1, the negative electrode of the first diode D1 is connected to the drain of the first NMOS tube Q1, one end of the third resistor R3 is connected to the bus voltage line, and the other end is connected to one end of the fourth resistor R4, the other end of the fourth resistor R4 is connected to the gate of the first NMOS tube Q1 and the negative electrode of the second voltage regulator tube Z2, and the positive electrode of the second voltage regulator tube Z2 is grounded.

[0032] In the power supply circuit:

[0033] The positive pole of the second diode D2 is connected to one end of the primary coil of the transformer, and the negative pole is connected to one end of the first filter inductor L1 and one end of the first filter capacitor C1. The other end of the first filter capacitor C1 is grounded, and the other end of the first filter inductor is connected to one end of the positive pole of the second filter capacitor C2 and one end of the second energy storage inductor L2. The negative pole of the second filter capacitor is grounded, and the other end of the energy storage inductor L2 is connected to a linear regulator.

[0034] In the above description, the first resistor R1 applies voltage to the drain of the first NMOS transistor Q1, and the third resistor R3, the fourth resistor R4 and the voltage stabilizing diode Z2 are used to apply a conduction voltage to the first NMOS transistor. After the power control chip U1 is started, the output end of the power supply circuit pulls up the source voltage of the first NMOS transistor Q1, causing the first NMOS transistor Q1 to be turned off, thereby achieving the loss on the startup resistor.

[0035] In the power control chip U1:

[0036] One end of the tenth resistor R10 is connected to the VCC pin of the power control chip U1, and the other end is connected to the PWM pin of the power control chip U1 and the positive electrode of the dimming input optocoupler U2B. One end of the output of the input optocoupler U2B is grounded.

[0037] In the second NMOS tube Q2:

[0038] The drain of the second NMOS tube Q2 is connected to one end of the primary coil of the transformer, the gate is connected to the GATE pin of the power control chip U1, the source is connected to one end of the eighth resistor R8, the other end of the eighth resistor R8 is connected to one end of the ninth resistor R9, one end of the fourth filter capacitor C4 and the CS pin of the power control chip U1, the other end of the ninth resistor R9 is grounded, and the other end of the fourth filter capacitor is grounded.

[0039] In the above description, the present invention does not use the primary auxiliary winding to power the chip, but uses the leakage inductance on the transformer to discharge energy to the primary side during the demagnetization process of the transformer. First, a π-type filter composed of a first filter capacitor C, a first filter inductor L1, and a second filter capacitor C2 is used to prevent the leakage inductance on the transformer and the spikes generated by the parasitic capacitance Cd on the second NMOS tube. The second energy storage inductor stores the voltage on the leakage inductance, and the voltage is stabilized within the operating voltage range of the power control chip U1 through a linear regulator.

[0040] The low power consumption power supply method of the first embodiment of the present invention: the above-mentioned linear regulator includes a second resistor R2, a second transistor Q3, a third transistor Q4, a first voltage regulator Z1, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7 and a fifth transistor.

[0041] In the above description, the working principle of a low-power power supply method is as follows: the three-terminal regulator main components Q3, R2, and Z1 of the linear regulator are the main voltage output circuit, and R5, R6, R7, and Q5 are composed and used to adjust the output voltage of the linear regulator, and its minimum output voltage is the undervoltage threshold of the power control chip U1 -0.8V.

[0042] The working steps are as follows: the power supply circuit and the power control chip U1 output adopt synchronous PWM signals, and when the PWM signal received by the power control chip changes from full load to light load, the power supply circuit also synchronously receives the PWM signal so that the voltage of the power control chip gradually decreases; when the duty cycle of the PWM signal is 100%, the voltage of the power supply circuit decreases to 0.1~0.8V below the undervoltage start threshold of the power control chip and triggers the undervoltage protection function of the power control chip, causing part of the circuit inside the chip to be shut down to achieve low power consumption and shut down the secondary output; at this time, the voltage of the power supply pin of the power control chip just triggers the conduction voltage drop threshold of the first NMOS tube, and at this time, the startup circuit supplies power to the power control chip and the third energy storage capacitor, the power control chip releases the undervoltage protection function and enters normal operation, and when the voltage of the third energy storage capacitor gradually drops to the undervoltage start threshold of the power control chip, the power control chip enters undervoltage protection.

[0043] Embodiment 2:

[0044] The difference from the first embodiment is that the fifth resistor R5, the sixth resistor R6, the seventh resistor R7, and the fifth transistor Q5 in the linear regulator are removed, and the sixth resistor R6, the seventh resistor R7 and the fourth transistor Q4 are added to the FB pin of the power control chip U1. The working principle is that when the fourth transistor Q4 is in a fully turned-on state, the voltage-dividing resistance is the lowest, so that the voltage detected by the FB pin of the power control chip U1 is the lowest, causing the power control chip U1 to enter overvoltage protection and shut down the output. Specifically: a resistance-dividing circuit consisting of a fourth transistor Q4, a sixth resistor R6 and a seventh resistor R7 is connected in parallel to the FB pin of the power control chip, and the transistor receives a PWM signal synchronized with the power control chip. When the PWM signal received by the power control chip changes from full load to light load, the voltage detected by the FB pin continues to decrease, and when the PWM signal is at a 100% duty cycle, the voltage of the FB pin triggers the overvoltage protection threshold of the chip, the chip shuts off the output, and waits for the dimming signal to change again to reset the overvoltage protection.

[0045] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

[0046] In addition, it should be understood that although the present specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

Claims

1. A power supply method for overvoltage protection and undervoltage protection of a low-power dimming circuit. It is characterized in that It includes a startup circuit, a power supply circuit, a power control chip U1, a dimming input optocoupler U2B, and a second NMOS tube Q2. The startup circuit and the power supply circuit are respectively connected to the VCC pin of the power control chip U1 and the positive electrode of the dimming input optocoupler U2B. The positive electrode of the dimming input optocoupler U2B is connected to the PWM pin of the power control chip U1. The drain of the second NMOS tube Q2 is connected to the power supply circuit, the gate of the second NMOS is connected to the GATE pin of the power control chip, the source of the second NMOS tube Q2 is connected to the CS sampling pin of the power control chip U1, and the circuit connected to the FB pin of the power control chip U1 includes a sixth resistor R6, a seventh resistor R7 and a fourth transistor Q4. The overvoltage protection enters the low-power power supply method: a resistance-dividing circuit composed of a fourth transistor Q4, a sixth resistor R6, and a seventh resistor R7 is connected in parallel to the FB pin of the power control chip U1, and the transistor receives a PWM signal synchronized with the power control chip. When the PWM signal received by the power control chip changes from full load to light load, the voltage detected by the FB pin keeps decreasing, and when the PWM signal is at a 100% duty cycle, the voltage of the FB pin triggers the overvoltage protection threshold of the chip, the chip shuts off the output, and waits for the dimming signal to change again to reset the overvoltage protection; The undervoltage protection enters the low-power power supply method: the power supply circuit and the power control chip U1 output adopt a synchronous PWM signal, when the PWM signal received by the power control chip changes from full load to light load, the power supply circuit also synchronously receives the PWM signal so that the voltage of the power control chip U1 gradually decreases; when the duty cycle of the PWM signal is 100%, the voltage of the power supply circuit decreases to 0.1~0.8V below the undervoltage start threshold of the power control chip U1 and triggers the undervoltage protection function of the power control chip, causing part of the circuit inside the power control chip U1 to be turned off to achieve low power consumption and turn off the secondary output; at this time, the voltage of the power supply pin of the power control chip just triggers the conduction voltage drop threshold of the first NMOS tube Q1, and at this time, the startup circuit supplies power to the power control chip U1 and the third energy storage capacitor C3, the power control chip releases the undervoltage protection function and enters normal operation, and when the voltage of the third energy storage capacitor C3 gradually drops to the undervoltage start threshold of the power control chip U1, the power control chip U1 enters undervoltage protection.

2. A power supply method for overvoltage protection and undervoltage protection of a low-power dimming circuit according to claim 1, It is characterized in that The startup circuit includes a first resistor R1, a first diode D1, a third resistor R3, a fourth resistor R4, a second voltage regulator tube Z2, and a first NMOS tube Q1.

3. A power supply method for overvoltage protection and undervoltage protection of a low-power dimming circuit according to claim 1, It is characterized in that The power supply circuit includes a second diode D2, a first filter inductor L1, a first filter capacitor C1, a second filter capacitor C2, a second energy storage inductor L2, and a linear regulator.

4. A power supply method for overvoltage protection and undervoltage protection of a low-power dimming circuit according to claim 3, It is characterized in that The linear regulator includes a second resistor R2, a second transistor Q3, a fourth transistor Q4, a first voltage regulator tube Z1, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7 and a fifth transistor Q5.

5. A power supply method for overvoltage protection and undervoltage protection of a low-power dimming circuit according to claim 4, It is characterized in that The base of the fifth transistor Q5 is connected to the PWM pin of the power control chip U1.

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