WAT electrical test layout

Abstract

The present invention provides a WAT ​​electrical test pattern, including an active area pattern; a plurality of contact hole patterns respectively located at both ends of the active area pattern and equidistantly distributed; pad patterns respectively located at both ends of the active area pattern and connected to the contact hole patterns; a plurality of groups of equally spaced gate patterns located between the contact hole patterns at both ends of the active area pattern; wherein each group of gate patterns includes at least one group of first and second gate patterns with staggered distribution, one end of the first and second gate patterns respectively exceeds the active area pattern, and the other end of the first and second gate patterns respectively lies within the range of the active area pattern. The test pattern of the present invention measures the resistance between the pads, and if a smaller normal metal silicide resistance is obtained, it proves that the entire serpentine active area has no silicide process interruption, that is, no thin film merging has occurred, and if the resistance is larger or even has an open circuit, it means that thin film merging may have occurred between the gates, and the process needs to be improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a WAT ​​electrical testing layout. Background Art

[0002] With the development of the times, chips have become a "necessity" in global life. With the advancement of chip technology, people's lives are becoming more and more intelligent, various travel is becoming more and more convenient, and the amount of information available every day is also increasing.

[0003] Today, as the requirements for integrated circuit design and manufacturing become increasingly higher, the characteristic dimensions of MOS tubes are becoming smaller and smaller, and many processes are even constantly pushing the limits of the technology.

[0004] One of the important steps to reduce the feature size is to reduce the line width of the polysilicon gate (metal gate), and then the spacing between the gates also becomes smaller, so as to achieve the goal of reducing the overall size of the device.

[0005] As the distance between gates decreases, merging may occur during thin film deposition after the gates are formed, which may block subsequent ion injection and silicide formation. Summary of the invention

[0006] In view of the above-mentioned shortcomings of the prior art, the object of the present invention is to provide a WAT ​​electrical test layout for solving the problem in the prior art that due to the reduction of the gate spacing, merging may occur during the thin film deposition after the gate is formed, which will block the subsequent ion injection and the formation of silicide.

[0007] To achieve the above objectives and other related objectives, the present invention provides a WAT ​​electrical test layout, including:

[0008] Active area graphics;

[0009] A plurality of contact hole patterns respectively located at two ends of the active area pattern and distributed equidistantly;

[0010] pad patterns respectively located at two ends of the active area pattern and connected to the contact hole pattern;

[0011] A plurality of groups of equally spaced gate patterns located between the contact hole patterns at both ends of the active area pattern; a plurality of groups of equally spaced gate patterns located between the pad patterns and located in the active area; wherein,

[0012] Each group of the gate patterns includes at least one group of first and second gate patterns that are staggered, one end of the first and second gate patterns respectively exceeds the active area pattern, and the other end of the first and second gate patterns respectively lies within the active area pattern.

[0013] Preferably, the distance between the first and second gate patterns meets the minimum design rule in layout design.

[0014] Preferably, from one end to the other end of the active area pattern, the critical dimensions of the widths of the first and second gate patterns in each group of the gate patterns increase sequentially.

[0015] Preferably, the critical dimensions of the first and second gate patterns in each group of the gate patterns are equal.

[0016] Preferably, the number of groups of the gate patterns is three.

[0017] Preferably, each group of the gate patterns includes two groups of the first and second gate patterns.

[0018] Preferably, the graphic in the layout design is a rectangle.

[0019] Preferably, the layout is used for detecting the completeness of silicide formation.

[0020] As described above, the WAT electrical test layout of the present invention has the following beneficial effects:

[0021] The present invention provides a test layout. During the test, the resistance between the pads is measured. If a smaller normal metal silicide resistance is obtained, it proves that the silicide process has not been interrupted in the entire serpentine active area, that is, no thin film merging has occurred. If the resistance is larger or even an open circuit occurs, it means that thin film merging may have occurred between the gates and the process needs to be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 Shown is a schematic diagram of the WAT electrical test layout of the present invention;

[0023] Figure 2 It is a schematic diagram of the serpentine active region of the present invention. DETAILED DESCRIPTION

[0024] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0025] See also Figure 1 The present invention provides a WAT ​​electrical test layout, including:

[0026] Active area graphics;

[0027] A plurality of contact hole patterns 20 respectively located at two ends of the active region pattern 10 and distributed equidistantly;

[0028] pad patterns 30 respectively located at two ends of the active area pattern 10 and connected to the contact hole pattern 20;

[0029] That is, the connected contact hole pattern 20 and pad pattern 30 are the two ends of the WAT electrical test pattern. In a semiconductor device made according to the pattern, the resistance between the two pads can be measured to obtain the resistance of the device between the two pads.

[0030] In an optional implementation, the two pad patterns 30 are respectively located on two sides outside the active region pattern 10. According to this arrangement, the pads at both ends are far away from the gate and are not easily merged.

[0031] A plurality of groups of gate patterns 40 are located between the pad pattern 30 and the contact hole pattern 20 connected thereto and on the active area pattern 10 and are distributed equidistantly in sequence; wherein,

[0032] Each group of gate patterns 40 includes at least one group of first and second gate patterns (401, 402) that are staggered, one end of the first and second gate patterns (401, 402) respectively exceeds the active area pattern 10, the other end of the first and second gate patterns (401, 402) are respectively located within the range of the active area pattern 10, and the distance between the first and second gate patterns (401, 402) is equal to the distance between the gate patterns 40.

[0033] In an optional implementation, the distance between the first and second gate patterns (401, 402) meets the minimum design rule in the layout design, that is, the semiconductor device subsequently obtained according to the layout meets the minimum design rule size of the manufacturing process.

[0034] In an optional embodiment, from one end to the other end of the active region pattern 10 , the critical dimensions of the widths of the first and second gate patterns ( 401 , 402 ) in each group of gate patterns 40 increase sequentially.

[0035] In an optional implementation, the critical dimensions of the first and second gate patterns (401, 402) in each group of gate patterns 40 are equal, that is, the sizes and shapes of the first and second gate patterns (401, 402) are equal.

[0036] In an optional implementation, the number of groups of gate patterns 40 is three.

[0037] In an optional implementation, each group of gate patterns 40 includes two groups of first and second gate patterns ( 401 , 402 ).

[0038] In an optional implementation, the shape of the graphic in the layout design is a rectangle.

[0039] In an alternative embodiment, see Figure 2 , forming an active area pattern 10 structure that is serpentine from left to right. When testing a semiconductor device made according to the pattern structure, the resistance between the pads is measured. If a smaller normal metal silicide resistance is obtained, it proves that the silicide process has not been interrupted in the entire serpentine active area, that is, no film merging has occurred. If the resistance is larger or even open circuit occurs, it means that film merging may have occurred between the gates, which is convenient for detecting the resistance between the pads.

[0040] In an optional embodiment, the layout is used to detect the completeness of silicide formation.

[0041] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner. Therefore, the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0042] In summary, the present invention provides a test layout. During the test, the resistance between the pads is measured. If a smaller normal metal silicide resistance is obtained, it proves that the silicide process has not been interrupted in the entire serpentine active area, that is, no film merging has occurred. If the resistance is larger or even an open circuit occurs, it means that film merging may have occurred between the gates, and the process needs to be improved. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0043] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A WAT electrical test layout, characterized in that: include: Active area graphics; A plurality of contact hole patterns respectively located at two ends of the active area pattern and distributed equidistantly; pad patterns respectively located at two ends of the active area pattern and connected to the contact hole pattern; A plurality of groups of equally spaced gate patterns located between the contact hole patterns at both ends of the active area pattern; wherein, Each group of the gate patterns includes at least one group of first and second gate patterns that are staggered, wherein one end of the first and second gate patterns respectively exceeds the active area pattern, and the other ends of the first and second gate patterns respectively lie within the active area pattern; From one end to the other end of the active region pattern, the critical dimensions of the widths of the first and second gate patterns in each group of the gate patterns increase sequentially.

2. The WAT electrical test layout according to claim 1, characterized in that: The distance between the first and second gate patterns meets the minimum design rule in layout design.

3. The WAT electrical test layout according to claim 1, characterized in that: The critical dimensions of the first and second gate patterns in each group of the gate patterns are equal.

4. The WAT electrical test layout according to claim 1, characterized in that: The number of groups of the gate patterns is three.

5. The WAT electrical test layout according to claim 1, characterized in that: Each group of the gate patterns includes two groups of the first and second gate patterns.

6. The WAT electrical test layout according to any one of claims 1 to 5, characterized in that: The shape of the graphics in the layout design is a rectangle.

7. The WAT electrical test layout according to claim 1, characterized in that: The layout is used to detect the completeness of silicide formation.

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