A synchronous rectification driving circuit with low transmission delay

Abstract

The present invention discloses a synchronous rectification driving circuit with low transmission delay, which mainly includes a falling edge detection circuit, a pull-up current control circuit, a comparator CP1, an inverter N1, a single pulse trigger circuit 1, a single pulse trigger circuit 2, an RS trigger RS1, a pull-up tube Q1 and a pull-down tube Q2. The present invention uses falling edge detection to establish a pull-up current in advance and realize a clear pull-down latch operation. After detecting that the drain-source voltage of the synchronous rectifier meets the opening condition, the pull-up output can be immediately pulled up to realize the opening, which can significantly reduce the transmission delay; at the same time, the pull-up current is controlled by the falling edge of the drain-source voltage of the synchronous rectifier, and naturally reaches zero before shutting down, without the need for additional prohibition of the pull-up current operation, which can reduce the shutdown delay; in addition, the present invention uses the gate capacitance of the synchronous rectifier to maintain the high level after conduction, which can reduce the power consumption of the driving circuit.

Description

Technical Field

[0001] The invention belongs to the technical field of power electronic conversion, and in particular to a synchronous rectification drive circuit with low transmission delay. Background Art

[0002] Buck, Boost, flyback, forward and other converters are widely used in various power conversion occasions due to their simple circuit structure, mature control technology, small size and low cost. As the power and current requirements of load electrical equipment continue to increase, the loss caused by the conduction voltage drop of the rectifier diode in the converter has gradually become the main limiting factor for improving the converter efficiency.

[0003] By adopting synchronous rectification technology and using the MOSFET channel instead of the rectifier diode to conduct, the conduction loss of the rectifier tube can be effectively reduced and the converter efficiency can be improved. Figure 1 A flyback converter with synchronous rectification control on the secondary side is given. The converter is mainly composed of the primary main switch tube S P , power transformer T1 (its magnetizing inductance is L m ), the secondary synchronous rectifier tube S R and output filter capacitor C o Composition, V in is the converter input voltage, V o is the output voltage, i SR is the current flowing into the synchronous rectifier S R Source current.

[0004] The synchronous rectification drive circuit generally detects the synchronous rectification tube S R The voltage difference between the drain and source is v DSR , determine the zero voltage turn-on and zero current turn-off to generate S R The driving control signal v GSR , when v DSR Lower than the turn-on threshold voltage V th_on When S R , when v DSR Higher than the turn-off threshold voltage V th_off When S is turned off R In actual use, the synchronous rectification drive circuit turns on and off S R There is a certain transmission delay in the process, that is, when v is detected DSR Lower than V th_on Or detect v DSR Higher than V th_off After a certain period of time, v GSR Output high level or low level, thereby controlling S R These delays are mainly determined by the implementation logic of the synchronous rectification drive circuit and the execution time of the internal component circuits. Figure 2 The logic flow chart of the opening and closing process of the conventional synchronous rectification drive circuit is given. During the opening process, the synchronous rectification drive circuit detects v DSR Is it lower than V th_on (Step S101), after the opening conditions are met (v DSR <V th_on ), clear the pull-down latch in sequence (step S102, used to prevent the synchronous rectifier drive circuit pull-up and pull-down tubes from being turned on at the same time and causing internal short circuit damage), establish the pull-up current (step S103), pull-up output (step S104), and finally output a high level to control the synchronous rectifier tube S R During the shutdown process, the synchronous rectification drive circuit detects v DSR Is it higher than V th_off (Step S201), after the shutdown condition is met (v DSR >V th_off ), successively prohibit the pull-up current (step S202, before the turn-off moment of the pull-up tube, which can reduce the loss of the driving circuit), clear the pull-up latch (step S203, used to avoid the pull-up and pull-down tubes of the synchronous rectification driving circuit being turned on at the same time and causing internal short circuit damage), pull-down output (step S204), and finally output a low level to control S R Shut down.

[0005] From the above analysis, it can be seen that the total turn-on or turn-off delay of the synchronous rectification drive circuit is obtained by adding up the execution time of multiple logic steps to realize the circuit. When the turn-on or turn-off delay is too large, it will significantly affect the performance of the converter. Figure 1 Taking the flyback converter with secondary-side synchronous rectification control as an example, its operating waveform at the key point when the turn-on or turn-off delay is too large is as follows Figure 3 When the opening delay is too long, such as Figure 3 As shown in (a), the synchronous rectifier tube S R It is turned on at the peak moment of the magnetizing inductor current, and the turn-on delay S R The body diode of S is turned on, because the body diode conduction voltage drop is much greater than S R The channel conduction voltage drop will increase the converter loss and reduce efficiency; when the turn-off delay is too large, such as Figure 3 As shown in (b), S R When actually shutting down, the current flowing into its source is negative, and the zero current shutdown characteristic is lost. At the same time, the negative current will introduce circulating current, thereby increasing the current stress and increasing the converter loss. When designing a synchronous rectification drive circuit, high-speed devices can be used to shorten the execution time of each logic step to realize the circuit, thereby shortening the total turn-on or turn-off delay, but this will increase the overall power consumption and cost of the circuit. Summary of the invention

[0006] The purpose of the present invention is to provide a synchronous rectification driving circuit with low transmission delay in view of the problems existing in the prior art.

[0007] The technical solution to achieve the purpose of the present invention is: a synchronous rectification driving circuit with low transmission delay, the circuit comprising a falling edge detection circuit, a pull-up current control circuit, a comparator CP1, an inverter N1, a single pulse trigger circuit 1, a single pulse trigger circuit 2, an RS trigger RS1, a pull-up tube Q1 and a pull-down tube Q2;

[0008] Synchronous rectifier S R Turn-on process: The falling edge detection circuit detects the synchronous rectifier S R The voltage difference between the drain and source is v DSR The falling edge generates the pull-up current control signal v IU_setc The pull-up current control circuit uses the signal v IU_setc Establish pull-up current i PU , while the signal v IU_setc The rising edge enables the single pulse trigger circuit 1 to output a high level pulse, control the RS trigger RS1 to reset, turn off the pull-down tube Q2, and realize the clear pull-down latch; the comparator CP1 detects S R The voltage difference between the drain and source is v DSR Whether the conditions for opening are met, if the conditions for opening are met, that is, v DSR <V th_on After that, the comparator CP1 outputs a high level and turns on the pull-up tube Q1 to achieve the pull-up output. Then the pull-up current i PU For S R The gate capacitance is charged and the driving control signal v GSR Establish a high level and turn on the synchronous rectifier S R ;

[0009] Synchronous rectifier S R Shutdown process: Comparator CP1 detects S R The voltage difference between the drain and source is v DSR Whether the shutdown condition is met, the shutdown condition is met, that is, v DSR >V th_off After that, comparator CP1 outputs low level and turns off the pull-up tube Q1 to clear the pull-up latch; at the same time, inverter N1 outputs high level, and its output changes from low to high. The rising edge enables the single pulse trigger circuit 2 to output a high level pulse, controls the RS trigger RS1 to set, turns on the pull-down tube Q2, and realizes the pull-down output. After that, the pull-down tube Q2 is connected to S R The gate capacitance is discharged, driving the control signal v GSR Establish a low level and turn off the synchronous rectifier S R .

[0010] Furthermore, the falling edge detection circuit and the pull-up current control circuit include: a capacitor C1, a resistor R1, a resistor R2 and a transistor Q3, the capacitor C1 and the resistor R2 are connected in series and connected to the base of the transistor Q3, and the common end of the capacitor C1 and the resistor R2 is connected to the power supply voltage V of the synchronous rectification drive circuit through the resistor R1. CC , the emitter of transistor Q3 is connected to the supply voltage V CC , the voltage across resistor R1 is the pull-up current control signal v IU_setc , the current flowing out of the collector of transistor Q3 is the pull-up current i PU .

[0011] Compared with the prior art, the present invention has the following significant advantages: (1) the pull-up current is established in advance by using falling edge detection and the pull-down latch operation is cleared. After detecting that the drain-source voltage of the synchronous rectifier tube meets the turn-on condition, the pull-up output can be immediately pulled up to achieve turn-on, which can significantly reduce the transmission delay; (2) the pull-up current is controlled by the falling edge of the drain-source voltage of the synchronous rectifier tube, and naturally reaches zero before shutting down. There is no need for additional prohibition of the pull-up current operation, which can reduce the shut-down delay; (3) the high level after conduction is maintained by the gate capacitance of the synchronous rectifier tube, which can reduce the power consumption of the driving circuit.

[0012] The present invention is further described in detail below in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 Schematic diagram of a flyback converter with secondary-side synchronous rectification control.

[0014] Figure 2 1 is a logic flow chart of the turn-on and turn-off process of a conventional synchronous rectification drive circuit, wherein Figure (a) is a logic flow chart of the turn-on process, and Figure (b) is a logic flow chart of the turn-off process.

[0015] Figure 3 Figure 1 is a waveform diagram of the impact of excessive delay on converter performance, where Figure (a) is a waveform diagram of the impact of excessive turn-on delay on converter performance, and Figure (b) is a waveform diagram of the impact of excessive turn-off delay on converter performance.

[0016] Figure 4 This is a block diagram of the synchronous rectification drive circuit system of the present invention.

[0017] Figure 5 The figure (a) is a logic flow chart of the opening and closing process of the synchronous rectification driving circuit of the present invention, wherein the figure (b) is a logic flow chart of the opening process, and the figure (a) is a logic flow chart of the closing process.

[0018] Figure 6 The following is a circuit diagram of a specific embodiment of the falling edge detection circuit and the pull-up current control circuit of the present invention.

[0019] Figure 7 This is a working waveform diagram of key points of the synchronous rectification drive circuit of the present invention.

[0020] Figure 8 The following are simulation waveform diagrams for the specific implementation of the present invention, wherein Figure (a) is a simulation waveform diagram for the turn-on delay, and Figure (b) is a simulation waveform diagram for the turn-off delay. DETAILED DESCRIPTION

[0021] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0022] The present invention proposes a synchronous rectification driving circuit with low transmission delay, the system block diagram is as follows Figure 4 As shown, it mainly includes a falling edge detection circuit, a pull-up current control circuit, a comparator CP1, an inverter N1, a single pulse trigger circuit 1, a single pulse trigger circuit 2, an RS trigger RS1, a pull-up tube Q1 and a pull-down tube Q2. D and v S They are synchronous rectifier tube S R The drain and source voltages, and v DSR =v D -v S , v IU_setc is the pull-up current control signal output by the falling edge detection circuit, i PU is the pull-up current output by the pull-up current control circuit, v IU_outc is the output voltage of comparator CP1 and also the pull-up current output enable control signal, v GSR It is the driving control signal output by the synchronous rectification driving circuit.

[0023] Combination Figure 5 The logic flow chart of the opening and closing process of the synchronous rectification driving circuit shown in FIG. 1 briefly describes the working principle of the synchronous rectification driving circuit of the present invention: during the opening process, the falling edge detection circuit detects the synchronous rectification tube S R The voltage difference between the drain and source is v DSR The falling edge of (step S301) generates a pull-up current control signal v IU_setc The pull-up current control circuit establishes the pull-up current i according to the signal PU (Step S302), while signal v IU_setc The rising edge enables the single pulse trigger circuit 1 to output a high level pulse, controls the RS trigger RS1 to reset, turns off the pull-down tube Q2, and realizes clearing the pull-down latch (step S303); the comparator CP1 detects S R The voltage difference between the drain and source is v DSRWhether the opening conditions are met (step S304), the opening conditions are met, that is, v DSR <V th_on After that, the comparator CP1 outputs a high level and turns on the pull-up tube Q1 to achieve the pull-up output (step S305). PU For S R The gate capacitance is charged and the driving control signal v GSR Establish a high level and turn on the synchronous rectifier S R According to the above analysis, Figure 2 Compared with the conventional scheme shown in (a), the synchronous rectification driving circuit of the present invention establishes a pull-up current and clears the pull-down latch by detecting the falling edge during the opening process. DSR After the turn-on conditions are met, only the pull-up output step needs to be executed, thus significantly reducing the transmission delay caused by too many logic steps and accumulated execution time.

[0024] During the shutdown process, comparator CP1 detects S R The voltage difference between the drain and source is v DSR Whether the shutdown condition is met (step S401), the shutdown condition is met, that is, v DSR >V th_off After that, the comparator CP1 outputs a low level and turns off the pull-up tube Q1 to clear the pull-up latch (step S402); at the same time, the inverter N1 outputs a high level, and the rising edge of its output changing from low to high enables the single pulse trigger circuit 2 to output a high level pulse, controls the RS trigger RS1 to be set, turns on the pull-down tube Q2, and realizes the pull-down output (step S403). After that, the pull-down tube Q2 is connected to S R The gate capacitance is discharged, driving the control signal v GSR Establish a low level and turn off the synchronous rectifier S R Since the pull-up current in the synchronous rectification driving circuit is controlled by S R The voltage difference between the drain and source is v DSR The falling edge of S R Before shutdown, the current naturally decreases to zero, and there is no need to perform additional pull-up current prohibition operations. This also optimizes the shutdown process logic flow and can reduce transmission delays.

[0025] Figure 6 A specific implementation circuit of the falling edge detection circuit and the pull-up current control circuit in the synchronous rectification drive circuit of the present invention is given, which is composed of a capacitor C1, a resistor R1, a resistor R2 and a transistor Q3. CC is the supply voltage of the synchronous rectification drive circuit, and the voltage across the resistor R1 is the pull-up current control signal v IU_setC , the current flowing out of the collector of transistor Q3 is the pull-up current i PU .

[0026] by Figure 1 The flyback converter shown in FIG. 1 is an application object, and the key working waveforms of the synchronous rectification circuit of the present invention are as follows: Figure 7 As shown in the figure, Lm is the current flowing through the magnetizing inductance L m The current, v R_RS1 and v S_RS1 are the voltages at the R input and S input of the RS trigger RS1, respectively. GQ2 It is the Q output voltage of the RS trigger RS1 and is also the driving control signal of the pull-down tube Q2.

[0027] Combined with the working principle of the flyback converter, the working principle of the synchronous rectification driving circuit of the present invention is described as follows: In the input energy storage stage, the primary main switch tube S P On, input voltage V in Applied to the primary side of power transformer T1, the magnetizing inductor current i Lm Linear increase, slope is V in / L m , secondary synchronous rectifier tube S R The voltage difference between the drain and source is v DSR =V in / n+V o , where n is the ratio of the number of primary turns to the number of secondary turns of the power transformer T1, then v DSR >V th_off , comparator CP1 outputs a low level, the pull-up tube Q1 is turned off; the primary main switch tube S P After shutdown, the input energy storage phase ends and the magnetizing inductor current i Lm For S R The drain-source junction capacitance is discharged, S R The voltage difference between the two ends is V in / n+V o Starts to drop rapidly, because the voltage across capacitor C1 will not change suddenly, such as Figure 7 As shown, the voltage at the junction of resistors R1 and R2 will be relative to V CC A fast falling edge is generated, that is, the voltage v across the resistor R1 IU_setc A fast rising edge will be generated, and the voltage signal v IU_setc Control the pull-up current i PU Generates a fast rising edge and has

[0028]

[0029] In the formula, β Q3 is the current amplification factor of transistor Q3, v eb_onis the emitter-base voltage drop of Q3. It should be particularly noted that in practical applications, the transistor Q3 can be composed of a multi-stage current amplifier circuit, such as a multi-stage cascaded Darlington transistor, to improve the total current amplification factor.

[0030] At the same time, the voltage signal v IU_setc The rising edge of enables the single pulse trigger circuit 1 to output a high level pulse, the RS trigger RS1 is reset and outputs a low level, the pull-down tube Q2 is turned off, and the pull-down latch is cleared.

[0031] When S R The voltage difference between the drain and source is v DSR drops below V th_on When the comparator CP1 outputs a high level, the pull-up tube Q1 is turned on, and the pull-up current i PU For S R The gate capacitance is charged and the driving control signal v GSR Establish a high level and turn on S R During this process, capacitor C1 discharges through resistor R1, and the voltage across resistor R1 is v IU_setC Gradually decreases to zero, the pull-up current i PU Also gradually decreases to zero, but due to S R The gate capacitance acts as a driving control signal v GSR It can maintain a high level, making S R Keep the on state.

[0032] Synchronous rectifier S R After being turned on, the converter enters the energy transfer stage, and the magnetizing inductor L m Transfer energy to the load, exciting the inductor current i Lm Linear decrease, slope is -n·V o / L m , at this time S R The voltage difference between the drain and source is v DSR =-i SR × ds_on , where r ds_on For S R The channel on-resistance is SR =n·i Lm , then as the magnetizing inductor current i Lm The decrease of S R The voltage difference between the drain and source is v DSR Increases, when it increases to greater than V th_off When the comparator CP1 outputs a low level, the pull-up tube Q1 is turned off, and the pull-up latch is cleared. PUAt the same time, the inverter N1 outputs a high level, and its rising edge from low to high enables the single pulse trigger circuit 2 to output a high level pulse, controls the RS trigger RS1 to be set, outputs a high level, turns on the pull-down tube Q2, and R The gate capacitance is discharged, driving the control signal v GSR Establish a low level and turn off the synchronous rectifier S R . Then the voltage v DSR Rising, the comparator CP1 output maintains a low level, the pull-down tube Q2 remains on, and the driving control signal v GSR Maintain low level, synchronous rectifier S R Keep it off.

[0033] In order to further verify the effectiveness of the synchronous rectification driving circuit described in the present invention, Figure 8 The simulation results of a specific embodiment are given, and it can be seen that the turn-on delay of the synchronous rectification drive circuit is about 3.4ns, and the turn-off delay is about 4.1ns, both of which are very small. It can be seen that the present invention achieves delay reduction by optimizing the turn-on / turn-off logic, which can reduce the body diode conduction time and avoid excessive negative current.

[0034] The above shows and describes the basic principles, main features and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited by the above embodiments, and the above embodiments and descriptions are only for explaining the principles of the present invention. Without departing from the spirit and scope of the present invention, any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A synchronous rectification driving circuit with low transmission delay, characterized in that: The circuit includes a falling edge detection circuit, a pull-up current control circuit, a comparator CP1, an inverter N1, a single pulse trigger circuit 1, a single pulse trigger circuit 2, an RS trigger RS1, a pull-up tube Q1 and a pull-down tube Q2; Synchronous rectifier S R The drain-source voltage v D 、v S The falling edge detection circuit is input to the negative input terminal and the positive input terminal of the comparator CP1 respectively. The falling edge detection circuit is used to detect the synchronous rectifier tube S R The voltage difference between the drain and source is v DSR The output of the comparator CP1 acts on the pull-up tube Q1, and is connected to the S end of the RS trigger RS1 through the inverter N1 and the single pulse trigger circuit 2. The output of the falling edge detection circuit is used as the input of the pull-up current control circuit, and is connected to the R end of the RS trigger RS1 through the single pulse trigger circuit 1. The Q end of the RS trigger RS1 acts on the pull-down tube Q2. The output of the pull-up current control circuit is connected to the pull-up tube Q1, and the common end of the pull-up tube Q1 and the pull-down tube Q2 outputs the synchronous rectifier tube drive signal v GSR .

2. The low transmission delay synchronous rectification driving circuit according to claim 1, characterized in that: The driving circuit realizes the synchronous rectifier S R Turn-on process: The falling edge detection circuit detects the synchronous rectifier S R The voltage difference between the drain and source is v DSR The falling edge generates the pull-up current control signal v IU_setc The pull-up current control circuit uses the signal v IU_setc Establish pull-up current i PU , while the signal v IU_setc The rising edge enables the single pulse trigger circuit 1 to output a high level pulse, control the RS trigger RS1 to reset, turn off the pull-down tube Q2, and realize the clear pull-down latch; the comparator CP1 detects S R The voltage difference between the drain and source is v DSR Whether the conditions for opening are met, if the conditions for opening are met, that is, v DSR <V th_on After that, the comparator CP1 outputs a high level and turns on the pull-up tube Q1 to achieve the pull-up output. Then the pull-up current i PU For S R The gate capacitance is charged and the driving control signal v GSR Establish a high level and turn on the synchronous rectifier S R .

3. The low transmission delay synchronous rectification driving circuit according to claim 1, characterized in that: The driving circuit realizes the synchronous rectifier S R Shutdown process: Comparator CP1 detects S R The voltage difference between the drain and source is v DSR Whether the shutdown condition is met, the shutdown condition is met, that is, v DSR >V th_off After that, comparator CP1 outputs low level and turns off the pull-up tube Q1 to clear the pull-up latch; at the same time, inverter N1 outputs high level, and its output changes from low to high. The rising edge enables the single pulse trigger circuit 2 to output a high level pulse, controls the RS trigger RS1 to set, turns on the pull-down tube Q2, and realizes the pull-down output. After that, the pull-down tube Q2 is connected to S R The gate capacitance is discharged, driving the control signal v GSR Establish a low level and turn off the synchronous rectifier S R .

4. The low transmission delay synchronous rectification driving circuit according to claim 1, characterized in that: The falling edge detection circuit and the pull-up current control circuit include: a capacitor C1, a resistor R1, a resistor R2 and a transistor Q3. The capacitor C1 and the resistor R2 are connected in series and connected to the base of the transistor Q3. The common end of the capacitor C1 and the resistor R2 is connected to the power supply voltage V of the synchronous rectification drive circuit through the resistor R1. CC , the emitter of transistor Q3 is connected to the supply voltage V CC , the voltage across resistor R1 is the pull-up current control signal v IU_setc , the current flowing out of the collector of transistor Q3 is the pull-up current i PU .

5. The synchronous rectification driving circuit with low transmission delay according to claim 4, characterized in that: The pull-up current i PU for: In the formula, β Q3 is the current amplification factor of transistor Q3, v be_on is the emitter-base voltage drop of Q3.

6. The low transmission delay synchronous rectification driving circuit according to claim 4, characterized in that: The transistor Q3 can be replaced by a multi-stage current amplifier circuit.

Images