Electronic device and method for manufacturing the same

Abstract

The electronic device includes a pair of depletion gates, an accumulation gate, and a conductive resonator. The depletion gates are spaced apart from each other. The accumulation gate is located above the depletion gate. The conductive resonator is located above the depletion gate and the accumulation gate. The conductive resonator includes a first portion, a second portion, and a third portion. The first portion and the second portion are located on opposite sides of the accumulation gate. The third portion interconnects the first portion and the second portion of the conductive resonator and spans the depletion gate. The bottom surface of the first portion of the conductive resonator is lower than the bottom surface of the accumulation gate. Embodiments of the present application also relate to a method for manufacturing an electronic device.

Description

Technical Field

[0001] Embodiments of the present application relate to electronic devices and methods for manufacturing the same. Background Art

[0002] Quantum computing refers to a field of study related to computing systems that use quantum mechanical phenomena to manipulate data. Several milestones have been achieved in the blueprint for building a scalable silicon-based quantum computer. Quantum computing may involve initializing the states of N quantum bits (qubits), creating controllable entanglement between them, allowing these states to evolve, and reading out the states of the qubits after the evolution. A qubit can be a system with two degenerate (i.e., equal energy) quantum states, with a non-zero probability of being found in either state. Thus, the N qubits can define an initial state that is 2 N A combination of classic states. Summary of the invention

[0003] Some embodiments of the present application provide an electronic device, comprising: a pair of depletion gates spaced apart from each other; an accumulation gate located above the depletion gates; and a conductive resonator located above the depletion gates and the accumulation gates, wherein the conductive resonator comprises: a first portion and a second portion located on opposite sides of the accumulation gates; and a third portion interconnecting the first portion and the second portion of the conductive resonator and spanning the depletion gates, wherein a bottom surface of the first portion of the conductive resonator is lower than a bottom surface of the accumulation gates.

[0004] Other embodiments of the present application provide an electronic device, comprising: a pair of depletion gates spaced apart from each other; an accumulation gate, the accumulation gate comprising: a first portion and a second portion located on opposite sides of the depletion gate; and a third portion interconnecting the first portion and the second portion of the accumulation gate and spanning the depletion gate; and a conductive resonator, the conductive resonator comprising: a first portion and a second portion located on opposite sides of the depletion gate, wherein the first portion of the accumulation gate is located between the first portion of the conductive resonator and the depletion gate; and a third portion interconnecting the first portion and the second portion of the conductive resonator.

[0005] Still other embodiments of the present application provide a method for manufacturing an electronic device, comprising: forming a pair of depletion gates above a substrate; depositing a first gate dielectric layer above the substrate to cover the pair of depletion gates; forming an accumulation gate above the first gate dielectric layer; depositing an isolation layer above the accumulation gate; forming an opening in the isolation layer and extending into the first gate dielectric layer; and forming a conductive resonator partially located in the opening of the isolation layer, so that a bottom surface of the conductive resonator is lower than a top surface of the depletion gate. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Aspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the dimensions of the various components may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1A is a perspective view of an electronic device according to some embodiments of the present invention.

[0008] Figure 1B According to some embodiments of the present invention Figure 1A An enlarged stereogram of area P in FIG.

[0009] Figure 2A It is along Figure 1B A cross-sectional view taken along line AA in FIG.

[0010] Figure 2B It is along Figure 1B A cross-sectional view taken along line BB in FIG.

[0011] Figure 3 is a schematic diagram of an electronic device during operation according to some embodiments of the present invention.

[0012] Figure 4 is a perspective view of an electronic device according to some embodiments of the present invention.

[0013] Figure 5A and Figure 5B is a top view of a conductive resonator according to some embodiments of the present invention.

[0014] FIG. 6A to FIG. 19B Illustrated are top and cross-sectional views of intermediate stages in the formation of electronic devices according to some embodiments of the present invention.

[0015] Fig. 20A and Fig. 20B The simulation results of the magnetic field and the ratio of the total magnetic field to the electric field of the electronic device at different positions are illustrated.

[0016] Fig.21The simulation and measurement results of the return loss of electronic devices with different thicknesses of the conductive resonator are shown.

[0017] Fig.22A and Fig. 22B Shown are simulation and measurement results of return loss for electronic devices with different numbers of qubits and different thicknesses of the conductive resonator.

[0018] Fig.23A and Fig. 23B The diagram shows different thicknesses and widths of the conductive resonator (e.g., Figure 2A The measurement results of the return loss of the electronic device with a width W5 in the figure. DETAILED DESCRIPTION

[0019] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0020] Furthermore, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0021] As used herein, "around", "about", "approximately" or "substantially" generally refers to within 20%, or within 10%, or within 5% of a given value or range. The values ​​given here are approximate, that is, if not explicitly stated, the terms "around", "about", "approximately" or "substantially" can be inferred.

[0022] Embodiments of the present invention provide electronic devices having a resonator adjacent to the sidewall of an accumulation gate of the electronic device to implement a qubit with high efficiency. The qubit is configured to control and read out the electron or hole spin of a single dopant in a (semiconductor) substrate. In some embodiments, the transistor used in the qubit can be implemented on a device selected from the group consisting of a planar device, a multi-gate device, a fin field effect transistor (FinFET), a nanosheet gate FET, and a full-ring gate FET.

[0023] Figure 1A is a perspective view of an electronic device 100 according to some embodiments of the present invention, Figure 1B According to some embodiments of the present invention Figure 1A An enlarged stereogram of the area P in FIG. Figure 2A It is along Figure 1B A cross-sectional view taken along line AA in FIG. Figure 2B It is along Figure 1B In addition to the electronic device 100, Figure 1B The X-axis direction, the Y-axis direction, and the Z-axis direction are also depicted. Figure 1A and Figure 1B The dielectric layer used to isolate the conductive elements of the electronic device 100 is omitted, and Figure 2A and Figure 2B The dielectric layer is shown in FIG. 1 . The electronic device 100 includes a substrate 110, a depletion gate 120, an accumulation gate 130, and a conductive resonator 140. The electronic device 100 also includes an active region 116, a source region 112, and a drain region 114 in the substrate 110. The active region 116 is not Figure 1A and Figure 1B is shown in Figure 2A and Figure 2B Shown in.

[0024] refer to Figure 1A and Figure 1B . The depletion gates 120 are above the substrate 110 and are spaced apart from each other. That is, the source region 112 and the drain region 114 in the substrate 110 are below the depletion gates 120. The depletion gates 120 define a tunnel barrier 118 in the substrate 110. The (minimum) distance D1 between the depletion gates 120 may be in the range of about 5 nm to about 50 nm. If the distance D1 is less than about 5 nm, quantum dots may not be formed in the active region 116 of the electronic device 100 and between the depletion gates 120. If the distance D1 is greater than about 50 nm, multiple charges (quantum dots) may be formed in the active region 116 and between the depletion gates 120.

[0025] The accumulation gate 130 is above the depletion gate 120 and is spaced apart from the depletion gate 120. That is, the depletion gate 120 is isolated from the accumulation gate 130. The accumulation gate 130 includes a first portion 132, a second portion 134, and a third portion 136 interconnecting the first portion 132 and the second portion 134. The first portion 132 and the second portion 134 are located on opposite sides of the depletion gate 120. The first portion 132 is spaced apart from the second portion 134 by a distance D2, and the third portion 136 is located between the first portion 132 and the second portion 134. In some embodiments, the first portion 132, the second portion 134, and the third portion 136 are integrally formed. That is, there is no interface between the first portion 132 and the third portion 136 and between the second portion 134 and the third portion 136. The first portion 132 and the second portion 134 do not overlap with the depletion gate 120, and the third portion 136 spans the depletion gate 120.

[0026] The conductive resonator 140 is located above the depletion gate 120 and the accumulation gate 130, and includes a first portion 142, a second portion 144, and a third portion 146 interconnecting the first portion 142 and the second portion 144. In some embodiments, the first portion 142, the second portion 144, and the third portion 146 of the conductive resonator 140 are formed as follows: Figure 1BThe conductive resonator 140 is formed into a U-shape as shown. The first portion 142 and the second portion 144 of the conductive resonator 140 are located on opposite sides of the accumulation gate 130 and on opposite sides of the depletion gate 120. The first portion 132 of the accumulation gate 130 is located between the depletion gate 120 and the first portion 142 of the conductive resonator 140, and the second portion 134 of the accumulation gate 130 is located between the depletion gate 120 and the second portion 144 of the conductive resonator 140. That is, the first portion 142 and the second portion 144 of the conductive resonator 140 do not overlap the depletion gate 120 and the accumulation gate 130. In some embodiments, the first portion 132 of the accumulation gate 130 is closer to the first portion 142 of the conductive resonator 140 relative to the depletion gate 120, and / or the second portion 134 of the accumulation gate 130 is closer to the second portion 144 of the conductive resonator 140 relative to the depletion gate 120. In addition, the third portion 146 of the conductive resonator 140 spans the first portion 132 and the second portion 134 of the depletion gate 120 and the accumulation gate 130, but is offset (or deviated) from the third portion 136 of the accumulation gate 130 by a distance D3. That is, the third portion 146 of the conductive resonator 140 does not overlap (or is spaced apart) from the third portion 136 of the accumulation gate 130. In some embodiments, the distance D3 between the third portion 146 and the third portion 136 is greater than the width W1 of the third portion 136 and less than the length L1 of the first portion 142 (or the second portion 144). In addition, the third portion 146 of the conductive resonator 140 is located between the source region 112 (or the drain region 114) and the second portion 144 (or the first portion 142) of the conductive resonator 140.

[0027] In some embodiments, the depletion gate 120, the first and second portions 132 and 134 of the accumulation gate 130, and the first and second portions 142 and 144 of the conductive resonator 140 extend in a first direction (e.g., the Y direction), and the third portion 132 of the accumulation gate 130 and the third portion 142 of the conductive resonator 140 extend in a second direction (e.g., the X direction) substantially perpendicular to the first direction.

[0028] Figure 3 is a schematic diagram of an electronic device 100 during operation according to some embodiments of the present invention. Figure 2A , Figure 2B and Figure 3. When the electronic device 100 is in operation, the accumulation gate 130 generates a gate induced charge layer in the active region 116. Subsequently, the depletion gate 120 forms a tunnel barrier 118 that interrupts the gate induced charge layer with a single dopant injected into the active region 116. The depletion gate 120 also has the function of resonating the dopant level with the Fermi level of the lead. In the presence of a magnetic field, the Zeeman split dopant states can also be resolved. By applying a source-drain bias and adjusting the dopant level in resonance with the Fermi energy of the gate induced charge layer, a sharp conductivity peak is expected to be observed. By inducing the Zeeman splitting of the electron or hole spin states with an external magnetic field, spin-dependent tunneling can be observed. Due to the charging effect, resonant charge tunneling is continuous, that is, only one charge can pass through the barrier at a time through the dopant level. Coherent manipulation of the quantum state of the spin qubit can use the application of a magnetic field, whose frequency matches the Zeeman splitting of the spin state. In some embodiments, the magnetic field is oscillated at microwave frequencies to excite the spin resonance of a single electron (dopant), ie, electron spin resonance (ESR).

[0029] The magnetic field can be strong to allow rapid oscillation (or rotation) of the spin state. At the same time, the electric field in the tunnel barrier 118 may be weak or non-existent to ensure proper operation of the electronic device 100. Specifically, the electric field may cause some effects such as photon-assisted tunneling, disrupt the operation of the electronic device, and cause local heating of the electronic device. Embodiments of the present invention solve the problems in the existing methods by providing an improved structure that generates a strong magnetic field and a weak or negligible electric field at the tunnel barrier 118.

[0030] Specifically, Figure 3 As shown, since the first portion 142, the second portion 144, and the third portion 146 of the conductive resonator 140 surround the qubit position Q of the electronic device 100 (i.e., the intersection region of the tunnel barrier 118 and the third portion 136 of the accumulation gate 130), the conductive resonator 140 can generate a strong magnetic field (i.e., the sum of the magnetic fields B1, B2, and B3) at the qubit position Q. In some embodiments, with an input power of 0 dBm, the total magnetic field of the electronic device 100 is greater than about 8 mT at about 10 GHz to about 50 GHz.

[0031] In addition, if Figure 3As shown, the strength of the electric field E is reduced at the qubit position q. The first portion 142 and the second portion 144 of the conductive resonator 140 are configured to reduce the strength of the electric field E at the qubit position. The first portion 132 and the second portion 134 of the accumulation gate 130 also provide a good shielding effect for reducing the electric field strength at the qubit position q. In some embodiments, with an input power of 0 dBm, the ratio of the total magnetic field to the electric field of the electronic device 100 is greater than 10E2 mT*m / MV at about 10 GHz to about 50 GHz. Under such a high magnetic field, the electronic device 100 has a fast operating speed.

[0032] refer to Figure 1B and Figure 3 In some embodiments, the width W2 of the third portion 146 of the conductive resonator 140 is in the range of about 100 nm to about 500 nm. If the width W2 is less than about 100 nm, the magnetic field B3 may be reduced due to a larger angle between the current I of the conductive resonator 140 and the quantum dots. If the width W2 is greater than about 500 nm, the magnetic field B3 may be reduced due to a long distance between the current I of the conductive resonator 140 and the quantum dots. With such a high ratio, the electronic device 100 has a low noise environment.

[0033] refer to Figure 2A and Figure 2B . In some embodiments, a width W3 of each of the depletion gates 120 is in a range of about 5 nm to about 50 nm. In some embodiments, a width W4 of each of the first portion 132 and the second portion 134 of the accumulation gate 130 is in a range of about 5 nm to about 50 nm. In some embodiments, the width W4 is greater than the width W3 to provide good shielding of the electric field E. In addition, a width W5 of each of the first portion 142 and the second portion 144 of the conductive resonator 140 is in a range of about 50 nm to about 500 nm. In some embodiments, the width W5 is greater than the width W4 of the first portion 132 and the second portion 134 (and / or the width W3 of the depletion gate 120) to provide good shielding of the electric field E.

[0034] In some embodiments, the thickness T1 of each of the first portion 142 and the second portion 144 of the conductive resonator 140 is in the range of about 100 nm to about 500 nm. If the thickness T1 is less than about 100 nm, the magnetic fields B1 and B2 may be reduced because the current I of the conductive resonator 140 may flow into the conductive resonator 140. If the thickness T1 is greater than about 500 nm, the magnetic field B3 may be reduced due to the long distance between the current I of the conductive resonator 140 and the quantum dots. When the thickness T1 is in the range of about 100 nm to about 500 nm, the conductive resonator 140 has a small return loss.

[0035] In some embodiments, the thickness T2 of each of the depletion gates 120 is in a range of about 1 nm to about 50 nm. In some embodiments, the thickness T3 of the accumulation gate 130 is in a range of about 1 nm to about 50 nm. In some embodiments, the thickness T1 is greater than the thickness T3, and / or the thickness T3 is greater than the thickness T2. Figure 2A and Figure 2B As shown, the bottom surfaces 142b and 144b of the first portion 142 and the second portion 144 of the conductive resonator 140 are lower than the bottom surfaces 132b and 134b of the first portion 132 and the second portion 134 of the accumulation gate 130. In some embodiments, the bottom surfaces 142b and 144b are the bottommost surfaces of the conductive resonator 140, and the bottom surfaces 132b and 134b are the bottommost surfaces of the accumulation gate 130.

[0036] In addition, bottom surfaces 132b and 134b of the first and second portions 132 and 134 of the accumulation gate 130 are lower than the top surface 120t of the depletion gate 120. Bottom surfaces 142b and 144b of the first and second portions 142 and 144 of the conductive resonator 140 are substantially coplanar with the bottom surface 120b of the depletion gate 120 and are lower than the top surface 130t of the accumulation gate 130.

[0037] In some embodiments, the thickness T4 of the dielectric layer 150 between the depletion gate 120 and the substrate 110 is in the range of about 1 nm to about 20 nm. In some embodiments, the thickness T5 of the dielectric layer 160 between the depletion gate 120 and the accumulation gate 130 is in the range of about 1 nm to about 20 nm. In some embodiments, the thickness T6 of a portion of the dielectric layer 170 between the third portion 146 of the conductive resonator 140 and the first portion 132 (second portion 134) of the accumulation gate 130 is in the range of about 5 nm to about 50 nm. In some embodiments, the thickness T6' of a portion of the dielectric layer 170 between the first portion 142 (or second portion 144) of the conductive resonator 140 and the first portion 132 (or second portion 134) of the accumulation gate 130 is in the range of about 5 nm to about 50 nm. In some embodiments, the thickness T6 is different from the thickness T6'. In some other embodiments, the thicknesses T6 and T6' have the same value.

[0038] refer to Figure 2B and Figure 3 In some embodiments, the distance D4 between the first portion 142 and the second portion 144 of the conductive resonator 140 is in the range of about 45 nm to about 600 nm. If the distance D4 is greater than about 600 nm, the magnetic fields B1, B2, and B3 are reduced. If the distance D4 is less than about 45 nm, the conductive resonator 140 may lack space for accommodating the accumulation gate 130. Figure 1B and Figure 2B As shown, a distance D4 between the first portion 142 and the second portion 144 of the conductive resonator 140 is greater than a distance D2 between the first portion 132 and the second portion 134 of the accumulation gate 130. In some embodiments, a height difference H1 between the bottom surface 142b and the bottom surface 146b is in a range of about 5 nm to about 120 nm, so that the accumulation gate 130 and the depletion gate 120 can be disposed under the third portion 146 of the conductive resonator 140, and the conductive resonator 140 can generate a strong magnetic field.

[0039] Figure 4 is a perspective view of an electronic device 100 a according to some embodiments of the present invention. Figure 4 The electronic device 100a and Figure 1B The difference between the electronic devices 100 in FIG. 1 is the number of qubits. Specifically, Figure 1B The multiple electronic devices 100 in the embodiment can be combined into Figure 4 In this way, Figure 4 The electronic device 100a includes Figure 1B Multiple electronic devices 100 in. Figure 4 The electronic devices 100 in the same embodiment share the same conductive resonator 140. In more detail, the adjacent electronic devices 100 share the first portion 142 (or the second portion 144) of the conductive resonator 140. With this structure, Figure 4 The electronic device 100a in the embodiment includes a plurality of qubits arranged in a high-density array. In addition, the third portions 146 of the conductive resonators 140 of adjacent electronic devices 100 are not aligned with each other. In some embodiments, the length L2 of each of the first portion 142 and the second portion 144 is in the range of about 0.3um to about 10um. If the length L2 is less than about 0.3um, the magnetic fields B1 and B2 are reduced. Other relevant structural and manufacturing details of the electronic device 100a are substantially the same as those of Figure 1B to Figure 2B The electronic device 100 is the same or similar to the electronic device 100, so the description in this regard will not be repeated hereinafter.

[0040] Figure 5A and Figure 5B is a top view of a conductive resonator 140 according to some embodiments of the present invention. Figure 5A and Figure 5B The conductive resonator 140 and Figure 4 The difference between the conductive resonator 140 in FIG. 1 and FIG. 2 is the shape of the conductive resonator 140. Figure 5A and Figure 5B In FIG. 1 , the conductive resonator 140 has a sawtooth shape. Figure 5AIn the embodiment, the first portion 142, the second portion 144, and the third portion 146 form a semicircle, and a distance D4' between the first portion 142 and the second portion 144 is in the range of about 45 nm to about 600 nm. Figure 5B In FIG. 1 , first portion 142 , second portion 144 and third portion 146 form a semi-elliptical ring. The qubit position Q is adjacent to third portion 146 . FIG. 5A to FIG. 5B The other relevant structural and manufacturing details of the conductive resonator 140 are basically the same as those of Figure 4 The conductive resonator 140 is the same or similar to the conductive resonator 140, so the description in this regard will not be repeated hereinafter.

[0041] FIG. 6A to FIG. 19B 1 and 2 illustrate top views and cross-sectional views of intermediate stages in the formation of an electronic device 200 according to some embodiments of the present invention. In the various views and illustrative embodiments, like reference numerals are used to refer to like elements. It should be understood that the electronic device 200 may be used in the following embodiments. FIG. 6A to FIG. 19B Additional operations are provided before, during, and after the processes shown, and some of the operations described below may be replaced or eliminated for additional embodiments of the methods. The order of the operations / processes may be interchanged.

[0042] refer to Fig. 6A and Figure 6B ,in, Figure 6B It is along Fig. 6A A cross-sectional view taken from CC of . A substrate 210 is provided. In some embodiments, the substrate 210 may include silicon (Si). Alternatively, the substrate 210 may include germanium (Ge), silicon germanium, gallium arsenide (GaAs) or other suitable semiconductor materials. In some alternative embodiments, the substrate 210 may include an epitaxial layer with or without a dopant. In addition, the substrate 210 may include a semiconductor on insulator (SOI) structure having a buried dielectric layer therein. The buried dielectric layer may be, for example, a buried oxide (BOX) layer. The SOI structure may be formed by a method known as isolation by implantation of oxygen, wafer bonding, selective epitaxial growth (SEG) or other suitable methods. In some embodiments, the thickness of the substrate 210 is greater than about 500um to improve the performance of the electronic device 200.

[0043] A mask layer 310' (which may be a hard mask layer) is formed above the top surface 210t of the substrate 210. In some embodiments, the mask layer 310' comprises a nitride. For example, the mask layer 310' is made of silicon nitride (SiN). However, other materials such as SiON, silicon carbide, or a combination thereof may also be used. The mask layer 310' may be formed by a process such as chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), or low pressure chemical vapor deposition (LPCVD). Alternatively, the mask layer 310' may be made of silicon oxide and then converted to SiN by nitridation.

[0044] refer to Fig. 7A and Figure 7B ,in, Figure 7B It is along Fig. 7A Cross-sectional view taken from CC. Fig. 6A and Figure 6B The mask layer 310' in is then patterned by photolithography. Fig. 6A and Figure 6B A photoresist layer is formed above the structure in, and the photoresist layer is exposed and then developed to form a patterned photoresist layer, which leaves a portion of the exposed mask layer 310'. The mask layer 310' is then etched using reactive ion etching (RIE) and / or other suitable processes, and the patterned photoresist layer is used as an etching mask for etching the mask layer 310'. After the etching process, a patterned mask layer 310 having a source opening 312 and a drain opening 314 is formed above the substrate 210, and the patterned photoresist layer is removed. In some embodiments, the patterned photoresist layer can be removed using processes such as ashing and etching. The source opening 312 and the drain opening 314 expose portions of the substrate 210, respectively.

[0045] refer to Fig. 8A and Figure 8B ,in, Figure 8B It is along Fig. 8A Then, an implantation process is performed to introduce impurities into the substrate 210 through the source opening 312 and the drain opening 314, thereby forming the source region 212 and the drain region 214, and the mask layer 310 (see Fig. 7A and Figure 7B ) can be used as a mask to substantially prevent impurities from being implanted into other regions of the substrate 210. The impurities may be n-type impurities or p-type impurities. The n-type impurities may be phosphorus, arsenic, etc., and the p-type impurities may be boron, BF2, etc.

[0046] Subsequently, the patterned mask layer 310 is removed. The patterned mask layer 310 can be removed using a process such as wet etching. After the removal process, the substrate 210 having the source region 212 and the drain region 214 is exposed. After removing the patterned mask layer 310, one or more annealing processes may be performed to activate the source region 212 and the drain region 214. The annealing process includes a rapid thermal annealing (RTA) and / or a laser annealing process. The annealing process may repair the implantation damage of impurities on the bottom and sidewalls of the source region 212 and the drain region 214.

[0047] refer to Fig. 9A and Fig. 9B ,in, Fig. 9B It is along Fig. 9A The first isolation layer 205 is formed on the substrate 210. Specifically, the first isolation layer 205 may include a material such as an oxide formed by tetraethyl orthosilicate (TEOS), undoped silicate glass, or doped silicon oxide (such as borophosphosilicate glass (BPSG), fused quartz glass (FSG), phosphosilicate glass (PSG), borosilicate glass (BSG), and / or other suitable dielectric materials). The first isolation layer 205 can be deposited by a PECVD process or other suitable deposition techniques.

[0048] refer to Fig. 10A and Fig. 10B ,in, Fig. 10B It is along Fig. 10A 2. A cross-sectional view taken along CC of FIG. 2. An opening 207 is formed in the first isolation layer 205 to define an active area 216 in the substrate 210. In some embodiments, the opening 207 is formed using a combination of photolithography and etching processes as described above. In some embodiments, the etching process is a wet etching process. The opening 207 exposes a portion of the substrate 210, the source region 212, and the drain region 214. The exposed portion of the substrate 210 is defined as the active area 216. The top view of the active area 216 may be circular, oval, rectangular, square, or some other shape with or without rounded corners.

[0049] refer to Fig.11A and Fig. 11B ,in, Fig. 11B It is along Fig.11A The first gate dielectric layer 250 and the first conductive layer 220' are Fig. 10A and 10BThe first gate dielectric layer 250 is formed in sequence above the structure in the opening 207. The first gate dielectric layer 250 is conformally formed in the opening 207. The first gate dielectric layer 250 is located above the active region 216, the source region 212 and the drain region 214. In some embodiments, the first gate dielectric layer 250 may include silicon dioxide, silicon nitride or other suitable materials. Alternatively, the first gate dielectric layer 250 may be a high-κ dielectric layer having a dielectric constant (κ) higher than that of SiO2, i.e., κ>3.9. The first gate dielectric layer 250 may include LaO, AlO, ZrO, TiO, Ta2O5, Y2O3, SrTiO3 (STO), BaTiO3 (BTO), BaZrO, HfZrO, HfLaO, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (B, Sr)TiO3 (BST), Al2O3, Si3N4, oxynitride (SiON) or other suitable materials. The first gate dielectric layer 250 is deposited by a suitable technique such as ALD, CVD, PVD, thermal oxidation, combinations thereof, or other suitable techniques.

[0050] The first conductive layer 220' is formed over the first gate dielectric layer 250. The first conductive layer 220' includes one or more layers of conductive material. Examples of the first conductive layer 220' include W, Ti, TiAlC, Al, TiAl, TaN, TaAlC, TiN, TiC, Co, TaC, Al, TiAl, HfTi, TiSi, TaSi, TiAlC, or combinations thereof. The first conductive layer 220' may be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD) including sputtering, atomic layer deposition (ALD), or other suitable methods.

[0051] refer to Fig. 12A and Fig. 12B ,in, Fig. 12B It is along Fig. 12A Cross-sectional view taken from CC. Fig.11A and Fig. 11B The first conductive layer 220' in the embodiment is patterned to form a depletion gate 220. Fig. 12A and 12B In the embodiment of the present invention, there are three pairs of depletion gates 220, for example. The patterning of the first conductive layer 220' can be formed using a combination of photolithography and etching processes as described above. Each pair of depletion gates 220 is formed between one of the source regions 212 and one of the drain regions 214. A portion 222 of each of the depletion gates 220 is above the active region 216, and another portion 224 of each of the depletion gates 220 extends above the first isolation layer 250 to serve as a bonding pad for a contact formed subsequently. The depletion gates 220 are spaced apart from each other.

[0052] refer to Fig.13Aand Fig. 13B ,in, Fig. 13B It is along Fig.13A A cross-sectional view taken from CC of FIG. A second gate dielectric layer 260 and a second conductive layer 230′ are sequentially formed over the first gate dielectric layer 250 and the depletion gate 220. The second gate dielectric layer 260 is conformally formed over the first gate dielectric layer 250 and the depletion gate 220, so that the second gate dielectric layer 260 covers the first gate dielectric layer 250 and the depletion gate 220. In some embodiments, the second gate dielectric layer 260 may include silicon dioxide, silicon nitride, or other suitable materials. Alternatively, the second gate dielectric layer 260 may be a high-κ dielectric layer having a dielectric constant (κ) higher than that of SiO2, i.e., κ>3.9. The second gate dielectric layer 260 may include LaO, AlO, ZrO, TiO, Ta2O5, Y2O3, SrTiO3 (STO), BaTiO3 (BTO), BaZrO, HfZrO, HfLaO, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (B, Sr)TiO3 (BST), Al2O3, Si3N4, oxynitride (SiON), or other suitable materials. The second gate dielectric layer 260 is deposited by a suitable technique such as ALD, CVD, PVD, thermal oxidation, a combination thereof, or other suitable techniques.

[0053] Subsequently, a second conductive layer 230' is formed over the second gate dielectric layer 260. The second conductive layer 230' includes one or more layers of conductive material. Examples of the second conductive layer 230' include W, Ti, TiAlC, Al, TiAl, TaN, TaAlC, TiN, TiC, Co, TaC, Al, TiAl, HfTi, TiSi, TaSi, TiAlC, or combinations thereof. The second conductive layer 230' may be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD) including sputtering, atomic layer deposition (ALD), or other suitable methods. The first conductive layer 220' and the second conductive layer 230' (i.e., the depletion gate 220 and the subsequently formed accumulation gate 230) are made of the same or different materials.

[0054] refer to Fig.14A and Fig. 14B ,in, Fig. 14B It is along Fig.14A Cross-sectional view taken from CC. Fig.13A and Fig. 13BThe second conductive layer 230' in the embodiment is patterned to form the accumulation gate 230. The patterning of the second conductive layer 230' can be formed using a combination of photolithography and etching processes as described above. Each of the accumulation gates 230 includes a first portion 232, a second portion 234, and a third portion 236 interconnecting the first portion 232 and the second portion 234.

[0055] refer to Fig.15A and Fig. 15B ,in, Fig. 15B It is along Fig.15A The second isolation layer 270 is formed over the second gate dielectric layer 260 and the accumulation gate 230. Specifically, the second isolation layer 270 covers the accumulation gate 230 and may include a material such as an oxide formed of tetraethyl orthosilicate (TEOS), undoped silicate glass, or doped silicon oxide (such as borophosphosilicate glass (BPSG), fused quartz glass (FSG), phosphosilicate glass (PSG), borosilicate glass (BSG), and / or other suitable dielectric materials). The second isolation layer 270 may be deposited by a PECVD process or other suitable deposition techniques.

[0056] refer to FIG. 16A to FIG. 16B ,in, Fig. 16B It is along Fig.16A A plurality of openings 272 are formed in the second isolation layer 270. The openings 272 further extend into the second gate dielectric layer 260. In some embodiments, the openings 272 are formed using a combination of photolithography and etching processes as described above. The openings 272 do not overlap with the accumulation gate 230, so that the openings 272 do not expose the accumulation gate 230 and the depletion gate 220.

[0057] refer to Fig.17A and Fig. 17B ,in, Fig. 17B It is along Fig.17A A third conductive layer is formed over the second isolation layer 270 and fills the opening 272, and the third conductive layer is patterned using a combination of photolithography and etching processes to form a conductive resonator 240. In some embodiments, the conductive resonator 240 includes one or more layers of conductive material. Examples of the conductive resonator 240 include W, Ti, TiAlC, Al, TiAl, TaN, TaAlC, TiN, TiC, Co, TaC, Al, TiAl, HfTi, TiSi, TaSi, TiAlC, or combinations thereof. The conductive resonator 240 may be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD) including sputtering, atomic layer deposition (ALD), or other suitable methods. Fig.17AAs shown, the portion of the conductive resonator 240 outside the opening 272 is a third portion of the conductive resonator 240 .

[0058] refer to Fig.18A and Fig.18B ,in, Fig.18B It is along Fig.18A The second isolation layer 270 is further etched by various methods (including dry etching, wet etching, or a combination of dry etching and wet etching) to form a plurality of openings 274. The openings 274 extend through the second isolation layer 270 (and the underlying dielectric layer) and expose the source region 212 and the drain region 214, respectively. In some embodiments, the openings 274 are formed using a combination of photolithography and etching processes as described above.

[0059] refer to Fig.19A and Fig.19B ,in, Fig.19B It is along Fig.19A A fourth conductive layer is formed over the second isolation layer 270 and fills the opening 274, and the fourth conductive layer is patterned using a combination of photolithography and etching processes to form a source contact 280 and a drain contact 285. In some embodiments, the source contact 280 and the drain contact 285 include one or more layers of conductive material. Examples of the source contact 280 and the drain contact 285 include W, Ti, TiAlC, Al, TiAl, TaN, TaAlC, TiN, TiC, Co, TaC, Al, TiAl, HfTi, TiSi, TaSi, TiAlC, or combinations thereof. The source contact 280 and the drain contact 285 may be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD) including sputtering, atomic layer deposition (ALD), or other suitable methods. In some embodiments, before forming the fourth conductive layer, a mask layer is formed over the conductive resonator 240 to protect the conductive resonator 240 , and the mask layer is removed after forming the source contact 280 and the drain contact 285 .

[0060] Optionally, a protective layer 290 is formed over the second isolation layer 270, the conductive resonator 240, the source contact 280, and the drain contact 290. In some embodiments, the protective layer 290 may include silicon dioxide, silicon nitride, or other suitable materials. Alternatively, the protective layer 290 may be a high-κ dielectric layer having a dielectric constant (κ) higher than that of SiO2, i.e., κ>3.9. The protective layer 290 may include LaO, AlO, ZrO, TiO, Ta2O5, Y2O3, SrTiO3 (STO), BaTiO3 (BTO), BaZrO, HfZrO, HfLaO, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (B, Sr)TiO3 (BST), Al2O3, Si3N4, oxynitride (SiON), or other suitable materials. The protective layer 290 is deposited by a suitable technique such as ALD, CVD, PVD, thermal oxidation, combinations thereof, or other suitable techniques.

[0061] Fig. 20A and Fig. 20B The simulation results of the magnetic field and the ratio of the total magnetic field to the electric field of the electronic device at different positions are shown. Fig. 20A and Fig. 20B In , the electronic device includes 11 qubits, and the magnetic field values ​​and the ratio of the total magnetic field to the electric field values ​​are shown as a function of position. Fig. 20A In FIG. 9 , curve 902 represents the magnetic field value obtained along line MM, and curve 904 represents the ratio of the total magnetic field to the electric field value obtained along line MM. Fig. 20B , curve 906 represents the magnetic field values ​​taken along line NN, and curve 908 represents the ratio of the total magnetic field to the electric field values ​​taken along line NN.

[0062] Fig.21 The diagram shows different thicknesses of conductive resonators (e.g. Figure 2A The return loss of the electronic device with thickness T1 in |S 11 |Simulation and measurement results. Fig.21 , curve 912 represents a simulated return loss of an electronic device having a first thickness of a conductive resonator, curve 914 represents a measured return loss of an electronic device having a first thickness of a conductive resonator, curve 916 represents a simulated return loss of an electronic device having a second thickness of a conductive resonator, and curve 918 represents a measured return loss of an electronic device having a second thickness of a conductive resonator, wherein the first thickness is greater than the second thickness.

[0063] Fig.22A and Fig. 22B Illustration of the return loss of the electronic device with different numbers of qubits and different thicknesses of the conductive resonator |S 11|Simulation and measurement results. Fig.22A In , curve 922 represents a simulated return loss of an electronic device having a first number of qubits and having a third thickness of a conductive resonator, curve 924 represents a measured return loss of an electronic device having a first number of qubits and having a third thickness of a conductive resonator, curve 926 represents a simulated return loss of an electronic device having a second number of qubits and having a third thickness of a conductive resonator, curve 928 represents a measured return loss of an electronic device having a second number of qubits and having a third thickness of a conductive resonator, curve 932 represents a simulated return loss of an electronic device having a third number of qubits and having a third thickness of a conductive resonator, and curve 934 represents a measured return loss of an electronic device having a third number of qubits and having a third thickness of a conductive resonator, wherein the third number is greater than the second number, and the second number is greater than the first number. In Fig. 22B , curve 942 represents a simulated return loss for an electronic device having a first number of qubits and having a fourth thickness of the conductive resonator, curve 944 represents a measured return loss for an electronic device having a first number of qubits and having a fourth thickness of the conductive resonator, curve 946 represents a simulated return loss for an electronic device having a second number of qubits and having a fourth thickness of the conductive resonator, curve 948 represents a measured return loss for an electronic device having a second number of qubits and having a fourth thickness of the conductive resonator, curve 952 represents a simulated return loss for an electronic device having a third number of qubits and having a fourth thickness of the conductive resonator, and curve 954 represents a measured return loss for an electronic device having a third number of qubits and having a fourth thickness of the conductive resonator, wherein the fourth thickness is greater than the third thickness.

[0064] Fig.23A and Fig. 23B The diagram shows different thicknesses and widths of the conductive resonator (e.g., Figure 2A The return loss of the electronic device with width W5 in |S 11 |The measurement results. Fig.23A , curve 962 represents the measured return loss of an electronic device having a fifth thickness and a first width of the conductive resonator, curve 964 represents the measured return loss of an electronic device having a fifth thickness and a second width of the conductive resonator, and curve 966 represents the measured return loss of an electronic device having a fifth thickness and a third width of the conductive resonator, wherein the first width is greater than the second width, and the second width is greater than the third width. Fig. 23B, curve 972 represents the measured return loss of an electronic device having a sixth thickness and a first width of the conductive resonator, curve 964 represents the measured return loss of an electronic device having a sixth thickness and a second width of the conductive resonator, and curve 966 represents the measured return loss of an electronic device having a sixth thickness and a third width of the conductive resonator, wherein the sixth thickness is greater than the fifth thickness.

[0065] Based on the above discussion, it can be seen that the present invention has many advantages. However, it should be understood that other embodiments may provide additional advantages, not all advantages need be disclosed here, and no specific advantages are required for all embodiments. One advantage is that the conductive resonator can generate a strong magnetic field and a weak or negligible electric field at the qubit location, so that the qubits generated in the qubit location have high efficiency. In addition, adjacent qubits can share a conductive resonator to obtain an electronic device with a high qubit density. In addition, the electronic device has a simple structure and can be integrated for IC design and / or PCB design.

[0066] According to some embodiments, an electronic device includes a pair of depletion gates, an accumulation gate, and a conductive resonator. The depletion gates are spaced apart from each other. The accumulation gate is located above the depletion gate. The conductive resonator is located above the depletion gate and the accumulation gate. The conductive resonator includes a first portion, a second portion, and a third portion. The first portion and the second portion are located on opposite sides of the accumulation gate. The third portion interconnects the first portion and the second portion of the conductive resonator and spans the depletion gate. The bottom surface of the first portion of the conductive resonator is lower than the bottom surface of the accumulation gate.

[0067] In some embodiments, the accumulation gate includes: a first portion and a second portion located on opposite sides of the depletion gate; and a third portion interconnecting the first portion and the second portion of the accumulation gate and spanning the depletion gate. In some embodiments, in a top view, the third portion of the accumulation gate is spaced apart from the third portion of the conductive resonator. In some embodiments, the first portion of the accumulation gate is closer to the first portion of the conductive resonator relative to the depletion gate. In some embodiments, the distance between the first portion and the second portion of the conductive resonator is greater than the distance between the first portion and the second portion of the accumulation gate. In some embodiments, the bottom surface of the accumulation gate is lower than the top surface of the depletion gate. In some embodiments, the electronic device further includes a source region and a drain region located below the depletion gate, wherein the third portion of the conductive resonator is located between the source region and the drain region of the conductive resonator.

[0068] According to some embodiments, an electronic device includes a pair of depletion gates, an accumulation gate, and a conductive resonator. The depletion gates are spaced apart from each other. The accumulation gate includes a first portion, a second portion, and a third portion. The first portion and the second portion are located on opposite sides of the depletion gate. The third portion interconnects the first portion and the second portion of the accumulation gate and spans the depletion gate. The conductive resonator includes a first portion, a second portion, and a third portion. The first portion and the second portion are located on opposite sides of the depletion gate. The first portion of the accumulation gate is located between the first portion of the conductive resonator and the depletion gate. The third portion interconnects the first portion and the second portion of the conductive resonator.

[0069] In some embodiments, the second portion of the accumulation gate is located between the second portion of the conductive resonator and the depletion gate. In some embodiments, the third portion of the conductive resonator spans the first portion and the second portion of the accumulation gate. In some embodiments, in a top view, the third portion of the conductive resonator is offset from the third portion of the accumulation gate. In some embodiments, the width of the first portion of the conductive resonator is greater than the width of one of the depletion gates. In some embodiments, the bottom surface of the conductive resonator is substantially coplanar with the bottom surface of the depletion gate. In some embodiments, the bottom surface of the conductive resonator is lower than the top surface of the accumulation gate.

[0070] According to some embodiments, a method includes forming a pair of depletion gates above a substrate. A first gate dielectric layer is deposited above the substrate to cover the pair of depletion gates. An accumulation gate is formed above the first gate dielectric layer. An isolation layer is deposited above the accumulation gate. An opening is formed in the isolation layer and extends into the first gate dielectric layer. A conductive resonator is partially formed in the opening of the isolation layer such that a bottom surface of the conductive resonator is lower than a top surface of the depletion gate.

[0071] In some embodiments, the method further comprises: forming a second gate dielectric layer over the substrate before forming the pair of depletion gates. In some embodiments, the opening is formed in the isolation layer such that the opening exposes the second gate dielectric layer. In some embodiments, the method further comprises: forming a source region and a drain region in the substrate before forming the pair of depletion gates. In some embodiments, forming the conductive resonator comprises forming a portion of the conductive resonator outside the opening of the isolation layer. In some embodiments, the conductive resonator is formed such that a portion of the conductive resonator outside the opening of the isolation layer spans the accumulation gate and the depletion gate.

[0072] The features of several embodiments are summarized above so that those skilled in the art can better understand aspects of the present invention. Those skilled in the art should understand that they can easily use the present invention as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the present invention, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present invention.

Claims

1. An electronic device comprising: a pair of depletion gates spaced apart from each other; an accumulation gate, located above the depletion gate, wherein the accumulation gate comprises: first and second portions located on opposite sides of the depletion gate; and a third portion interconnecting the first portion and the second portion of the accumulation gate and spanning the depletion gate; and a conductive resonator located above the depletion gate and the accumulation gate, wherein the conductive resonator comprises: a first portion and a second portion located on opposite sides of the accumulation gate; and a third portion interconnecting the first portion and the second portion of the conductive resonator and spanning the depletion gate, wherein a bottom surface of the first portion of the conductive resonator is lower than a bottom surface of the accumulation gate, The first portion of the conductive resonator, the second portion of the conductive resonator, and the third portion of the conductive resonator surround a qubit position Q of the electronic device, the qubit position Q is an intersection region of a tunnel barrier generated by the depletion gate and the third portion of the accumulation gate, and the first portion of the conductive resonator and the second portion of the conductive resonator are configured to reduce the strength of an electric field at the qubit position Q, and the first portion of the accumulation gate and the second portion of the accumulation gate are configured to reduce the strength of an electric field at the qubit position Q.

2. The electronic device according to claim 1, wherein: The third portion of the conductive resonator has a top surface that is higher than a top surface of the first portion of the conductive resonator.

3. The electronic device according to claim 2, wherein: In a top view, the third portion of the accumulation gate is spaced apart from the third portion of the conductive resonator.

4. The electronic device according to claim 2, wherein: The first portion of the accumulation gate is closer to the first portion of the conductive resonator than the depletion gate.

5. The electronic device according to claim 2, wherein: A distance between the first portion and the second portion of the conductive resonator is greater than a distance between the first portion and the second portion of the accumulation gate.

6. The electronic device according to claim 1, wherein: The bottom surface of the accumulation gate is lower than a top surface of the depletion gate.

7. The electronic device according to claim 1, further comprising a source region and a drain region located below the depletion gate, wherein: The third portion of the conductive resonator is located between the source region and the drain region of the conductive resonator.

8. An electronic device comprising: a pair of depletion gates spaced apart from each other; An accumulation gate, the accumulation gate comprising: first and second portions located on opposite sides of the depletion gate; and a third portion interconnecting the first portion and the second portion of the accumulation gate and spanning the depletion gate; and A conductive resonator, the conductive resonator comprising: a first portion and a second portion located on opposite sides of the depletion gate, wherein the first portion of the accumulation gate is located between the first portion of the conductive resonator and the depletion gate; and a third portion interconnecting the first portion and the second portion of the conductive resonator, The first portion of the conductive resonator, the second portion of the conductive resonator, and the third portion of the conductive resonator surround a qubit position Q of the electronic device, the qubit position Q is an intersection region of a tunnel barrier generated by the depletion gate and the third portion of the accumulation gate, and the first portion of the conductive resonator and the second portion of the conductive resonator are configured to reduce the strength of an electric field at the qubit position Q, and the first portion of the accumulation gate and the second portion of the accumulation gate are configured to reduce the strength of an electric field at the qubit position Q.

9. The electronic device according to claim 8, wherein: The second portion of the accumulation gate is located between the second portion of the conductive resonator and the depletion gate.

10. The electronic device according to claim 8, wherein: The third portion of the conductive resonator spans the first portion and the second portion of the accumulation gate.

11. The electronic device according to claim 8, wherein: In a top view, the third portion of the conductive resonator is offset from the third portion of the accumulation gate.

12. The electronic device according to claim 8, wherein: The first portion of the conductive resonator has a width greater than a width of one of the depletion gates.

13. The electronic device according to claim 8, wherein: A bottom surface of the conductive resonator is substantially coplanar with a bottom surface of the depletion gate.

14. The electronic device according to claim 8, wherein: The bottom surface of the conductive resonator is lower than the top surface of the accumulation gate.

15. A method for manufacturing an electronic device, comprising: forming a pair of depletion gates over the substrate; depositing a first gate dielectric layer over the substrate to cover the pair of depletion gates; forming an accumulation gate over the first gate dielectric layer; depositing an isolation layer over the accumulation gate; forming an opening in the isolation layer and extending into the first gate dielectric layer; as well as forming a conductive resonator partially located in the opening of the isolation layer so that a bottom surface of the conductive resonator is lower than a top surface of the depletion gate, Wherein, the accumulation gate comprises: first and second portions located on opposite sides of the depletion gate; and a third portion interconnecting the first portion and the second portion of the accumulation gate and spanning the depletion gate, The conductive resonator includes a first portion and a second portion located in the opening and a third portion located outside the opening, the first portion of the conductive resonator, the second portion of the conductive resonator, and the third portion of the conductive resonator surround a qubit position Q of the electronic device, the qubit position Q is an intersection region of a tunnel barrier generated by the depletion gate and the third portion of the accumulation gate, and the first portion of the conductive resonator and the second portion of the conductive resonator are configured to reduce the strength of an electric field at the qubit position Q, and the first portion of the accumulation gate and the second portion of the accumulation gate are configured to reduce the strength of an electric field at the qubit position Q.

16. The method according to claim 15, further comprising: Prior to forming the pair of depletion gates, a second gate dielectric layer is formed over the substrate.

17. The method according to claim 16, wherein: The opening is formed in the isolation layer such that the opening exposes the second gate dielectric layer.

18. The method according to claim 15, further comprising: Prior to forming the pair of depletion gates, source and drain regions are formed in the substrate.

19. The method according to claim 15, wherein: The third portion of the conductive resonator has a top surface that is higher than a top surface of the first portion of the conductive resonator.

20. The method according to claim 15, wherein: The conductive resonator is formed such that a third portion of the conductive resonator outside the opening of the isolation layer spans across the accumulation gate and the depletion gate.

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