A method and device for improving the reliability test efficiency of resistive memory

Abstract

The present invention relates to the application field of resistive memory, and in particular to a method and device for improving the efficiency of resistive memory reliability testing, the method comprising: first defining the absolute value of the difference between the high resistance value and the low resistance value of the resistive memory as a window size, as a basis for judging whether the resistive memory is in an abnormal state, then performing read and write operations on the resistive memory through a read and write operation circuit, and simultaneously starting an abnormal detection circuit to detect in real time whether the resistive memory is in an abnormal state during the read and write operation process, if in an abnormal state, making the read and write operation circuit perform abnormal read and write operations on the resistive memory, otherwise performing normal read and write operations. The present invention can speed up the test rate of the reliability of the resistive memory, improve the test efficiency of the resistive memory, and can also accurately locate the number of rounds in which the abnormality occurs, so as to facilitate the analysis and processing of the resistive memory.

Description

Technical Field

[0001] The present invention relates to the application field of resistive random access memory, and in particular to a method and a device for improving the reliability test efficiency of a resistive random access memory. Background Art

[0002] When performing reliability testing of resistive random access memory, it is necessary to perform set, read and reset, and read operations cyclically, wherein the read operation is relatively time-consuming, resulting in a long overall test time and low efficiency. In order to improve the test efficiency, an existing test method for periodic reading is disclosed, that is, a read operation is performed every N cycle periods, and only set and reset operations are performed in the first N-1 cycles, where N is a constant greater than 0. This method can greatly improve the test efficiency and shorten the test cycle, but it also introduces other problems, that is, in order to shorten the test cycle, N is generally larger, and the larger N is, the shorter the test time is, but because N is a larger value, only set and reset operations are performed between N and 2N, and it is impossible to accurately judge whether the reliability failure of the resistive random access memory is between N and 2N, and it is impossible to accurately evaluate the reliability performance, and the key read and write data information during the period when the resistive random access memory is about to fail is also missing. Summary of the invention

[0003] In order to solve the above technical problems existing in the prior art, the present invention proposes a method and device for improving the reliability test efficiency of a resistive random access memory, which detects in real time whether the resistive random access memory is in an abnormal state through an abnormal detection circuit, and switches between a normal detection state and an abnormal detection state in real time, thereby determining whether to perform a normal read / write operation step or an abnormal read / write operation step. The specific technical solution is as follows:

[0004] A method for improving the reliability test efficiency of a resistive memory comprises the following steps: firstly defining the absolute value of the difference between a high resistance value and a low resistance value of the resistive memory as a window size W0 as a basis for judging whether the resistive memory is in an abnormal state; then performing read and write operations on the resistive memory through a read and write operation circuit; and simultaneously starting an abnormality detection circuit to detect in real time whether the resistive memory is in an abnormal state during the read and write operations; if the resistive memory is in an abnormal state, the read and write operation circuit performs abnormal read and write operations on the resistive memory; otherwise, a normal read and write operation is performed.

[0005] Furthermore, the abnormality detection circuit is composed of a mirror circuit, a transistor, a resistor Rs, a comparator and a pulse statistics circuit. The current generated by the resistive random access memory is obtained by mirroring the mirror circuit. The current flows through the transistor to the resistor Rs, and at the same time generates a voltage Vs. The voltage Vs and the preset voltage Vp are respectively input to the two input ends of the comparator. The output end of the comparator outputs high and low level pulses. The pulse statistics circuit detects the change of current according to the high and low level pulses, and determines whether the resistive random access memory is in an abnormal state according to the change of current.

[0006] Furthermore, when the abnormality detection circuit determines that the resistive memory is in an abnormal state, the abnormality detection circuit reads the window size of the resistive memory in real time. If the real-time read window size is greater than A times the defined window size W0, or less than B times the defined window size W0, the resistive memory is determined to be in an abnormal state, where A and B are numbers greater than 0, and A>B.

[0007] Further, the read-write operation circuit performs normal read-write operations on the resistive memory, specifically: firstly, a preset number of operations is performed, and then a first operation and a second operation are cyclically performed on the resistive memory, and the first composite operation and the second composite operation are performed once every specified number of times, wherein the specified number of times is greater than or equal to a minimum number of preset operation times and less than a maximum number of preset operation times;

[0008] The first operation is a set operation, the second operation is a reset operation, the first composite operation includes a set operation and a read operation, and the second composite operation includes a reset operation and a read operation.

[0009] Further, the method firstly presets the number of operations, then cyclically executes the first operation and the second operation on the resistive random access memory, and executes the first composite operation and the second composite operation once every specified number of times, wherein the specified number of times is greater than or equal to the minimum number of preset operation times and less than the maximum number of preset operation times, specifically comprising the following steps:

[0010] Step S1: For the 1st to K1th times, the first operation and the second operation are cyclically performed on the resistive random access memory, and the first combined operation and the second combined operation are performed once every N0 times, where N0 is an integer greater than 0 and less than K1;

[0011] Step S2: From K1 to K2 times, the first operation and the second operation are cyclically performed on the resistive random access memory, and the first combined operation and the second combined operation are performed once every N1 times, where N1 is an integer greater than N0 and less than K2;

[0012] Step S3: From K2 to K3 times, cyclically executing the first operation and the second operation on the resistive random access memory, and executing the first combined operation and the second combined operation once every N2 times, wherein N2 is an integer greater than N1 and less than K3;

[0013] Step S4: For the K3-K4th time, the first operation and the second operation are cyclically performed on the resistive random access memory, and the first combined operation and the second combined operation are performed once every N3 times, where N3 is an integer greater than N2 and less than K4;

[0014] Step S5: For the K4-K5th time, the first operation and the second operation are cyclically performed on the resistive random access memory, and the first combined operation and the second combined operation are performed once every N4 times, where N4 is an integer greater than N3 and less than K5;

[0015] And so on.

[0016] Furthermore, the read / write operation circuit performs abnormal read / write operations on the resistive memory, specifically: cyclically performing a first composite operation and a second composite operation on the resistive memory, wherein the first composite operation includes a set operation and a read operation, and the second reset operation includes a reset operation and a read operation.

[0017] A device for improving the reliability test efficiency of a resistive memory comprises a resistive memory, a read / write operation circuit and an abnormality detection circuit which are connected to each other. The read / write operation circuit performs read / write operations on the resistive memory, and the abnormality detection circuit detects the resistive memory and determines whether it is in an abnormal state. When it is in an abnormal state, the read / write operation circuit performs abnormal read / write operations on the resistive memory. When it is in a normal state, the read / write operation circuit performs normal read / write operations on the resistive memory.

[0018] Furthermore, the abnormality detection circuit includes a mirror circuit, a transistor, a resistor Rs, a comparator and a pulse statistics circuit, one end of the mirror circuit is connected to the resistive memory to obtain the current generated by the resistive memory, the other end is connected to the first end of the transistor, the second end of the transistor is connected to the power supply end, the third end of the transistor is connected to one end of the resistor Rs and then connected to the first input end of the comparator, the other end of the resistor Rs is grounded, the second input end of the comparator is connected to a preset external voltage Vp, and the output end of the comparator is connected to the pulse statistics circuit;

[0019] The current of the resistive memory is mirrored by the current mirror circuit and then flows through the transistor to the resistor Rs, generating a voltage Vs at the same time. The voltage Vs and the preset voltage Vp are respectively input to the two input ends of the comparator. The output end of the comparator outputs high and low level pulses. The pulse statistics circuit detects the current change based on the high and low level pulses.

[0020] Beneficial effects:

[0021] The present invention can accelerate the test rate of the reliability of the resistive random access memory, improve the test efficiency of the resistive random access memory, and can also accurately locate the number of abnormal rounds, and can obtain key read and write data information during the period when the reliability of the resistive random access memory is about to fail, including its accurate read and write times, so as to facilitate the analysis and processing of the resistive random access memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 It is a principle block diagram of the present invention;

[0023] Figure 2 is a schematic diagram of a storage unit of a resistive random access memory of the present invention;

[0024] Figure 3 It is a schematic diagram of the abnormality detection circuit of the present invention. DETAILED DESCRIPTION

[0025] In order to make the purpose, technical scheme and technical effect of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments.

[0026] The present invention proposes a method for improving the reliability test efficiency of a resistive random access memory. First, the absolute value of the difference between a high resistance value and a low resistance value of the resistive random access memory is defined as a window size W0 as a basis for judging whether the resistive random access memory is in an abnormal state. Then, a read-write operation circuit performs a read-write operation on the resistive random access memory, and simultaneously starts an abnormal detection circuit to detect in real time whether the resistive random access memory is in an abnormal state during the read-write operation. If the resistive random access memory is in an abnormal state, the read-write operation circuit performs an abnormal read-write operation on the resistive random access memory, otherwise, a normal read-write operation is performed.

[0027] The abnormal state specifically includes the following two situations:

[0028] (1) If the real-time reading window is larger than A times the initially defined window W0, it is an abnormal state;

[0029] (2) If the real-time reading window is smaller than B times the initially defined window W0, it is an abnormal state; A and B are numbers greater than 0, and A>B.

[0030] If no abnormal state is detected, the normal read and write operation state is maintained, that is, the normal read and write operation steps are performed by the read and write operation circuit, specifically including the following steps:

[0031] Step S1: For the 1st to K1th times, the first operation and the second operation are cyclically performed on the resistive random access memory, and the first combined operation and the second combined operation are performed once every N0 times, where N0 is an integer greater than 0 and less than K1;

[0032] Step S2: From K1 to K2 times, the first operation and the second operation are cyclically performed on the resistive random access memory, and the first combined operation and the second combined operation are performed once every N1 times, where N1 is an integer greater than N0 and less than K2;

[0033] Step S3: From K2 to K3 times, cyclically executing the first operation and the second operation on the resistive random access memory, and executing the first combined operation and the second combined operation once every N2 times, wherein N2 is an integer greater than N1 and less than K3;

[0034] Step S4: For the K3-K4th time, the first operation and the second operation are cyclically performed on the resistive random access memory, and the first combined operation and the second combined operation are performed once every N3 times, where N3 is an integer greater than N2 and less than K4;

[0035] Step S5: For the K4-K5th time, the first operation and the second operation are cyclically performed on the resistive random access memory, and the first combined operation and the second combined operation are performed once every N4 times, where N4 is an integer greater than N3 and less than K5;

[0036] By analogy, the number of tests can theoretically be infinite;

[0037] The first operation is a set operation, the second operation is a reset operation, the first composite operation includes a set operation and a read operation, and the second composite operation includes a reset operation and a read operation.

[0038] If the abnormality detection circuit detects an abnormality during the above test steps, it enters an abnormal state and performs abnormal read and write operations through the read and write operation circuit: cyclically execute the first compound operation and the second compound operation on the resistive memory until the abnormal state is exited and the above steps are continued.

[0039] Example:

[0040] A method for improving the reliability test efficiency of a resistive random access memory of the present invention includes the following steps: performing normal read and write operations through a read and write operation circuit when no abnormal state is detected:

[0041] S1: For the 1-1Kth time, the first operation and the second operation are cyclically executed on the resistive random access memory, and the first composite operation and the second composite operation are executed once every other time;

[0042] S2: For the 1K-10K times, the first operation and the second operation are cyclically executed on the resistive random access memory, and the first composite operation and the second composite operation are executed once every 10 times;

[0043] S3: For the 10K-100K times, the first operation and the second operation are cyclically executed on the resistive random access memory, and the first composite operation and the second composite operation are executed once every 100 times;

[0044] S4: for the 100K-1Mth time, the first operation and the second operation are cyclically executed on the resistive random access memory, and the first composite operation and the second composite operation are executed once every 1K times;

[0045] S5: For the 1M-10M times, the first operation and the second operation are cyclically executed on the resistive random access memory, and the first composite operation and the second composite operation are executed once every 10K times;

[0046] Similarly, if the abnormality detection circuit detects an abnormality in the above test steps, the first composite operation and the second operation are looped until the abnormal state is exited and the above steps are continued. 1M=1000K, 1K=1000.

[0047] The initial high resistance is set to 100K, the initial low resistance is set to 20K, then the initial window size W0 is 80K, A is 5, B is 0.5, and the abnormal state includes the following two situations:

[0048] (1) If the window size is larger than 5.0 times the initially defined window size of 80K, that is, 400K, it is defined as abnormal state 1;

[0049] (2) If the window size is less than 0.5 times the initially defined window size of 80K, that is, 40K, it is defined as abnormal state 2;

[0050] Among them, Figure 2 As shown, the conditions for applying the first operation, the second operation, and the read operation applied by the read / write operation circuit to the resistive memory storage unit are as follows:

[0051] First operation: a single pulse is applied to the bit line, with a pulse amplitude of 2.0V and a pulse width of 500ns, a level of 1.2V is applied to the word line, and a level of 0V is applied to the source line;

[0052] Second operation: 0V level is applied to the bit line, 3.0V level is applied to the word line, and a single pulse is applied to the source line, with a pulse amplitude of 2.5V and a pulse width of 500ns;

[0053] Read operation: 0.4V is applied to the bit line, 3.3V is applied to the word line, and 0V is applied to the source line;

[0054] Through the above steps, the test rate of the reliability of the resistive random access memory can be accelerated, the test efficiency of the resistive random access memory can be improved, and the number of rounds in which the abnormality occurs can be accurately located, which facilitates the analysis and processing of the resistive random access memory.

[0055] Corresponding to the aforementioned embodiment of a method for improving the efficiency of a reliability test of a resistive memory, the present invention further provides an embodiment of a device for improving the efficiency of a reliability test of a resistive memory.

[0056] like Figure 1As shown, a device for improving the reliability test efficiency of a resistive memory of the present invention includes a resistive memory, a read-write operation circuit and an abnormality detection circuit. The read-write operation circuit performs read-write operations on the resistive memory, and the abnormality detection circuit detects the resistive memory and determines whether it is in an abnormal state. When it is in an abnormal state, the read-write operation circuit performs abnormal read-write operations on the resistive memory. When it is in a normal state, the read-write operation circuit performs normal read-write operations on the resistive memory.

[0057] like Figure 3 As shown, the abnormality detection circuit is composed of a mirror circuit, a transistor, a resistor Rs, a comparator and a pulse statistical circuit. The current flowing through the resistive memory is mirrored to the abnormality detection circuit in a current mirroring manner. During the normal write operation of the resistive memory, the set and reset operations will cause the current to change. After passing through the mirror circuit, the current flowing through the transistor to the resistor Rs changes dynamically to generate a voltage Vs. The voltage Vs and the set voltage Vp are respectively input to the two input terminals of the comparator. The output terminal of the comparator outputs high and low level pulses. Finally, the current change is detected by the pulse statistical circuit. Therefore, if the write operation of the resistive memory is abnormal, the current change of the resistive memory will be reflected in the pulse statistical circuit.

[0058] The above is only a preferred implementation case of the present invention and does not limit the present invention in any form. Although the implementation process of the present invention is described in detail above, for those familiar with the art, they can still modify the technical solutions recorded in the above examples, or replace some of the technical features therein with equivalents. All modifications, equivalent replacements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for improving the reliability test efficiency of a resistive random access memory, characterized in that: First, the absolute value of the difference between the high resistance value and the low resistance value of the resistive memory is defined as the window size W0, which is used as a basis for judging whether the resistive memory is in an abnormal state. Then, the resistive memory is read and written by the read and write operation circuit, and the abnormality detection circuit is started to detect in real time whether the resistive memory is in an abnormal state during the read and write operation. If it is in an abnormal state, the read and write operation circuit performs abnormal read and write operations on the resistive memory, otherwise, normal read and write operations are performed. The read / write operation circuit performs abnormal read / write operations on the resistive memory, specifically: cyclically performing a first composite operation and a second composite operation on the resistive memory; The read / write operation circuit performs normal read / write operations on the resistive memory, specifically: firstly, a preset number of operations is performed, and then a first operation and a second operation are cyclically performed on the resistive memory, and the first composite operation and the second composite operation are performed once every specified number of times, wherein the specified number of times is greater than or equal to a minimum number of preset operation times and less than a maximum number of preset operation times; The first operation is a set operation, the second operation is a reset operation, the first composite operation includes a set operation and a read operation, and the second composite operation includes a reset operation and a read operation.

2. A method for improving the reliability test efficiency of a resistive random access memory as claimed in claim 1, characterized in that: The abnormality detection circuit is composed of a mirror circuit, a transistor, a resistor Rs, a comparator and a pulse statistics circuit. The current generated by the resistive random access memory is obtained by mirroring the mirror circuit. The current flows through the transistor to the resistor Rs, and a voltage Vs is generated at the same time. The voltage Vs and the preset voltage Vp are respectively input to the two input ends of the comparator. The output end of the comparator outputs high and low level pulses. The pulse statistics circuit detects the change of the current according to the high and low level pulses, and determines whether the resistive random access memory is in an abnormal state according to the change of the current.

3. A method for improving the reliability test efficiency of a resistive random access memory as claimed in claim 2, characterized in that: When the abnormality detection circuit determines that the resistive memory is in an abnormal state, the abnormality detection circuit reads the window size of the resistive memory in real time. If the real-time read window size is greater than A times the defined window size W0, or less than B times the defined window size W0, the resistive memory is determined to be in an abnormal state, where A and B are numbers greater than 0, and A>B.

4. The method for improving the reliability test efficiency of a resistive random access memory according to claim 1, characterized in that: The method firstly presets the number of operations, then cyclically performs the first operation and the second operation on the resistive random access memory, and performs the first composite operation and the second composite operation once every specified number of times, wherein the specified number of times is greater than or equal to the minimum number of preset operation times and less than the maximum number of preset operation times, specifically comprising the following steps: Step S1: For the 1st to K1th times, the first operation and the second operation are cyclically performed on the resistive random access memory, and the first combined operation and the second combined operation are performed once every N0 times, where N0 is an integer greater than 0 and less than K1; Step S2: From K1 to K2 times, the first operation and the second operation are cyclically performed on the resistive random access memory, and the first combined operation and the second combined operation are performed once every N1 times, where N1 is an integer greater than N0 and less than K2; Step S3: From K2 to K3 times, cyclically executing the first operation and the second operation on the resistive random access memory, and executing the first combined operation and the second combined operation once every N2 times, wherein N2 is an integer greater than N1 and less than K3; Step S4: For the K3-K4th time, the first operation and the second operation are cyclically performed on the resistive random access memory, and the first combined operation and the second combined operation are performed once every N3 times, where N3 is an integer greater than N2 and less than K4; Step S5: For the K4-K5th time, the first operation and the second operation are cyclically performed on the resistive random access memory, and the first combined operation and the second combined operation are performed once every N4 times, where N4 is an integer greater than N3 and less than K5; And so on.

5. A device for improving the reliability test efficiency of a resistive random access memory using the method according to any one of claims 1 to 4, comprising a resistive random access memory, a read / write operation circuit and an abnormality detection circuit connected to each other, characterized in that: The read / write operation circuit performs read / write operations on the resistive memory, and the abnormality detection circuit detects the resistive memory and determines whether it is in an abnormal state. When it is in an abnormal state, the read / write operation circuit performs abnormal read / write operations on the resistive memory, and when it is in a normal state, the read / write operation circuit performs normal read / write operations on the resistive memory; The abnormality detection circuit includes a mirror circuit, a transistor, a resistor Rs, a comparator and a pulse statistics circuit, one end of the mirror circuit is connected to the resistive memory to obtain the current generated by the resistive memory, the other end is connected to the first end of the transistor, the second end of the transistor is connected to the power supply end, the third end of the transistor is connected to one end of the resistor Rs and then connected to the first input end of the comparator, the other end of the resistor Rs is grounded, the second input end of the comparator is connected to a preset external voltage Vp, and the output end of the comparator is connected to the pulse statistics circuit; The current of the resistive memory is mirrored by the current mirror circuit and then flows through the transistor to the resistor Rs, generating a voltage Vs at the same time. The voltage Vs and the preset voltage Vp are respectively input to the two input ends of the comparator. The output end of the comparator outputs high and low level pulses. The pulse statistics circuit detects the change of the current based on the high and low level pulses, and determines whether the resistive memory is in an abnormal state based on the change of the current.

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