Method and device for monitoring abnormal communication of I2C bus, and I2C master device

Abstract

The present application discloses a method and device for monitoring abnormal communication of an I2C bus, and an I2C master device, wherein the I2C bus is connected with a master device and at least one slave device, and the method comprises: obtaining a clock signal sent by the master device to the slave device; obtaining a feedback signal corresponding to the clock signal on SCL; and determining the abnormal device by comparing the clock signal and the feedback signal. The present application scheme can quickly and accurately locate the abnormal device on the I2C bus.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to a method and device for monitoring abnormal communication of an I2C bus, and an I2C master device. Background Art

[0002] The I2C (Inter-Integrated Circuit) bus is a simple, bidirectional, two-wire synchronous serial bus that is widely used in low-speed communication scenarios. I2C communication works in a master-slave mode, usually with one master device communicating with multiple slave devices. The I2C bus uses SCL (Serial Clock Line) and SDA (Serial Data Address) to connect and communicate with slave devices. The basic architecture of the I2C bus system is as follows: Figure 1 As shown, it includes a master device and N slave devices.

[0003] In the prior art, when communication anomalies occur on the I2C bus, the device is usually disassembled to remove the slave devices on the I2C bus one by one to rule out which slave device is abnormal. When all slave devices are removed and the bus is still abnormal, it is indirectly proved that the master device is abnormal. This method cannot intuitively find the problem and requires disassembling the device to locate the problem point, which is time-consuming and laborious. Summary of the invention

[0004] The embodiments of the present application provide a method and apparatus for monitoring I2C bus communication anomalies, and an I2C master device, so as to quickly and accurately locate abnormal devices on the I2C bus.

[0005] In order to solve the above technical problems, the embodiments of the present application provide the following technical solutions:

[0006] On the one hand, an embodiment of the present application provides a method for monitoring I2C bus communication abnormalities, wherein a master device and at least one slave device are connected to the I2C bus, and the method includes:

[0007] Get the clock signal sent by the master device to the slave device;

[0008] Obtaining a feedback signal corresponding to the clock signal on SCL;

[0009] An abnormal device is determined by comparing the clock signal and the feedback signal.

[0010] Optionally, the feedback signal is delayed by a certain period compared to the clock signal.

[0011] Optionally, determining the abnormal device by comparing the clock signal and the feedback signal includes: if the feedback signal is 0 when the clock signal is 1 and lasts for a certain period of time, determining that the slave device is abnormal.

[0012] Optionally, the method further includes: if the delayed signal of the clock signal is consistent with the clock signal but remains unchanged for a certain period of time, determining that the master device is abnormal.

[0013] Optionally, the method further includes: generating an interrupt signal when a device abnormality is detected; and controlling I2C bus communication according to the interrupt signal.

[0014] Optionally, controlling the I2C bus communication according to the interrupt signal includes: reading the interrupt signal when the I2C bus communication is abnormal; resetting the master device if the interrupt signal indicates that the master device is abnormal; and ending the communication if the interrupt signal indicates that the slave device is abnormal.

[0015] On the other hand, an embodiment of the present application further provides a device for monitoring abnormal communication of an I2C bus, wherein a master device and at least one slave device are connected to the I2C bus, and the device comprises:

[0016] A clock signal acquisition module, used to acquire the clock signal sent by the master device to the slave device;

[0017] A feedback signal acquisition module, used to acquire a feedback signal corresponding to the clock signal on SCL;

[0018] The first judgment module is used to determine an abnormal device by comparing the clock signal and the feedback signal.

[0019] Optionally, the feedback signal is delayed by a certain period compared to the clock signal.

[0020] Optionally, the first judgment module is specifically used to determine that the slave device is abnormal when the feedback signal is 0 and lasts for a certain period of time when the clock signal is 1.

[0021] Optionally, the first judgment module includes: a first delayer, an inverter, a first AND gate, and a first timer; the first AND gate has three input terminals, one of which is input with an I2C working state signal, and the other two input terminals are respectively connected with an output terminal of the first delayer and an output terminal of the inverter, and the output terminal of the first AND gate is connected with an input terminal of the first timer; the output terminal of the first AND gate is connected with an input terminal of the first timer;

[0022] The first delay device is used to input the clock signal;

[0023] The inverter is used to input the feedback signal;

[0024] The first AND gate is used to output a high level when the clock signal is 1 and the feedback signal is 0, so as to trigger the first timer to start timing;

[0025] The first timer is used to output a slave device abnormality indication signal after the timing time reaches a set first duration.

[0026] Optionally, the apparatus further comprises: a second judgment module, configured to determine that the master device is abnormal when the delay signal of the clock signal is consistent with the clock signal but remains unchanged for a certain period of time.

[0027] Optionally, the second judgment module includes: a second delayer, an XOR gate, a second AND gate, and a second timer; the output end of the second delayer is connected to an input end of the XOR gate; the clock signal is input to the other input end of the XOR gate; the second AND gate has two input ends, one of which is input with an I2C working status signal, and the other is connected with the output end of the XOR gate; the output end of the second AND gate is connected to the input end of the second timer;

[0028] The second delay device is used to input the clock signal;

[0029] The second AND gate is used for outputting a high level when the feedback signal is consistent with the clock signal, so as to trigger the second timer to start timing;

[0030] The second timer is used to output a master device abnormality indication signal after the timing time reaches a set second time period.

[0031] Optionally, the slave device abnormality indication signal and the master device abnormality indication signal are interrupt signals; the apparatus further comprises: a control module, configured to control I2C bus communication according to the interrupt signal.

[0032] Optionally, the control module is specifically configured to read the interrupt signal when the I2C bus communication is abnormal, and reset the master device if the interrupt signal indicates that the master device is abnormal; and terminate the communication if the interrupt signal indicates that the slave device is abnormal.

[0033] On the other hand, an embodiment of the present application further provides an I2C master device, which includes the aforementioned apparatus for monitoring I2C bus communication abnormalities.

[0034] On the other hand, an embodiment of the present application further provides a computer-readable storage medium, which is a non-volatile storage medium or a non-transient storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the method described above is executed.

[0035] On the other hand, an embodiment of the present application also provides a device for monitoring I2C bus communication anomalies, including a memory and a processor, wherein the memory stores a computer program that can be executed on the processor, and when the processor runs the computer program, the method described above is executed.

[0036] The method and apparatus for monitoring I2C bus communication anomalies and the I2C master device provided in the embodiments of the present application can determine the abnormal device by obtaining a clock signal sent by the master device to the slave device and obtaining a feedback signal corresponding to the clock signal on SCL, and then comparing the clock signal and the feedback signal.

[0037] Furthermore, the abnormal device may be determined by comparing the delayed signal of the clock signal with the clock signal.

[0038] The solution provided by the embodiment of the present application does not require disassembling the devices on the I2C bus, and can simply, conveniently and quickly accurately locate whether the master device or the slave device has an abnormality, thereby facilitating the troubleshooting of abnormal situations in the I2C bus system. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 This is a basic architecture diagram of the existing I2C bus system;

[0040] Figure 2 It is a schematic diagram of the principle of the method for monitoring I2C bus communication abnormality according to an embodiment of the present application;

[0041] Figure 3 This is a flow chart of a method for monitoring I2C bus communication abnormalities according to an embodiment of the present application;

[0042] Figure 4 is a flow chart of controlling I2C bus communication according to an interrupt signal in an embodiment of the present application;

[0043] Figure 5 It is a structural schematic diagram of a device for monitoring I2C bus communication abnormality according to an embodiment of the present application;

[0044] Figure 6 It is a structural schematic diagram of a first judgment module in the device for monitoring I2C bus communication abnormality in an embodiment of the present application;

[0045] Figure 7 It is a structural schematic diagram of a second judgment module in the device for monitoring I2C bus communication abnormality in an embodiment of the present application;

[0046] Figure 8 This is another structural schematic diagram of the device for monitoring I2C bus communication abnormalities according to an embodiment of the present application. DETAILED DESCRIPTION

[0047] In order to make the above-mentioned purposes, features and beneficial effects of the present application more obvious and easy to understand, the specific embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0048] In view of the problem in the prior art that it is impossible to simply and quickly locate the abnormal device on the I2C bus after an abnormality occurs on the I2C bus, the embodiments of the present application provide a method and apparatus for monitoring I2C bus communication abnormalities, and an I2C master device, by obtaining a clock signal sent by the master device to the slave device and a feedback signal corresponding to the clock signal from SCL, and then determining the abnormal device by comparing the clock signal and the feedback signal.

[0049] like Figure 2 , which is a schematic diagram of the principle of the method for monitoring I2C bus communication anomalies according to an embodiment of the present application.

[0050] A logic circuit 21 is provided in the master device, and the logic circuit 21 is connected to SCL.

[0051] like Figure 2 As shown, the logic circuit 21 has two ports, namely, an OUT port and an IN port, wherein the OUT port is an output port and the IN port is an input port.

[0052] The output terminal OUT of the logic circuit 21 is connected to SCL at the connection point OE, and the input terminal IN of the logic circuit 21 is connected to SCL at the pin pad. The SCL clock signal is driven by the master device and sent to the slave device. The clock signal is output at the output terminal OUT of the logic circuit 21, the clock signal on SCL is monitored at the input terminal IN of the logic circuit 21, and the feedback signal corresponding to the clock signal is captured at the input terminal IN, which can also be called a monitoring signal. Usually, the feedback signal can be delayed by N clock cycles (N is generally 1-2) than the clock signal output from the output terminal OUT through corresponding timing control.

[0053] Since the clock signal outputted by the output terminal OUT of the logic circuit 21 is known, it can be compared with the feedback signal monitored by the input terminal IN, and it can be determined whether there is any abnormality in a device on the I2C bus according to the comparison result.

[0054] Specifically, the internal control logic of the logic circuit 21 compares the clock signal output by the output terminal OUT with the feedback signal obtained by the input terminal IN. If the output of the output terminal OUT is 1, but the feedback signal monitored by the input terminal IN is 0 and lasts for a certain period of time, it indicates that the master device is normal and the slave device abnormally pulls down the bus. Furthermore, if the delay signal of the clock signal output by OUT is consistent with the clock signal, but remains 1 or 0 for a long time, it indicates that the master device is abnormal.

[0055] Based on the above principle, a flow chart of a method for monitoring I2C bus communication abnormality provided in an embodiment of the present application is as follows: Figure 3 As shown, the following steps are included:

[0056] Step 301, obtaining a clock signal sent by a master device to a slave device.

[0057] Step 302: Obtain a feedback signal on SCL corresponding to the clock signal.

[0058] It should be noted that, through corresponding timing control, the feedback signal can be delayed by a certain period than the clock signal, for example, by 1-2 clock cycles. In other words, the feedback signal refers to the monitoring signal collected on SCL after a certain period of delay after the master device sends the clock signal.

[0059] In the embodiment of the present application, the clock signal is a clock signal sent by the master device and transmitted on SCL. The feedback signal corresponding to the clock signal refers to the signal on SCL monitored after the master device sends the clock signal. In other words, the clock signal is actually sent by the master device, and the feedback signal is the actual signal on SCL after a certain period of delay after the master device sends the clock signal.

[0060] Step 303: Determine the abnormal device by comparing the clock signal and the feedback signal.

[0061] If both the master and slave devices are normal, the feedback signal should be consistent with the clock signal, but if the slave device is abnormal, the feedback signal should be inconsistent with the clock signal. Specifically, the clock signal sent by the master device to the slave device and the feedback signal corresponding to the clock signal on SCL are compared. If the feedback signal is 0 when the clock signal is 1 and lasts for a certain period of time (usually seconds, such as 2-3 seconds), it is determined that the slave device is abnormal.

[0062] Further, in another non-limiting embodiment of the method for monitoring I2C bus communication abnormality of the present application, the abnormal device can also be determined by comparing the delayed signal of the clock signal with the clock signal. Specifically, if the delayed signal of the clock signal is consistent with the clock signal but remains unchanged for a certain period of time (for example, 2-3 clock cycles), it is determined that the master device is abnormal.

[0063] It should be noted that the delayed signal may be delayed by a certain clock cycle than the clock signal, for example, by 1-2 clock cycles.

[0064] Furthermore, if the slave device is abnormal, it is also possible to determine which slave device is abnormal based on the slave device address stored in the current register.

[0065] The method for monitoring I2C bus communication abnormality provided in the embodiment of the present application can quickly determine whether there is an abnormal slave device on the I2C bus by acquiring the clock signal sent by the master device to the slave device and monitoring the feedback signal corresponding to the clock signal transmitted on SCL. Furthermore, it can also be determined whether the master device is abnormal by comparing the delayed signal of the clock signal with the clock signal.

[0066] In another non-limiting embodiment of the method for monitoring I2C bus communication anomalies of the present application, an interrupt signal may be generated when an abnormal device on the I2C is detected, and the I2C bus communication may be controlled according to the interrupt signal.

[0067] like Figure 4 , which is a flow chart of controlling I2C bus communication according to an interrupt signal in an embodiment of the present application, including the following steps:

[0068] Step 401: The master device and the slave device start communicating.

[0069] Step 402, determine whether the I2C bus communication is normal. If normal, execute step 403; otherwise, execute step 404.

[0070] Step 403: Perform normal communication.

[0071] Step 404, read the interrupt signal, and determine the abnormal device according to the interrupt signal. If the slave device is abnormal, execute step 405; if the master device is abnormal, execute step 406.

[0072] Step 405, end the communication.

[0073] Step 406, reset the master device, and then return to step 401.

[0074] In a specific application, the master device may be reset multiple times. If the master device is still detected to be abnormal after multiple resets, it indicates that the abnormality of the master device cannot be eliminated by the reset operation. In this case, the communication may be terminated and the master device may be checked by other means.

[0075] It should be noted that, in specific applications, the method for monitoring I2C bus communication abnormalities in the above embodiment of the present application can be implemented by combining hardware and software. For example, the above interrupt signal is written into an interrupt register, and the interrupt register is read to determine whether there is a device abnormality, and whether it is a master device abnormality or a slave device abnormality.

[0076] Accordingly, the embodiment of the present application also provides a device for monitoring I2C bus communication abnormalities, such as Figure 5 , which is a schematic diagram of the structure of a device for monitoring I2C bus communication abnormalities according to an embodiment of the present application.

[0077] In this embodiment, the device 500 includes a clock signal acquisition module 501, a feedback signal acquisition module 502, and a first judgment module 503. Wherein:

[0078] The clock signal acquisition module 501 is used to acquire the clock signal sent by the master device to the slave device;

[0079] The feedback signal acquisition module 502 is used to acquire a feedback signal corresponding to the clock signal on SCL;

[0080] The first judgment module 503 is used to determine an abnormal device by comparing the clock signal and the feedback signal. Specifically, when the feedback signal is 0 when the clock signal is 1 and lasts for a certain period of time, it is determined that the slave device is abnormal.

[0081] Further, in another non-limiting embodiment of the device for monitoring I2C bus communication abnormality in the present application, the device may also include: a second judgment module (see below) Figure 8 The embodiment shown in the figure is used to determine that the main device is abnormal when the delayed signal of the clock signal is consistent with the clock signal but remains unchanged for a certain period of time.

[0082] In the embodiment of the present application, the first judgment module 503 can determine whether there is an abnormality in a slave device on the I2C bus based on the comparison of the clock signal and the corresponding feedback signal. After determining that the slave device is abnormal, it is also possible to further locate which slave device is abnormal. For example, the slave device address stored in the current register can be read by software to determine which slave device is abnormal. Of course, other judgment methods in the prior art can also be used, which are not limited in the embodiment of the present application.

[0083] The first judgment module 503 may be implemented by pure hardware. For example, in a non-limiting embodiment, the first judgment module 503 is used to determine that the slave device is abnormal when the feedback signal is 0 and lasts for a certain period of time when the clock signal is 1.

[0084] Combine the following Figure 6 and Figure 7 The working principles of the first judgment module and the second judgment module in the embodiment of the present application are described in detail.

[0085] like Figure 6 , which is a structural diagram of a first judgment module in a device for monitoring I2C bus communication abnormalities according to an embodiment of the present application.

[0086] In this embodiment, the first judgment module includes: a first delayer 61, an inverter 62, a first AND gate 63, and a first timer 64. The first AND gate 63 has three input terminals, one of which inputs the I2C working state signal, and the other two input terminals are respectively connected to the output terminal of the first delayer 61 and the output terminal of the inverter 62, and the output terminal of the first AND gate 63 is connected to the input terminal of the first timer 64; the output terminal of the first AND gate 63 is connected to the input terminal of the first timer 64.

[0087] in:

[0088] The first delay device 61 is used to input the clock signal;

[0089] The inverter 62 is used to input the feedback signal;

[0090] The first AND gate 63 is used to output a high level when the clock signal is 1 and the feedback signal is 0, so as to trigger the first timer 64 to start timing;

[0091] The first timer 64 is used to output a slave device abnormality indication signal after the timing time reaches a set first duration.

[0092] The I2C working status signal is Figure 6 The I2C_busy signal in the I2C bus is used to indicate that the I2C bus is in working state, which is different from the I2C idle state signal, that is, the master device and the slave device on the I2C bus are communicating. The present application scheme will only detect whether there is an abnormality in the device on the I2C bus when the I2C is in working state.

[0093] It should be noted that, in a specific application, when the I2C bus is in a working state, the I2C_busy signal can be set to 1, and when the I2C bus is in an idle state, the I2C_busy signal can be set to 0.

[0094] Reference Figure 6 , the working logic of the first judgment module is as follows:

[0095] The I2C bus is in a busy state, that is, the I2C bus is working. Since the IN signal (that is, the feedback signal) is delayed by 1-2 clock cycles compared to the OUT signal (that is, the clock signal), the OUT signal is delayed by 1-2 clock cycles to match the IN signal. Then the IN signal and the OUT signal are compared. When the OUT signal output is 1, the IN signal is detected to be 0, which triggers the first timer 64 to start timing. When the set time is reached (the time is set by the chip manufacturer according to actual conditions, such as 2S), it is judged that the slave device is abnormal, and the first timer 64 outputs a slave device abnormality indication signal.

[0096] like Figure 7 , which is a structural diagram of a second judgment module in the device for monitoring I2C bus communication abnormalities according to an embodiment of the present application.

[0097] In this embodiment, the second judgment module includes: a second delayer 71, an XOR gate 72, a second AND gate 74, and a second timer 75. The output end of the second delayer 71 is connected to one input end of the XOR gate 72; the other input end of the XOR gate 72 inputs the clock signal; the second AND gate 74 has two input ends, one of which inputs the I2C working status signal, and the other input end is connected to the output end of the XOR gate 72; the output end of the second AND gate 74 is connected to the input end of the second timer 75.

[0098] The second delay device 71 is used to input the clock signal;

[0099] The second AND gate 74 is used to output a high level when the feedback signal is consistent with the clock signal, so as to trigger the second timer 75 to start timing;

[0100] The second timer 75 is used to output a master device abnormality indication signal after the timing time reaches a set second time period.

[0101] Reference Figure 7 , the working logic of the second judgment module is as follows:

[0102] The I2C bus is in a busy state, that is, the I2C bus is working. The OUT signal is compared to see if it is consistent with the signal before and after one clock cycle. Because the SCL signal is a periodic 0 / 1 jump, as long as it is delayed for one clock cycle and monitored to be consistent with the signal one cycle ago, the second timer 75 is triggered to start timing. After the set time (for example, the time can be set to 2-3 cycles), it is determined that the master device is abnormal, and the second timer 75 outputs a master device abnormality indication signal.

[0103] It should be noted that the timing durations of the first timer 64 and the second timer 75, that is, the first duration and the second duration mentioned above, can be set to be the same or different, and this embodiment of the present application does not limit this.

[0104] In addition, it should be noted that in order to enable the first timer 64 and the second timer 75 to be reset after reaching the timing duration so as to continue to detect the subsequent signals. Figure 6 and Figure 7 As shown in FIG. 1 , the first timer 64 and the second timer 75 are reset by corresponding reset inverters 60 and 70 , respectively.

[0105] like Figure 8 , which is another structural schematic diagram of the device for monitoring I2C bus communication abnormalities according to an embodiment of the present application.

[0106] and Figure 5 What is different from the illustrated embodiment is that, in this embodiment, the device 500 further includes a second determination module 505 and a control module 504 .

[0107] In this embodiment, the slave device abnormality indication signal and the master device abnormality indication signal are interrupt signals, and the interrupt signals are generated by the first judgment module 503 and the second judgment module 505. For example, when the first judgment module 503 determines that the slave device is abnormal, it outputs a corresponding signal to the first I / O port of the control module 504; similarly, when the second judgment module 505 determines that the master device is abnormal, it outputs a corresponding signal to the second I / O port of the control module 504. The first I / O port and the second I / O port do not refer to specific I / O ports, but are only used to distinguish the two as different I / O ports.

[0108] Correspondingly, the control module 504 is used to control the I2C bus communication according to the interrupt signal. Specifically, the interrupt signal is read when the I2C bus communication is abnormal. If the interrupt signal indicates that the master device is abnormal, the master device is reset; if the interrupt signal indicates that the slave device is abnormal, the communication is terminated.

[0109] It should be noted that the control module 504 can repeat the reset operation of the master device multiple times (generally less than 5 times). For example, the control module 504 forcibly resets the master device through software, and notifies the upper-layer caller to re-initiate communication, and then continue communication; if the communication is abnormal again, continue to read the interruption situation, if the master device is still abnormal, continue to reset the master device and notify the upper-layer caller to re-initiate communication, and then continue communication; if the master device is always abnormal, the software will forcibly reset the master device N times (N times is generally less than 5 times); if it is detected again that the master device is abnormal, the communication is terminated.

[0110] In a specific application, the apparatus for monitoring I2C bus communication abnormalities according to the embodiment of the present application may be disposed in a master device.

[0111] The device for monitoring I2C bus communication abnormalities provided in the embodiment of the present application can quickly determine whether there is an abnormal device on the I2C bus by acquiring the clock signal sent by the master device to the slave device and monitoring the feedback signal corresponding to the clock signal transmitted on SCL. Furthermore, the abnormal device can be determined by comparing the delayed signal of the clock signal with the clock signal, thereby facilitating the troubleshooting of abnormal conditions in the I2C bus system.

[0112] The solution provided by the embodiment of the present application does not require disassembling the devices on the I2C bus, and can simply, conveniently and quickly accurately locate whether the master device or the slave device has an abnormality, thereby facilitating the troubleshooting of abnormal situations in the I2C bus system.

[0113] In a specific implementation, the above-mentioned device for monitoring I2C bus communication anomalies may correspond to a chip with corresponding functions in a terminal device, such as a SOC (System-On-a-Chip), a baseband chip, a chip module, etc.

[0114] In a specific implementation, each module / unit included in each device or product described in the above embodiments may be a software module / unit or a hardware module / unit, or may be partly a software module / unit and partly a hardware module / unit.

[0115] For example, for each device or product applied to or integrated in a chip, each module / unit contained therein may be implemented in the form of hardware such as circuits, or at least some of the modules / units may be implemented in the form of software programs, which run on a processor integrated inside the chip, and the remaining (if any) modules / units may be implemented in the form of hardware such as circuits; for each device or product applied to or integrated in a chip module, each module / unit contained therein may be implemented in the form of hardware such as circuits, and different modules / units may be located in the same component (such as a chip, circuit module, etc.) or different components of the chip module, or at least some of the modules / units may be implemented in the form of software programs. The element can be implemented in the form of a software program, which runs on a processor integrated inside the chip module, and the remaining (if any) modules / units can be implemented in the form of hardware such as circuits; for various devices and products applied to or integrated in the terminal, the various modules / units contained therein can be implemented in the form of hardware such as circuits, and different modules / units can be located in the same component (for example, chip, circuit module, etc.) or in different components in the terminal, or, at least some modules / units can be implemented in the form of a software program, which runs on a processor integrated inside the terminal, and the remaining (if any) modules / units can be implemented in the form of hardware such as circuits.

[0116] Correspondingly, an embodiment of the present application further provides an I2C master device, which includes the aforementioned apparatus for monitoring I2C bus communication abnormalities.

[0117] Accordingly, an embodiment of the present application also provides a computer-readable storage medium, which is a non-volatile storage medium or a non-transient storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps in the above-mentioned method embodiments are executed.

[0118] Correspondingly, an embodiment of the present application also provides a device for monitoring I2C bus communication anomalies, including a memory and a processor, wherein the memory stores a computer program that can be executed on the processor, and the processor executes the steps in the above-mentioned method embodiments when running the computer program.

[0119] It should be understood that the term "and / or" in this article is only a description of the association relationship of the associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article indicates that the associated objects before and after are in an "or" relationship.

[0120] The "plurality" appearing in the embodiments of the present application refers to two or more.

[0121] The first, second, etc. descriptions appearing in the embodiments of the present application are only used for illustration and distinction of the description objects. There is no order, nor do they indicate any special limitation on the number of devices in the embodiments of the present application, and cannot constitute any limitation on the embodiments of the present application.

[0122] The various embodiments provided in this application can be implemented in whole or in part by software, hardware, firmware or any other combination. When implemented using software, the above embodiments can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions or computer programs. When the computer instructions or computer programs are loaded or executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website site, a computer, a server or a data center to another website site, a computer, a server or a data center by wired or wireless means. It should be understood that in various embodiments of the present application, the size of the sequence number of the above-mentioned processes does not mean the order of execution, and the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiment of the present application.

[0123] In the several embodiments provided in the present application, it should be understood that the disclosed methods, devices and systems can be implemented in other ways. For example, the device embodiments described above are merely schematic; for example, the division of the units is only a logical function division, and there may be other division methods in actual implementation; for example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0124] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0125] In addition, each functional unit in each embodiment of the present application can be integrated into one processing unit, or each unit can be physically arranged separately, or two or more units can be integrated into one unit. The above integrated unit can be implemented in the form of hardware or in the form of hardware plus software functional units.

[0126] Although the present application is disclosed as above, the present application is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the protection scope of the present application shall be subject to the scope defined by the claims.

Claims

1. A method for monitoring abnormal communication of an I2C bus, wherein the I2C bus is connected to a master device and at least one slave device, characterized in that: The method comprises: Get the clock signal sent by the master device to the slave device; Obtaining a feedback signal corresponding to the clock signal on the clock signal line SCL; Determining an abnormal device by comparing the clock signal and the feedback signal specifically includes: if the feedback signal is 0 when the clock signal is 1 and lasts for a certain period of time, determining that the slave device is abnormal.

2. The method according to claim 1, characterized in that The feedback signal is delayed by a certain period compared to the clock signal.

3. The method according to claim 1, characterized in that The method further comprises: If the delayed signal of the clock signal is consistent with the clock signal but remains unchanged for a certain period of time, it is determined that the master device is abnormal.

4. The method according to any one of claims 1 to 3, characterized in that: The method further comprises: When a device abnormality is detected, an interrupt signal is generated; The I2C bus communication is controlled according to the interrupt signal.

5. The method according to claim 4, characterized in that The controlling of the I2C bus communication according to the interrupt signal comprises: Reading the interrupt signal when I2C bus communication is abnormal; If the interrupt signal indicates that the master device is abnormal, the master device is reset; if the interrupt signal indicates that the slave device is abnormal, the communication is terminated.

6. A device for monitoring abnormal communication of an I2C bus, wherein the I2C bus is connected to a master device and at least one slave device, characterized in that: The device comprises: A clock signal acquisition module, used to acquire the clock signal sent by the master device to the slave device; A feedback signal acquisition module, used to acquire a feedback signal corresponding to the clock signal on the clock signal line SCL; The first judgment module is used to determine the abnormal device by comparing the clock signal and the feedback signal, specifically including: when the clock signal is 1 and the feedback signal is 0 and lasts for a certain period of time, determining that the slave device is abnormal.

7. The device according to claim 6, characterized in that The feedback signal is delayed by a certain period compared to the clock signal.

8. The device according to claim 6, characterized in that The first judgment module includes: a first delayer, an inverter, a first AND gate, and a first timer; the first AND gate has three input terminals, one of which is input with an I2C working state signal, and the other two input terminals are respectively connected with an output terminal of the first delayer and an output terminal of the inverter, and the output terminal of the first AND gate is connected with an input terminal of the first timer; the output terminal of the first AND gate is connected with an input terminal of the first timer; The first delay device is used to input the clock signal; The inverter is used to input the feedback signal; The first AND gate is used to output a high level when the clock signal is 1 and the feedback signal is 0, so as to trigger the first timer to start timing; The first timer is used to output a slave device abnormality indication signal after the timing time reaches a set first duration.

9. The device according to any one of claims 6 to 8, characterized in that The device also includes: The second judgment module is used to determine that the main device is abnormal when the delay signal of the clock signal is consistent with the clock signal but remains unchanged for a certain period of time.

10. The device according to claim 9, characterized in that The second judgment module includes: a second delayer, an XOR gate, a second AND gate, and a second timer; the output end of the second delayer is connected to an input end of the XOR gate; the clock signal is input to the other input end of the XOR gate; the second AND gate has two input ends, one of which is input with an I2C working status signal, and the other is connected with the output end of the XOR gate; the output end of the second AND gate is connected to the input end of the second timer; The second delay device is used to input the clock signal; The second AND gate is used for outputting a high level when the feedback signal is consistent with the clock signal, so as to trigger the second timer to start timing; The second timer is used to output a master device abnormality indication signal after the timing time reaches a set second time period.

11. The device according to claim 10, characterized in that The slave device abnormality indication signal and the master device abnormality indication signal are interrupt signals; the device further comprises: The control module is used to control the I2C bus communication according to the interrupt signal.

12. The device according to claim 11, characterized in that The control module is specifically used to read the interrupt signal when the I2C bus communication is abnormal, and reset the master device if the interrupt signal indicates that the master device is abnormal; if the interrupt signal indicates that the slave device is abnormal, end the communication.

13. An I2C master device, characterized in that: The device comprises the apparatus for monitoring I2C bus communication abnormalities as described in any one of claims 6 to 12.

14. A computer-readable storage medium, wherein the computer-readable storage medium is a non-volatile storage medium or a non-transient storage medium, and a computer program is stored thereon, wherein: When the computer program is executed by a processor, the method according to any one of claims 1 to 5 is performed.

15. A device for monitoring abnormal communication of an I2C bus, comprising a memory and a processor, wherein the memory stores a computer program that can be run on the processor, characterized in that: When the processor runs the computer program, the method according to any one of claims 1 to 5 is executed.

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