Test pad processing method and semiconductor device manufacturing method

Abstract

The present invention provides a test pad processing method and a method for preparing a semiconductor device, the test pad processing method comprising: providing a substrate, on which a first insulating dielectric layer and a first test pad located in the first insulating dielectric layer are formed, the first insulating dielectric layer exposes at least part of the surface of the first test pad, and the surface of the first test pad exposed by the first insulating dielectric layer is formed with a needle mark protrusion caused by a probe test; a laser annealing process is used to heat and melt the needle mark protrusion to reduce the height of the needle mark protrusion. The technical solution of the present invention can ensure that the bonding surface has good flatness while reducing the process difficulty and avoiding metal contamination of the bonding surface.

Description

Technical Field

[0001] The invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a test pad processing method and a semiconductor device preparation method. Background Art

[0002] In the 3D IC process, wafers or chips before stacking and bonding are allowed to be tested for yield using probes to reduce the yield loss of wafers or chips, especially when multiple wafers or multiple chips are stacked and bonded.

[0003] The melt bonding process and hybrid bonding process have extremely high requirements for the surface treatment of the bonded wafer or chip, which requires very good flatness. Wafers that have passed the yield test will leave probing marks on the test pads. The diameter of the probe marks is about 2μm to 20μm. The probe marks include depressions and protrusions on the surface of the test pads. The height of the protrusions exceeds the top surface of the insulating material layer around the test pads and can be as high as about 2μm, which seriously affects the flatness of the bonding surface.

[0004] Currently, methods to ensure that the bonding surface has good flatness include:

[0005] (1) See Figure 1a and Figure 1b , a first insulating material layer 11, a second insulating material layer 12 and a third insulating material layer 13 are stacked from bottom to top, a metal interconnection structure 14 is formed in the first insulating material layer 11, a first test pad 15 and a second test pad 16 are formed in the second insulating material layer 12 and the third insulating material layer 13, the first test pad 15 and the second test pad 16 are connected in parallel to form the metal interconnection structure 14, and the top surface of the first test pad 15 is exposed by the third insulating material layer 13, and the second test pad 16 is buried by the third insulating material layer 13; after a probe test, a needle mark is left on the surface of the first test pad 15, and the height of the protrusion D1 of the needle mark far exceeds the top surface of the third insulating material layer 13, the first test pad 15 exposed by the third insulating material layer 13 is removed by an etching process, so that the needle mark is removed, and after covering the fourth insulating material layer 17 on the third insulating material layer 13 and the position where the exposed first test pad 15 is removed, a conductive structure 18 is formed on the parallel second test pad 16 to connect the metal interconnection structure 14. This method requires designing two test pads in parallel, which makes wiring more difficult.

[0006] (2) See Figure 2a and Figure 2bThe first insulating material layer 21, the second insulating material layer 22 and the third insulating material layer 23 are stacked from bottom to top, a metal interconnection structure 24 is formed in the first insulating material layer 21, a test pad is formed in the second insulating material layer 22 and the third insulating material layer 23, the test pad is connected to the metal interconnection structure 24, the test pad includes a first metal layer 251 located in the second insulating material layer 22 and the third insulating material layer 23 and a second metal layer 252 located on the top surface of the first metal layer 251, and the top surface of the second metal layer 252 is covered by the third insulating material The material layer 23 is exposed; after the probe test, the needle mark is only located in the second metal layer 252, and the height of the protrusion D2 of the needle mark is far higher than the top surface of the third insulating material layer 23. The needle mark is removed by removing the exposed second metal layer 252, and the third metal layer 253 is regrown at the position where the second metal layer 252 is removed, and after the fourth insulating material layer 26 is covered on the third insulating material layer 23 and the third metal layer 253, a conductive structure 27 is formed on the third metal layer 253 to connect the metal interconnection structure 24. This method requires the test pad to be made into a structure of at least two layers, and it is necessary to control the removal of only the second metal layer 252, and the third metal layer 253 needs to be regrown after the second metal layer 252 is removed, resulting in a very complicated process and high cost.

[0007] Therefore, how to improve the existing method of ensuring that the bonding surface has good flatness is a problem that needs to be solved urgently. Summary of the invention

[0008] The object of the present invention is to provide a test pad processing method and a semiconductor device preparation method, which can ensure that the bonding surface has good flatness while reducing the process difficulty and avoiding metal contamination of the bonding surface.

[0009] To achieve the above object, the present invention provides a test pad processing method, comprising:

[0010] A substrate is provided, on which a first insulating dielectric layer and a first test pad located in the first insulating dielectric layer are formed, the first insulating dielectric layer exposes at least a portion of a surface of the first test pad, and a probe mark protrusion caused by a probe test is formed on the surface of the first test pad exposed by the first insulating dielectric layer;

[0011] The needle mark protrusion is heated and melted by a laser annealing process to reduce the height of the needle mark protrusion.

[0012] Optionally, the needle mark protrusion extends from the surface of the first test pad beyond the surface of the first insulating medium layer.

[0013] Optionally, the laser used in the laser annealing process is a monochromatic laser or a superposition of at least two monochromatic lasers.

[0014] Optionally, the laser annealing process is used to heat and melt the needle mark protrusion so that the needle mark protrusion is fused with the first test pad to remove the needle mark protrusion.

[0015] Optionally, the energy density of the laser used in the laser annealing process is such that the heating temperature at least reaches the melting point of the material of the first test pad.

[0016] Optionally, the first test pad is made of a metal alloy including aluminum and copper, and the heating temperature is 600°C to 700°C.

[0017] Optionally, the laser annealing process adopts surface spot continuous irradiation or point scanning irradiation, and the irradiation area does not exceed the first test pad exposed by the first insulating dielectric layer.

[0018] Optionally, the temperature of the bottom surface of the first test pad is not higher than 500°C.

[0019] Optionally, after the needle mark protrusion is heated and melted by laser annealing, the test pad processing method further comprises: cleaning the surface of the first test pad.

[0020] The present invention also provides a method for preparing a semiconductor device, comprising:

[0021] A substrate is provided, on which a first insulating dielectric layer and a first test pad located in the first insulating dielectric layer are formed, the first insulating dielectric layer exposes at least a portion of a surface of the first test pad, and a probe mark protrusion caused by a probe test is formed on the surface of the first test pad exposed by the first insulating dielectric layer;

[0022] Using a laser annealing process to heat and melt the needle mark protrusion to reduce the height of the needle mark protrusion;

[0023] forming a second insulating dielectric layer covering the first test pad and the first insulating dielectric layer;

[0024] A planarization process is performed on the second insulating dielectric layer, and the reduced height of the needle mark protrusion is lower than the surface of the second insulating dielectric layer after the planarization process.

[0025] Optionally, the laser annealing process is used to heat and melt the needle mark protrusion so that the needle mark protrusion is fused with the first test pad to remove the needle mark protrusion.

[0026] Optionally, a metal interconnect structure is formed in the first insulating dielectric layer, and the bottom of the first test pad is electrically connected to the metal interconnect structure; the method for preparing the semiconductor device further includes:

[0027] A wafer or a chip is provided, and a surface of the second insulating medium layer away from the substrate is bonded to the wafer or the chip.

[0028] Optionally, after performing a planarization process on the second insulating dielectric layer and before bonding a side of the second insulating dielectric layer away from the substrate to the wafer or the chip, the method for preparing the semiconductor device further comprises:

[0029] forming a conductive structure in the second insulating dielectric layer, wherein the conductive structure is electrically connected to the first test pad;

[0030] Alternatively, after bonding the side of the second insulating dielectric layer away from the substrate to the wafer or the chip, the method for preparing the semiconductor device further comprises:

[0031] A conductive structure is formed that penetrates the wafer or the chip and extends into the second insulating medium layer, and the conductive structure is electrically connected to the first test pad.

[0032] Optionally, a second test pad is further formed in the first insulating dielectric layer, and a bottom of the second test pad is electrically connected to the metal interconnect structure; after performing a planarization process on the second insulating dielectric layer and before bonding a side of the second insulating dielectric layer away from the substrate to the wafer or the chip, the method for preparing the semiconductor device further includes:

[0033] forming a conductive structure penetrating the second insulating dielectric layer and extending to the first insulating dielectric layer, wherein the conductive structure is electrically connected to the second test pad;

[0034] Alternatively, after bonding the side of the second insulating dielectric layer away from the substrate to the wafer or the chip, the method for preparing the semiconductor device further comprises:

[0035] A conductive structure is formed which penetrates the wafer or the chip and the second insulating dielectric layer and extends into the first insulating dielectric layer, and the conductive structure is electrically connected to the second test pad.

[0036] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0037] 1. The test pad processing method of the present invention uses a laser annealing process to heat and melt the needle mark protrusion caused by the probe test formed on the surface of the first test pad exposed by the first insulating dielectric layer, so that the height of the needle mark protrusion is reduced, thereby ensuring that the bonding surface has good flatness while reducing the process difficulty, improving the processing efficiency and reducing the cost.

[0038] 2. In the method for preparing a semiconductor device of the present invention, a laser annealing process is used to heat and melt the needle mark protrusion caused by the probe test formed on the surface of the first test pad exposed by the first insulating dielectric layer, so that the height of the needle mark protrusion is reduced to be lower than the surface of the second insulating dielectric layer after the flattening process, thereby ensuring that the bonding surface has good flatness, reducing the process difficulty and avoiding metal contamination on the bonding surface. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1a to Figure 1b A schematic diagram of a device in a method for ensuring that the bonding surface has good flatness;

[0040] Figure 2a to Figure 2b It is a schematic diagram of a device in another method of ensuring that the bonding surface has good flatness;

[0041] Figure 3 is a flow chart of a test pad processing method according to an embodiment of the present invention;

[0042] Figure 4a to Figure 4d yes Figure 3 A schematic diagram of a device in a test pad processing method shown;

[0043] Figure 5a to Figure 5b FIG. 1 is a schematic diagram of a parallel test pad connected to a metal interconnect structure according to an embodiment of the present invention.

[0044] Among them, Figure 1a to Figure 5b The reference numerals are described as follows:

[0045] 11-first insulating material layer; 12-second insulating material layer; 13-third insulating material layer; 14-metal interconnection structure; 15-first test pad; 16-second test pad; 17-fourth insulating material layer; 18-conductive structure; 21-first insulating material layer; 22-second insulating material layer; 23-third insulating material layer; 24-metal interconnection structure; 251-first metal layer; 252-second metal layer; 253-third metal layer; 26-fourth insulating material layer; 27-conductive structure; 31-first insulating dielectric layer; 311-first insulating material layer; 312-second insulating material layer; 313-third insulating material layer; 32-first test pad; 321-first conductive plug; 322-first pad; 33-metal interconnection structure; 331-second conductive plug; 332-metal line; 34-second insulating dielectric layer; 35-conductive structure; 36-second test pad. DETAILED DESCRIPTION

[0046] In order to make the purpose, advantages and features of the present invention more clear, the test pad processing method and the semiconductor device manufacturing method proposed by the present invention are further described in detail below in conjunction with the accompanying drawings. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0047] An embodiment of the present invention provides a test pad processing method, referring to Figure 3 , Figure 3 is a flow chart of a test pad processing method according to an embodiment of the present invention, the test pad processing method comprising:

[0048] Step S11, providing a substrate, on which a first insulating dielectric layer and a first test pad located in the first insulating dielectric layer are formed, the first insulating dielectric layer exposes at least a portion of a surface of the first test pad, and a probe mark protrusion caused by a probe test is formed on the surface of the first test pad exposed by the first insulating dielectric layer;

[0049] Step S12: using a laser annealing process to heat and melt the needle mark protrusion to reduce the height of the needle mark protrusion.

[0050] See below Figure 4a to Figure 4d as well as Figure 5a to Figure 5b The test pad processing method provided in this embodiment is described in detail. Figure 4a to Figure 4d as well as Figure 5a to Figure 5b It is a schematic diagram of a longitudinal cross-section of a semiconductor device.

[0051] According to step S11, a substrate (not shown) is provided, on which a first insulating dielectric layer 31 and a first test pad 32 located in the first insulating dielectric layer 31 are formed, the first insulating dielectric layer 31 exposes at least a portion of the surface of the first test pad 32, and the surface of the first test pad 32 exposed by the first insulating dielectric layer 31 is formed with a needle mark protrusion caused by a probe test.

[0052] In particular, when the needle mark protrusion extends from the surface of the first test pad 32 and exceeds the surface of the first insulating dielectric layer 31 , it will seriously affect the planarization of the subsequent bonding surface.

[0053] It should be noted that structures such as a source region, a drain region, a well region and an isolation structure may be formed in the substrate, and structures such as a gate and a sidewall may also be formed in the first insulating dielectric layer 31 .

[0054] The first insulating dielectric layer 31 may be a multi-layer stacked structure. Figure 4aIn the illustrated embodiment, the first insulating dielectric layer 31 includes, from bottom to top, a first insulating material layer 311, a second insulating material layer 312, and a third insulating material layer 313; the first test pad 32 includes a first conductive plug 321 located in the second insulating material layer 312 and a first pad 322 located in the third insulating material layer 313, the first pad 322 is electrically connected to the first conductive plug 321, a portion of the surface of the first pad 322 is exposed by the third insulating material layer 313, and the surface of the first pad 322 exposed by the third insulating material layer 313 is the surface of the first test pad 32 exposed by the first insulating dielectric layer 31. It should be noted that the first insulating dielectric layer 31 is not limited to Figure 4a The structure shown.

[0055] After the probe is used to contact the first test pad 32 for testing, the surface of the first test pad 32 (i.e. Figure 4a A needle mark may be generated on the surface of the first test pad 322, and the needle mark includes a needle mark protrusion D3 and a needle mark depression D4. The height of the needle mark protrusion D3 is much greater than the height of the third insulating material layer 313, that is, the needle mark protrusion D3 extends from the surface of the first test pad 32 beyond the surface of the third insulating material layer 313. For example, the height of the needle mark protrusion D3 may reach about 2 μm, which seriously affects the flatness of the surface of the semiconductor device. Moreover, if the semiconductor device needs to be bonded to a wafer with the side where the needle mark protrusion D3 is located as a bonding surface, the uneven bonding surface may cause bonding abnormalities.

[0056] A metal interconnect structure 33 is formed in the first insulating dielectric layer 31, and the first test pad 32 is electrically connected to the metal interconnect structure 33. Figure 4a As shown, the metal interconnect structure 33 is formed in the first insulating material layer 311, and the metal interconnect structure 33 includes a second conductive plug 331 and a metal wire 332. One side of the metal wire 332 is electrically connected to the second conductive plug 331, and the other side of the metal wire 332 is electrically connected to the first conductive plug 321. The contact surface between the other side of the metal wire 332 and the first conductive plug 321 is the bottom surface of the first test pad 32. It should be noted that the structure of the metal interconnect structure 33 is not limited to Figure 4a The structure shown.

[0057] And, if Figure 4a to Figure 4d As shown, the first insulating dielectric layer 31 may only be formed with the first test pad 32, and the single first test pad 32 connects the metal interconnect structure 33; or Figure 5a to Figure 5bAs shown, a first test pad 32 and a second test pad 36 are formed in the first insulating dielectric layer 31 at the same time, the bottoms of the first test pad 32 and the second test pad 36 are both electrically connected to the metal interconnect structure 33, and the first test pad 32 and the second test pad 36 are connected in parallel to the metal interconnect structure 33. The second test pad 36 may include a third conductive plug (not shown) located in the second insulating material layer 312 and a second pad (not shown) located in the third insulating material layer 313, the second pad is electrically connected to the third conductive plug, and the third conductive plug is electrically connected to the metal line 332.

[0058] The material of the first insulating dielectric layer 31 is a conventional insulating material in the art, and the material of the first insulating dielectric layer 31 can be at least one of insulating materials such as silicon oxide, silicon nitride, silicon oxynitride and silicon carbide nitride; the material of the first test pad 32 and the second test pad 36 is pure metal or metal alloy, wherein the metal alloy can contain at least two of aluminum, tin, copper, nickel and gold; the material of the metal interconnect structure 33 is a conventional metal material in the art, and can be at least one of metal materials such as aluminum, tungsten, copper and titanium, and the material of the metal wire 332 and the second conductive plug 331 can be the same or different.

[0059] According to step S12, the needle mark protrusion D3 is heated and melted by a laser annealing process to reduce the height of the needle mark protrusion D3.

[0060] In particular, when the height of the needle mark protrusion D3 is very high (for example, the needle mark protrusion D3 extends from the surface of the first test pad 32 to exceed the surface of the first insulating dielectric layer 31), the height of the needle mark protrusion D3 is reduced to be lower than the height of the second insulating dielectric layer (i.e. Figure 4c to Figure 4d as well as Figure 5a to Figure 5b The surface of the second insulating dielectric layer 34 in the test pad 32 after the planarization process is performed, so that when the planarization process is performed on the second insulating dielectric layer 34, the needle mark protrusion D3 will not be exposed, thereby avoiding metal contamination during the planarization process. At the same time, it also allows the subsequent semiconductor device to use the side where the needle mark protrusion D3 is located as the bonding surface to be bonded to a wafer, avoiding bonding abnormalities caused by uneven bonding surfaces. In addition, when the height of the needle mark protrusion D3 is small (for example, the needle mark protrusion D3 does not extend from the surface of the first test pad 32 to the surface of the first insulating dielectric layer 31), the presence of the needle mark protrusion D3 will also cause device performance to deteriorate.

[0061] When performing the laser annealing process, the laser light L( Figure 4aThe needle mark protrusion D3 on the first test pad 32 exposed by the first insulating dielectric layer 31 is irradiated with the arrow in the middle (as shown in the figure). Preferably, the irradiation area does not exceed the first test pad 32 exposed by the first insulating dielectric layer 31, and may be irradiated only on the needle mark protrusion D3, or may be irradiated on the needle mark protrusion D3 and the first test pad 32 (including the area of ​​the needle mark depression D4) close to the needle mark protrusion D3, or may be irradiated on the entire first test pad 32 exposed by the first insulating dielectric layer 31. The material of the needle mark protrusion D3 melts and flows to the area outside the needle mark protrusion D3 on the first test pad 32, so that the height of the needle mark protrusion D3 is reduced. Furthermore, the melted material of the needle mark protrusion D3 can fill the needle mark depression D4 and re-flow on the surface of the first test pad 32 to form a new surface without the needle mark protrusion D3 and the needle mark depression D4 after cooling, so that the needle mark protrusion D3 is fused with part of the material of the first test pad 32 to remove the needle mark protrusion D3. Figure 4b As shown, after the needle mark protrusion D3 is heated and melted by laser annealing process, the height of the needle mark protrusion D3 is reduced to be smaller than the height of the third insulating material layer 313 .

[0062] It should be noted that after the needle mark protrusion D3 is heated and melted by the laser annealing process, the needle mark protrusion D3 can only be reduced in height, or the needle mark protrusion D3 can be completely removed (that is, the first test pad 32 exposed by the first insulating dielectric layer 31 forms a new flat surface without needle mark protrusions and needle mark depressions).

[0063] Therefore, the laser annealing process is used to heat and melt the needle mark protrusion D3 so that the needle mark protrusion D3 is fused with the first test pad 32 to reduce the height of the needle mark protrusion D3 or remove the needle mark protrusion D3. Figure 1a and Figure 1b As shown, the first test pad 15 is abandoned and the second test pad 16 is used to connect the metal interconnect structure 14 and Figure 2a and Figure 2b Compared with the two solutions of removing part of the thickness of the test pad and refilling the test pad, the solution of this embodiment can solve the problem of needle mark protrusion defects with minimal processes, and the first test pad 32 can continue to be used after reducing or removing the needle mark protrusion, so that the process difficulty is significantly reduced.

[0064] Furthermore, the laser annealing process may use a monochromatic laser or a superposition of at least two monochromatic lasers. The monochromatic laser is any known laser in the art, for example, the monochromatic laser may be a laser of different wavelengths ranging from short-wave ultraviolet to far infrared, preferably, the monochromatic laser may be red light, green light, yellow light or violet light, and the superposition of at least two monochromatic lasers may be a mixed superposition of red light and green light, or a mixed superposition of red light and violet light.

[0065] The energy density of the laser used in the laser annealing process is such that the heating temperature of the first test pad 32 at least reaches the melting point of the material of the first test pad 32 .

[0066] According to the material of the first test pad 32, a suitable laser wavelength and a suitable laser irradiation time are selected so that the laser used in the laser annealing process reaches a suitable energy density, thereby melting the material of the first test pad 32 while avoiding affecting other structures of the device. The shorter the laser wavelength and / or the longer the laser irradiation time, the higher the temperature for heating and melting the first test pad 32; and the shorter the laser wavelength, the deeper the heating depth of the first test pad 32.

[0067] Preferably, the temperature of the bottom surface of the first test pad 32 and the temperature below the bottom surface is not higher than 500° C. For example, if the material of the first test pad 32 is a metal alloy including aluminum and copper, the energy density of the laser used in the laser annealing process needs to make the heating temperature of the first test pad 32 reach 600° C. to 700° C., so that the first test pad 32 can be melted. However, since the laser heating action area is located on the surface of the object and there is a temperature drop from the surface to the inside of the object, in order to avoid damage to the structure below the first test pad 32, such as Figure 4a As shown, the contact surface between the first test pad 32 and the metal interconnection structure 33 and the temperature of the metal interconnection structure 33 are not higher than 500° C. The laser used in the laser annealing process may be green light.

[0068] In addition, the laser annealing process can adopt continuous spot irradiation or point scanning irradiation. Among them, when the area of ​​the first test pad 32 exposed by the first insulating dielectric layer 31 is large, it is preferred to adopt continuous spot irradiation, that is, a laser spot with a larger area is used to irradiate a certain area on the first test pad 32, and it is kept for a long time until the irradiated area melts, so as to improve efficiency; when the area of ​​the first test pad 32 exposed by the first insulating dielectric layer 31 is small, in order to avoid laser irradiation to the first insulating dielectric layer 31 outside the exposed first test pad 32, it is preferred to adopt point scanning irradiation, that is, a laser spot with a very small area is used to irradiate a certain position on the first test pad 32, and the duration is very short. After the irradiation of this position is completed, it is moved to another position until all the areas to be irradiated are completed.

[0069] In addition, after the needle mark protrusion D3 is heated and melted by laser annealing, the test pad processing method may further include: cleaning the surface of the first test pad 32 and the first insulating dielectric layer 31 .

[0070] From the above content, it can be seen that the test pad processing method of the present invention, for the needle mark protrusion caused by the probe test formed on the surface of the first test pad exposed by the first insulating dielectric layer, heats and melts the needle mark protrusion by using a laser annealing process, so that the height of the needle mark protrusion is reduced, thereby ensuring that the bonding surface has good flatness while reducing the process difficulty, improving the processing efficiency and reducing the cost.

[0071] An embodiment of the present invention provides a method for manufacturing a semiconductor device, the method comprising:

[0072] Step S21, providing a substrate, on which a first insulating dielectric layer and a first test pad located in the first insulating dielectric layer are formed, the first insulating dielectric layer exposes at least a portion of a surface of the first test pad, and a probe mark protrusion caused by a probe test is formed on the surface of the first test pad exposed by the first insulating dielectric layer;

[0073] Step S22, heating and melting the needle mark protrusion by laser annealing process to reduce the height of the needle mark protrusion;

[0074] Step S23, forming a second insulating dielectric layer covering the first test pad and the first insulating dielectric layer;

[0075] Step S24, performing a planarization process on the second insulating dielectric layer, so that the height of the reduced protrusions is lower than the surface of the second insulating dielectric layer after the planarization process.

[0076] See below Figure 4a to Figure 4d as well as Figure 5a to Figure 5b The method for preparing the semiconductor device provided in this embodiment is introduced in detail. Figure 4a to Figure 4d as well as Figure 5a to Figure 5b It is a schematic diagram of a longitudinal cross-section of a semiconductor device.

[0077] According to step S21, a substrate (not shown) is provided, on which a first insulating dielectric layer 31 and a first test pad 32 located in the first insulating dielectric layer 31 are formed, the first insulating dielectric layer 31 exposes at least a portion of the surface of the first test pad 32, and the surface of the first test pad 32 exposed by the first insulating dielectric layer 31 is formed with a needle mark protrusion caused by a probe test.

[0078] The specific content of step S21 refers to step S11, which will not be repeated here.

[0079] According to step S22, the needle mark protrusion D3 is heated and melted by a laser annealing process to reduce the height of the needle mark protrusion D3.

[0080] The specific content of step S22 refers to step S12, which will not be repeated here.

[0081] The laser annealing process is used to heat and melt the needle mark protrusion D3 to reduce the height of the needle mark protrusion D3 or to fuse the needle mark protrusion D3 with the first test pad 32 to remove the needle mark protrusion D3, and Figure 1a and Figure 1b As shown, the first test pad 15 is abandoned and the second test pad 16 is used to connect the metal interconnect structure 14 and Figure 2a and Figure 2b Compared with the two solutions of removing part of the thickness of the test pad and refilling the test pad, the solution of this embodiment can solve the problem of needle mark protrusion defects with minimal processes, and the first test pad 32 can continue to be used after reducing or removing the needle mark protrusion, which can significantly reduce the process complexity.

[0082] Step S23, forming a second insulating dielectric layer 34 covering the first test pad 32 and the first insulating dielectric layer 31. Figure 4c As shown, the second insulating dielectric layer 34 buries the third insulating material layer 313 and the first test pad 32 exposed by the third insulating material layer 313 .

[0083] The second insulating dielectric layer 34 may be made of at least one insulating material selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide nitride.

[0084] Step S24 , performing a planarization process on the second insulating dielectric layer 34 , so that the height of the reduced needle mark protrusion D3 is lower than the surface of the second insulating dielectric layer 34 after the planarization process.

[0085] Among them, since the height of the needle mark protrusion D3 on the first test pad 32 is reduced to be lower than the surface of the second insulating dielectric layer 34 after the flattening process is performed, the thickness of the formed second insulating dielectric layer 34 is very thin and can cover the first test pad 32 and the first insulating dielectric layer 31, thereby reducing the difficulty of subsequent processes (for example, the difficulty of forming a conductive structure through subsequent etching and filling processes is reduced), thereby reducing costs.

[0086] The second insulating dielectric layer 34 may be planarized by chemical mechanical polishing, so that the second insulating dielectric layer 34 has good flatness.

[0087] Since the height of the needle mark protrusion D3 on the first test pad 32 is reduced to be lower than the surface of the second insulating dielectric layer 34 after the planarization process is performed, the needle mark protrusion D3 will not be exposed when the planarization process is performed on the second insulating dielectric layer 34, thereby avoiding metal contamination during the planarization process.

[0088] In addition, the method for preparing the semiconductor device may further include: providing a wafer (not shown) or a chip (not shown), and bonding the side of the second insulating dielectric layer 34 away from the substrate to the wafer or the chip. In particular, since the surface of the second insulating dielectric layer 34 (i.e., the side of the second insulating dielectric layer 34 away from the substrate) has good flatness, and the surface of the second insulating dielectric layer 34 is free of metal contamination, the side of the second insulating dielectric layer 34 away from the substrate as a bonding surface can be bonded normally with the wafer or chip, thereby avoiding bonding abnormalities.

[0089] in, Figure 4a to Figure 4d as well as Figure 5a to Figure 5b The structure shown may be located on a wafer or a chip, that is, the bonding of the side of the second insulating dielectric layer 34 away from the substrate to the wafer or chip may be wafer-to-wafer bonding, wafer-to-chip bonding, or chip-to-chip bonding.

[0090] Furthermore, a side of the second insulating dielectric layer 34 away from the substrate may be the front side or the back side of a wafer or a chip, and the front side and the back side are opposite sides.

[0091] In addition, if only the first test pad 32 is formed in the first insulating dielectric layer 31, then Figure 4d As shown, after performing a planarization process on the second insulating dielectric layer 34 and before bonding the side of the second insulating dielectric layer 34 away from the substrate to the wafer or the chip, the method for preparing the semiconductor device also includes: forming a conductive structure 35 in the second insulating dielectric layer 34, and the bottom of the conductive structure 35 is electrically connected to the first test pad 32; or, after bonding the side of the second insulating dielectric layer 34 away from the substrate to the wafer or the chip, the method for preparing the semiconductor device also includes: forming a conductive structure 35 that penetrates the wafer or the chip and extends into the second insulating dielectric layer 34, and the conductive structure 35 is electrically connected to the first test pad 32.

[0092] If the first test pad 32 and the second test pad 36 are formed in the first insulating dielectric layer 31, and the bottoms of the first test pad 32 and the second test pad 36 are electrically connected to the metal interconnect structure 33, then after the second insulating dielectric layer 34 is planarized and before the second insulating dielectric layer 34 is bonded to the wafer or the chip at a side away from the substrate, the method for preparing the semiconductor device further includes: Figure 5a As shown, a conductive structure 35 is formed in the second insulating dielectric layer 34, and the bottom of the conductive structure 35 is electrically connected to the first test pad 32; or Figure 5b As shown, a conductive structure 35 is formed which penetrates the second insulating dielectric layer 34 and extends to a third insulating material layer 313 of a part of the thickness of the first insulating dielectric layer 31, and the conductive structure 35 is electrically connected to the second test pad 36. Alternatively, after bonding the side of the second insulating dielectric layer 34 away from the substrate to the wafer or the chip, the method for preparing the semiconductor device further includes: Figure 5a As shown, a conductive structure 35 is formed that penetrates the wafer or the chip and extends into the second insulating dielectric layer 34, and the bottom of the conductive structure 35 is electrically connected to the first test pad 32; or Figure 5b As shown, a conductive structure 35 is formed which penetrates the wafer or the chip and the second insulating dielectric layer 34 and extends into the first insulating dielectric layer 31 , and the bottom of the conductive structure 35 is electrically connected to the second test pad 36 .

[0093] The conductive structure 35 may include a conductive plug (not shown) and a pad (not shown), the pad is exposed by the second insulating dielectric layer 34, and the bottom surface of the pad is electrically connected to the conductive plug. Figure 4d and Figure 5a to Figure 5b The structure shown in FIG. 3 may also be connected in parallel with at least two conductive plugs to connect the first test pad 32 or the second test pad 36 to reduce connection resistance and increase connection reliability.

[0094] From the above content, it can be seen that the method for preparing a semiconductor device of the present invention, for the needle mark protrusion caused by the probe test formed on the surface of the first test pad exposed by the first insulating dielectric layer, heats and melts the needle mark protrusion by using a laser annealing process, so that the height of the needle mark protrusion is reduced to be lower than the surface of the second insulating dielectric layer after the flattening process, thereby ensuring that the bonding surface has good flatness while reducing the process difficulty and avoiding metal contamination of the bonding surface.

[0095] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A test pad processing method, characterized in that: include: A substrate is provided, on which a first insulating dielectric layer and a first test pad located in the first insulating dielectric layer are formed, the first insulating dielectric layer exposes at least a portion of a surface of the first test pad, and a needle mark protrusion caused by a probe test is formed on the surface of the first test pad exposed by the first insulating dielectric layer, and the needle mark protrusion extends from the surface of the first test pad to exceed the surface of the first insulating dielectric layer; The needle mark protrusion is heated and melted by laser annealing process to reduce the height of the needle mark protrusion. The upper surface of the needle mark protrusion after reduction is lower than the surface of the first insulating medium layer and higher than the surface of the first test pad outside the needle mark.

2. The test pad processing method according to claim 1, characterized in that: The laser used in the laser annealing process is a monochromatic laser or a superposition of at least two monochromatic lasers.

3. The test pad processing method according to claim 1, characterized in that: The energy density of the laser used in the laser annealing process is such that the heating temperature at least reaches the melting point of the material of the first test pad.

4. The test pad processing method according to claim 3, characterized in that: The first test pad is made of a metal alloy including aluminum and copper, and the heating temperature is 600° C. to 700° C.

5. The test pad processing method according to claim 1, wherein: The laser annealing process adopts surface spot continuous irradiation or point scanning irradiation, and the irradiation area does not exceed the first test pad exposed by the first insulating dielectric layer.

6. The test pad processing method according to claim 1, wherein: The temperature of the bottom surface of the first test pad is not higher than 500°C.

7. The test pad processing method according to claim 1, characterized in that: After the needle mark protrusion is heated and melted by laser annealing process, the test pad processing method further includes: cleaning the surface of the first test pad.

8. A method for preparing a semiconductor device, characterized in that: include: A substrate is provided, on which a first insulating dielectric layer and a first test pad located in the first insulating dielectric layer are formed, the first insulating dielectric layer exposes at least a portion of a surface of the first test pad, and a needle mark protrusion caused by a probe test is formed on the surface of the first test pad exposed by the first insulating dielectric layer, and the needle mark protrusion extends from the surface of the first test pad to exceed the surface of the first insulating dielectric layer; Using a laser annealing process to heat and melt the needle mark protrusion to reduce the height of the needle mark protrusion, wherein the upper surface of the needle mark protrusion after the reduction is lower than the surface of the first insulating dielectric layer and higher than the surface of the first test pad outside the needle mark; forming a second insulating dielectric layer covering the first test pad and the first insulating dielectric layer; A planarization process is performed on the second insulating dielectric layer.

9. The method for preparing a semiconductor device according to claim 8, wherein: A metal interconnection structure is formed in the first insulating dielectric layer, and the bottom of the first test pad is electrically connected to the metal interconnection structure; the method for preparing the semiconductor device further includes: A wafer or a chip is provided, and a surface of the second insulating medium layer away from the substrate is bonded to the wafer or the chip.

10. The method for preparing a semiconductor device according to claim 9, characterized in that: After performing a planarization process on the second insulating dielectric layer and before bonding a side of the second insulating dielectric layer away from the substrate to the wafer or the chip, the method for preparing the semiconductor device further includes: forming a conductive structure in the second insulating dielectric layer, wherein the conductive structure is electrically connected to the first test pad; Alternatively, after bonding the side of the second insulating dielectric layer away from the substrate to the wafer or the chip, the method for preparing the semiconductor device further comprises: A conductive structure is formed that penetrates the wafer or the chip and extends into the second insulating medium layer, and the conductive structure is electrically connected to the first test pad.

11. The method for preparing a semiconductor device according to claim 9, wherein: A second test pad is also formed in the first insulating dielectric layer, and the bottom of the second test pad is electrically connected to the metal interconnect structure; after performing a planarization process on the second insulating dielectric layer and before bonding a side of the second insulating dielectric layer away from the substrate to the wafer or the chip, the method for preparing the semiconductor device further includes: forming a conductive structure penetrating the second insulating dielectric layer and extending to the first insulating dielectric layer, wherein the conductive structure is electrically connected to the second test pad; Alternatively, after bonding the side of the second insulating dielectric layer away from the substrate to the wafer or the chip, the method for preparing the semiconductor device further comprises: A conductive structure is formed which penetrates the wafer or the chip and the second insulating dielectric layer and extends into the first insulating dielectric layer, and the conductive structure is electrically connected to the second test pad.

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