A circuit and method for multiplexing JTAG pins in FPGA chip

Abstract

The present application discloses a circuit and method for multiplexing JTAG pins in an FPGA chip, the circuit comprising: a plurality of input terminals, including a TCK pin, a TMS pin and a TDI pin; wherein the TCK pin provides a TCK clock, the TMS pin provides a TMS signal, and the TDI pin provides a TDI signal; a TDO pin; a virtual JTAG device, which is used to generate a virtual JTAG output according to the TMS signal and the TDI signal under the control of the TCK clock; or a user logic device, which is used to generate a user logic JTAG output according to the TMS signal and the TDI signal under the control of the TCK clock; a gating circuit, which is used to provide the TCK clock, the TMS signal and the TDI signal to the virtual JTAG device in one case, and output the virtual JTAG output of the virtual JTAG device through the TDO pin according to the control of the user logic; in another case, provide the TCK clock, the TMS signal and the TDI signal to the user logic device, and output the user logic JTAG output of the user logic device through the TDO pin.

Description

Technical Field

[0001] The present invention relates to the field of Field-Programmable Gate Array (FPGA) technology, and in particular to a circuit and method for multiplexing Joint Test Action Group (JTAG) pins in an FPGA chip. Background Art

[0002] As FPGA devices are increasingly widely used, more and more application design companies are beginning to use FPGA devices to implement their application designs, such as burning user logic designs into FPGA devices. Many users will integrate complex designs with JTAG debugging functions into user logic designs, such as microcontroller unit (MCU) designs. To facilitate debugging of MCU programs in MCU designs, users will connect a set of JTAG pins of MCU designs, such as test clock (TCK) pins, test mode select (TMS) pins, test data input (TDI) pins, and test data output (TDO) pins to a set of user input / output (IO) interfaces, and connect debuggers through user IO interfaces for debugging, or connect programmers for programming, or connect testers for testing. In this way, when there are multiple MCU designs, there will be multiple sets of JTAG pins. At this time, it is necessary to connect multiple debuggers for debugging, or connect multiple programmers for programming, or connect multiple testers for testing through multiple sets of user IO interfaces, resulting in a large amount of resource overhead. Summary of the invention

[0003] Since the existing methods have the above-mentioned problems, the present application proposes a circuit and method for multiplexing JTAG pins in an FPGA chip.

[0004] In a first aspect, the present application proposes a circuit for multiplexing JTAG pins in an FPGA chip, comprising:

[0005] Multiple input terminals, including a test clock TCK pin, a test mode selection TMS pin and a test data input TDI pin; wherein the TCK pin provides a TCK clock, the TMS pin provides a TMS signal, and the TDI pin provides a TDI signal;

[0006] Test data output TDO pin;

[0007] A virtual joint test action group JTAG device, used for generating a virtual JTAG output according to the TMS signal and the TDI signal under the control of the TCK clock; or

[0008] A user logic device, used for generating a user logic JTAG output according to the TMS signal and the TDI signal under the control of the TCK clock;

[0009] A gating circuit is used for, according to the control of user logic, in one case, providing the TCK clock, the TMS signal and the TDI signal to the virtual JTAG device, and outputting the virtual JTAG output of the virtual JTAG device through the TDO pin; in another case, providing the TCK clock, the TMS signal and the TDI signal to the user logic device, and outputting the user logic JTAG output of the user logic device through the TDO pin.

[0010] In a possible implementation, the gating circuit includes:

[0011] A configuration bit unit, configured to output a first signal, wherein the first signal is used to enable an AND gate and to serve as an input signal of the AND gate;

[0012] A JTAG test access port TAP state machine, configured to output a second signal and a third signal according to the TCK clock, the TMS signal, the TDI signal and a timing relationship therebetween, wherein the second signal and the first signal are used to determine a fourth signal output by the AND gate, wherein the fourth signal is used to determine a first selection result of the first selector and a second selection result of the second selector, and wherein the third signal is sent to the virtual JTAG device when the virtual JTAG device is enabled, or is sent to the user logic device when the user logic device is enabled;

[0013] The AND gate is used to output the fourth signal according to the first signal and the second signal;

[0014] The first selector is used to determine a first selection result according to the fourth signal, wherein the first selection result is that in one case, the TCK clock, the TMS signal and the TDI signal are provided to the virtual JTAG device; in another case, the TCK clock, the TMS signal and the TDI signal are provided to the user logic device;

[0015] The second selector is used to determine a second selection result according to the fourth signal, wherein the second selection result is that in one case, the virtual JTAG output of the virtual JTAG device is output through the TDO pin; in another case, the user logic JTAG output of the user logic device is output through the TDO pin.

[0016] In a possible implementation, the FPGA chip further includes:

[0017] An external input pin is used to output a fifth signal, and the fifth signal, the first signal and the second signal are used to determine a fourth signal output by the AND gate.

[0018] In a second aspect, the present application proposes a method for multiplexing JTAG pins in an FPGA chip, comprising:

[0019] Generate a virtual JTAG output through a virtual JTAG device based on a TMS signal provided by the TMS pin and a TDI signal provided by the TDI pin under the control of a TCK clock provided by the TCK pin; or

[0020] Under the control of the TCK clock provided by the TCK pin, the user logic JTAG output is generated through the user logic device according to the TMS signal provided by the TMS pin and the TDI signal provided by the TDI pin;

[0021] According to the control of the user logic, in one case, the TCK clock, the TMS signal and the TDI signal are provided to the virtual JTAG device through the gating circuit, and the virtual JTAG output of the virtual JTAG device is output through the TDO pin; in another case, the TCK clock, the TMS signal and the TDI signal are provided to the user logic device through the gating circuit, and the user logic JTAG output of the user logic device is output through the TDO pin.

[0022] In one possible implementation, the gating circuit includes a configuration bit unit, a JTAG TAP state machine, an AND gate, a first selector, and a second selector;

[0023] According to the control of the user logic, in one case, the TMS signal and the TDI signal are provided to the virtual JTAG device through a gating circuit, and the virtual JTAG output of the virtual JTAG device is output through a TDO pin; in another case, the TMS signal and the TDI signal are provided to the user logic device through a gating circuit, and the user logic JTAG output of the user logic device is output through the TDO pin, including:

[0024] Outputting a first signal by configuring the bit unit, wherein the first signal is used to enable an AND gate and serves as an input signal of the AND gate;

[0025] According to the TCK clock, the TMS signal, the TDI signal and the timing relationship between them, a second signal and a third signal are output through a JTAG TAP state machine, the second signal and the first signal are used to determine a fourth signal output by the AND gate, the fourth signal is used to determine a first selection result of the first selector and a second selection result of the second selector, and the third signal is sent to the virtual JTAG device when the virtual JTAG device is enabled, or is sent to the user logic device when the user logic device is enabled;

[0026] Outputting the fourth signal through the AND gate according to the first signal and the second signal;

[0027] According to the fourth signal, determining a first selection result by the first selector, wherein the first selection result is that in one case, the TCK clock, the TMS signal and the TDI signal are provided to the virtual JTAG device; in another case, the TCK clock, the TMS signal and the TDI signal are provided to the user logic device;

[0028] According to the fourth signal, a second selection result is determined by the second selector, and the second selection result is that in one case, the virtual JTAG output of the virtual JTAG device is output through the TDO pin; in another case, the user logic JTAG output of the user logic device is output through the TDO pin.

[0029] In a possible implementation, the method further includes:

[0030] Output a fifth signal via an external input pin;

[0031] A fourth signal output by the AND gate is determined according to the fifth signal, the first signal, and the second signal.

[0032] In a third aspect, the present application also proposes a device for reusing JTAG pins in an FPGA chip, comprising:

[0033] a processing unit for generating a virtual JTAG output through a virtual JTAG device according to a TMS signal provided by a TMS pin and a TDI signal provided by a TDI pin under the control of a TCK clock provided by a TCK pin; or

[0034] The processing unit is used to generate a user logic JTAG output through a user logic device according to a TMS signal provided by a TMS pin and a TDI signal provided by a TDI pin under the control of a TCK clock provided by a TCK pin;

[0035] The transceiver unit is used to provide the TCK clock, the TMS signal and the TDI signal to the virtual JTAG device through a gating circuit in one case and output the virtual JTAG output of the virtual JTAG device through a TDO pin according to the control of the user logic; and to provide the TCK clock, the TMS signal and the TDI signal to the user logic device through a gating circuit in another case and output the user logic JTAG output of the user logic device through the TDO pin.

[0036] In a fourth aspect, the present application also proposes a device for multiplexing JTAG pins within an FPGA chip, comprising at least one processor, wherein the processor is used to execute a program stored in a memory. When the program is executed, the device executes the various steps in the second aspect and various possible implementations.

[0037] In a fifth aspect, the present application further proposes a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the various steps in the second aspect and various possible implementations.

[0038] It can be seen from the above technical solution that the virtual JTAG device and the user logic device in the present application share four JTAG pins. It only needs to connect the four JTAG pins to a set of user input / output (IO) interfaces for debugging through a debugger, or programming through a programmer, or testing through a tester, thereby reducing the number of user IO interfaces and debuggers, programmers or testers used, and reducing resource overhead. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0040] Figure 1a A schematic diagram of a circuit for multiplexing JTAG pins in an FPGA chip provided in an embodiment of the present application;

[0041] Figure 1b The embodiment of the present application provides Figure 1aA schematic diagram of a circuit with an external input pin 108 added to the basis;

[0042] Figure 2 A flowchart of a method for multiplexing JTAG pins in an FPGA chip provided in an embodiment of the present application;

[0043] Figure 3 A schematic diagram of the structure of a device for multiplexing JTAG pins in an FPGA chip provided in an embodiment of the present application. DETAILED DESCRIPTION

[0044] The technical solutions in the embodiments of the present invention will be described below in conjunction with the accompanying drawings in the embodiments of the present invention. The following embodiments are only used to more clearly illustrate the technical solutions of the present invention, and cannot be used to limit the protection scope of the present invention.

[0045] It should be noted that the term "and / or" in this application is only a kind of association relationship describing the associated objects, indicating that there may be three relationships, for example, A and / or B, which can represent: A exists alone, A and B exist at the same time, and B exists alone. The terms "first" and "second" in the description and claims of the embodiments of the present application are used to distinguish different objects, rather than to describe the specific order of objects. For example, the first selector and the second selector are used to distinguish different selectors, rather than to describe the specific order of target objects. In the embodiments of the present application, words such as "exemplary", "for example" or "for example" are used to indicate examples, illustrations or explanations. Any embodiment or design described as "exemplary", "for example" or "for example" in the embodiments of the present application should not be interpreted as having advantages over other embodiments or design schemes. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way. In the description of the embodiments of the present application, unless otherwise specified, the meaning of "multiple" refers to two or more.

[0046] In one possible implementation, more and more application design companies will burn user logic designs into FPGA devices. Many of these users will integrate complex designs with JTAG debugging functions into user logic designs, such as MCU designs. To facilitate debugging of MCU programs in MCU designs, users will connect a set of JTAG pins of the MCU design, such as TCK pins, TMS pins, TDI pins, and TDO pins, to a set of user IO interfaces, and connect a debugger through the user IO interface for debugging, or connect a programmer for programming, or connect a tester for testing. In this way, when there are multiple MCU designs, there will be multiple sets of JTAG pins. At this time, it is necessary to connect multiple debuggers for debugging, or connect multiple programmers for programming, or connect multiple testers for testing through multiple sets of user IO interfaces, resulting in a large amount of resource overhead.

[0047] To solve the above technical problems, the present application embodiment proposes a circuit for multiplexing JTAG pins in an FPGA chip. The schematic diagram of the circuit is shown in FIG. Figure 1a The schematic diagram of the circuit specifically includes: multiple input terminals, TDO pin 104, virtual JTAG device 105, user logic device 106 and gating circuit 107; wherein the multiple input terminals include: TCK pin 101 for providing TCK clock, TMS pin 102 for providing TMS signal, TDI pin 103 for providing TDI signal, gating circuit 107 includes configuration bit unit 1071, JTAG TAP state machine 1072, AND gate 1073, first selector 1074 and second selector 1075.

[0048] See also Figure 1a , according to the control of the user logic, in one case (i.e. the virtual JTAG device 105 is enabled and the user logic device 106 is disabled), the virtual JTAG device 105 is connected to the strobe circuit 107, the TCK pin 101, the TMS pin 102 and the TDO pin 104 respectively; wherein the strobe circuit 107 is connected to the TDI pin 103. The strobe circuit 107 provides the TCK clock, TMS signal and TDI signal to the virtual JTAG device 105, and outputs the virtual JTAG output of the virtual JTAG device 105 through the TDO pin 104. Or

[0049] According to the control of the user logic, in another case (i.e., the user logic device 106 is enabled and the virtual JTAG device 105 is disabled), the user logic device 106 is respectively connected to the strobe circuit 107, the TCK pin 101, the TMS pin 102 and the TDO pin 104; wherein the strobe circuit 107 is connected to the TDI pin 103. The strobe circuit 107 provides the TCK clock, the TMS signal and the TDI signal to the user logic device 106, and outputs the user logic JTAG output of the user logic device 106 through the TDO pin 104. It can be understood that the user logic device 106 is obtained by burning the user logic design into the FPGA device.

[0050] See also Figure 1a , the configuration bit unit 1071 is used to output a first signal, and the first signal is used to enable the AND gate 1073 and serve as an input signal of the AND gate 1073. It can be understood that the configuration bit unit 1071 is burned into the circuit, and the first signal outputted by it is set to 1 when the circuit is powered on, and is set to 0 when the circuit is powered off. The first signal is 1, indicating that the AND gate 1073 is enabled, and the first signal serves as an input signal of the AND gate 1073.

[0051] The JTAG TAP state machine 1072 is connected to the TCK pin 101, the TMS pin 102 and the TDI pin 103, and is used to output a second signal and a third signal according to the TCK clock, the TMS signal, the TDI signal and the timing relationship between them. The second signal and the first signal are used to determine the fourth signal output by the AND gate 1073. The fourth signal is used to determine the first selection result of the first selector 1074 and the second selection result of the second selector 1075. The third signal is sent to the virtual JTAG device 105 when the virtual JTAG device 105 is enabled, or is sent to the user logic device 106 when the user logic device 106 is enabled.

[0052] The AND gate 1073 is used to output a fourth signal according to the first signal and the second signal. Exemplarily, when the first signal is 1 and the second signal is also 1, the fourth signal output by the AND gate 1073 is 1; or when the first signal is 1 and the second signal is 0, the fourth signal output by the AND gate 1073 is 0.

[0053] It should be noted here that Figure 1aFor example, "#Enable" in represents enabling the user logic device 106, and at this time, the fourth signal output by the AND gate 1073 needs to be 1. Since one of the input signals of the AND gate 1073 is the first signal output by the configuration bit unit 1071, that is, 1, the other input signal of the AND gate 1073 needs to be 1 in order for the fourth signal output by the AND gate 1073 to be 1. In other words, the second signal output by the JTAG TAP state machine 1072 is 1, and the second signal is used as another input signal of the AND gate 1073, so that the fourth signal output by the AND gate 1073 can be 1.

[0054] The first selector 1074 is used to determine a first selection result according to the fourth signal, wherein the first selection result is that in one case (i.e., the virtual JTAG device 105 is enabled and the user logic device 106 is disabled), the TCK clock, TMS signal and TDI signal are provided to the virtual JTAG device 105; in another case (i.e., the user logic device 106 is enabled and the virtual JTAG device 105 is disabled), the TCK clock, TMS signal and TDI signal are provided to the user logic device 106. In one example, Figure 1a As shown, if the fourth signal is 0, it is determined that the virtual JTAG device 105 is enabled, and the TCK clock, TMS signal and TDI signal are provided to the virtual JTAG device 105; if the fourth signal is 1, it is determined that the user logic device 106 is enabled, and the TCK clock, TMS signal and TDI signal are provided to the user logic device 106.

[0055] The second selector 1075 is used to determine a second selection result according to the fourth signal, wherein the second selection result is that in one case (i.e., the virtual JTAG device 105 is enabled and the user logic device 106 is disabled), the virtual JTAG output of the virtual JTAG device 105 is output through the TDO pin 104; in another case (i.e., the user logic device 106 is enabled and the virtual JTAG device 105 is disabled), the user logic JTAG output of the user logic device 106 is output through the TDO pin 104. In one example, Figure 1a As shown, if the fourth signal is 0, it is determined that the virtual JTAG device 105 is enabled, and the virtual JTAG output of the virtual JTAG device 105 is output through the TDO pin 104; if the fourth signal is 1, it is determined that the user logic device 106 is enabled, and the user logic JTAG output of the user logic device 106 is output through the TDO pin 104.

[0056] In a possible implementation, the aforementioned TCK pin 101, TMS pin 102, TDI pin 103, and TDO pin 104 are connected to a debugger, a programmer, or a tester outside the aforementioned circuit through four input / output IO interfaces. When the first selector 1074 determines to enable the virtual JTAG device 105, the debugger will debug the JTAG TAP state machine 1072 and the virtual JTAG device 105, or the programmer will program the JTAG TAP state machine 1072 and the virtual JTAG device 105, or the tester will test the JTAG TAP state machine 1072 and the virtual JTAG device 105. When the first selector 1074 determines to enable the user logic device 106, the debugger will debug the JTAG TAP state machine 1072 and the user logic device 106, or the programmer will program the JTAG TAP state machine 1072 and the user logic device 106, or the tester will test the JTAG TAP state machine 1072 and the user logic device 106.

[0057] It is understandable that the user logic device 106 may be short-circuited during use. In such an emergency, the user logic device 106 needs to be turned off in time, that is, the output of the AND gate 1073 needs to be turned to 0 in time. Figure 1a An external input pin 108 is added to the circuit shown in FIG. Figure 1b As shown. The external input pin 108 is used to output the fifth signal. When the circuit is powered on, the fifth signal output by the external input pin 108 is set to 1; in an emergency, such as when the user logic device 106 is short-circuited during use, the fifth signal output is set to 0. The fifth signal, the first signal, and the second signal jointly determine the fourth signal output by the AND gate 1073. Exemplarily, when the fifth signal, the first signal, and the second signal are all 1, the fourth signal output by the AND gate 1073 is 1. At this time, the user logic device 106 is still enabled and the virtual JTAG device 105 is turned off. When the fifth signal is 0, even if the first signal and the second signal are both 1, the fourth signal output by the AND gate 1073 is 0, and the user logic device 106 will be turned off and the virtual JTAG device 105 will be enabled. In this way, the fourth signal output by the AND gate 1073 can be controlled by the external input pin 108, thereby effectively controlling the user logic device 106 to be turned off in time and the virtual JTAG device 105 to be enabled when a short circuit occurs in the user logic device 106.

[0058] It can be seen from the above technical solution that the first virtual JTAG device and the first FPGA user logic device in the embodiment of the present application share four JTAG pins. They only need to connect the four JTAG pins to a group of user IO interfaces for debugging through a debugger, or programming through a programmer, or testing through a tester, thereby reducing the number of user IO interfaces and debuggers, programmers or testers used, and reducing resource overhead.

[0059] Figure 2 A flowchart of a method for multiplexing JTAG pins in an FPGA chip provided in an embodiment of the present application, the flowchart comprising: S201-S202;

[0060] S201, under the control of the TCK clock provided by the TCK pin, a virtual JTAG output is generated through a virtual JTAG device according to the TMS signal provided by the TMS pin and the TDI signal provided by the TDI pin; or under the control of the TCK clock provided by the TCK pin, a user logic JTAG output is generated through a user logic device according to the TMS signal provided by the TMS pin and the TDI signal provided by the TDI pin.

[0061] In the embodiment of the present application, the TCK pin 101 provides a TCK clock, the TMS pin 102 provides a TMS signal, and the TDI pin 103 provides a TDI signal. Under the control of the TCK clock, a virtual JTAG output is generated through the virtual JTAG device 105 according to the TMS signal and the TDI signal; or under the control of the TCK clock, a user logic JTAG output is generated through the user logic device 106 according to the TMS signal and the TDI signal.

[0062] S202, according to the control of the user logic, in one case, the TCK clock, TMS signal and TDI signal are provided to the virtual JTAG device through the selection circuit, and the virtual JTAG output of the virtual JTAG device is output through the TDO pin; in another case, the TCK clock, TMS signal and TDI signal are provided to the user logic device through the selection circuit, and the user logic JTAG output of the user logic device is output through the TDO pin.

[0063] In the embodiment of the present application, according to the control of the user logic, in one case (i.e., the virtual JTAG device 105 is enabled and the user logic device 106 is turned off), the TCK clock, TMS signal and TDI signal are provided to the virtual JTAG device 105 through the selection circuit 107, and the virtual JTAG output of the virtual JTAG device 105 is output through the TDO pin 104; in another case (i.e., the user logic device 106 is enabled and the virtual JTAG device 105 is turned off), the TCK clock, TMS signal and TDI signal are provided to the user logic device 106 through the selection circuit 107, and the user logic JTAG output of the user logic device 106 is output through the TDO pin 104.

[0064] In one example, a first signal is outputted through the configuration bit unit 1071, and the first signal is used to enable the AND gate 1073 and is an input signal of the AND gate 1073. According to the TCK clock, the TMS signal, the TDI signal and the timing relationship between them, a second signal and a third signal are outputted through the JTAG TAP state machine 1072, and the second signal and the first signal are used to determine a fourth signal outputted by the AND gate 1073, and the fourth signal is used to determine a first selection result of the first selector 1074 and a second selection result of the second selector 1075, and the third signal is sent to the virtual JTAG device 105 when the virtual JTAG device 105 is enabled, or is sent to the user logic device 106 when the user logic device 106 is enabled. According to the first signal and the second signal, a fourth signal is outputted through the AND gate 1073. According to the fourth signal, a first selection result is determined by the first selector 1074, wherein the first selection result is that in one case, the TCK clock, TMS signal and TDI signal are provided to the virtual JTAG device 105; in another case, the TCK clock, TMS signal and TDI signal are provided to the user logic device 106. According to the fourth signal, a second selection result is determined by the second selector, wherein the second selection result is that in one case, the virtual JTAG output of the virtual JTAG device 105 is output through the TDO pin 104; in another case, the user logic JTAG output of the user logic device 106 is output through the TDO pin 104.

[0065] In a possible implementation, the method further includes: outputting a fifth signal through the external input pin 108. A fourth signal output by the AND gate 1073 is determined according to the fifth signal, the first signal, and the second signal.

[0066] The virtual JTAG device and the user logic device in the embodiment of the present application share four JTAG pins. It is only necessary to connect the four JTAG pins to a group of user IO interfaces for debugging through a debugger, or programming through a programmer, or testing through a tester, thereby reducing the number of user IO interfaces and debuggers, programmers or testers used, and reducing resource overhead.

[0067] Figure 3 A device for multiplexing JTAG pins in an FPGA chip provided in an embodiment of the present application includes:

[0068] The processing unit 301 is used to generate a virtual JTAG output through a virtual JTAG device according to a TMS signal provided by a TMS pin and a TDI signal provided by a TDI pin under the control of a TCK clock provided by a TCK pin; or

[0069] The processing unit 301 is used to generate a user logic JTAG output through a user logic device according to a TMS signal provided by a TMS pin and a TDI signal provided by a TDI pin under the control of a TCK clock provided by a TCK pin;

[0070] The transceiver unit 302 is used to provide the TCK clock, the TMS signal and the TDI signal to the virtual JTAG device through a gating circuit in one case according to the control of the user logic, and output the virtual JTAG output of the virtual JTAG device through the TDO pin; in another case, provide the TCK clock, the TMS signal and the TDI signal to the user logic device through a gating circuit, and output the user logic JTAG output of the user logic device through the TDO pin.

[0071] In a possible implementation, the transceiver unit 302 is used to output a first signal through a configuration bit unit, where the first signal is used to enable an AND gate and serve as an input signal of the AND gate;

[0072] The transceiver unit 302 is used to output a second signal and a third signal through a JTAG TAP state machine according to a TCK clock, a TMS signal, a TDI signal and a timing relationship therebetween, wherein the second signal and the first signal are used to determine a fourth signal output by an AND gate, wherein the fourth signal is used to determine a first selection result of the first selector and a second selection result of the second selector, and the third signal is sent to the virtual JTAG device when the virtual JTAG device is enabled, or is sent to the user logic device when the user logic device is enabled;

[0073] The transceiver unit 302 is used to output a fourth signal through an AND gate according to the first signal and the second signal;

[0074] The processing unit 301 is used to determine a first selection result through a first selector according to the fourth signal, wherein the first selection result is that in one case, the TCK clock, the TMS signal and the TDI signal are provided to the virtual JTAG device; in another case, the TCK clock, the TMS signal and the TDI signal are provided to the user logic device;

[0075] The processing unit 301 is used to determine a second selection result through a second selector according to the fourth signal, wherein the second selection result is, in one case, outputting the virtual JTAG output of the virtual JTAG device through the TDO pin; in another case, outputting the user logic JTAG output of the user logic device through the TDO pin.

[0076] In a possible implementation, the transceiver unit 302 is configured to output the fifth signal through an external input pin;

[0077] The processing unit 301 is configured to determine a fourth signal output by the AND gate according to the fifth signal, the first signal and the second signal.

[0078] An embodiment of the present application also provides a device for multiplexing JTAG pins within an FPGA chip, comprising at least one processor, wherein the processor is used to execute a program stored in a memory. When the program is executed, the device executes each step of the aforementioned method for multiplexing JTAG pins within an FPGA chip.

[0079] An embodiment of the present application provides a non-transitory computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the steps of the aforementioned method for multiplexing JTAG pins in an FPGA chip are implemented.

[0080] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without paying creative labor.

[0081] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0082] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A circuit for multiplexing JTAG pins in an FPGA chip, characterized in that: include: Multiple input terminals, including a test clock TCK pin, a test mode selection TMS pin and a test data input TDI pin; wherein the TCK pin provides a TCK clock, the TMS pin provides a TMS signal, and the TDI pin provides a TDI signal; Test data output TDO pin; A virtual joint test action group JTAG device, used for generating a virtual JTAG output according to the TMS signal and the TDI signal under the control of the TCK clock; or A user logic device, used for generating a user logic JTAG output according to the TMS signal and the TDI signal under the control of the TCK clock; A gating circuit, for providing the TCK clock, the TMS signal and the TDI signal to the virtual joint test action group JTAG device according to the control of the user logic, in one case, to output the virtual JTAG output of the virtual joint test action group JTAG device through the TDO pin; in another case, to provide the TCK clock, the TMS signal and the TDI signal to the user logic device, to output the user logic JTAG output of the user logic device through the TDO pin; The gating circuit includes: a configuration bit unit, which is used to output a first signal, wherein the first signal is used to enable an AND gate and serves as an input signal of the AND gate; A JTAG test access port TAP state machine, configured to output a second signal and a third signal according to the TCK clock, the TMS signal, the TDI signal and a timing relationship therebetween, wherein the second signal and the first signal are used to determine a fourth signal output by the AND gate, wherein the fourth signal is used to determine a first selection result of the first selector and a second selection result of the second selector, and wherein the third signal is sent to the virtual joint test action group JTAG device when the virtual joint test action group JTAG device is enabled, or is sent to the user logic device when the user logic device is enabled; The AND gate is used to output the fourth signal according to the first signal and the second signal; The first selector is used to determine a first selection result according to the fourth signal, wherein the first selection result is that in one case, the TCK clock, the TMS signal and the TDI signal are provided to the virtual joint test action group JTAG device; in another case, the TCK clock, the TMS signal and the TDI signal are provided to the user logic device; The second selector is used to determine a second selection result according to the fourth signal, wherein the second selection result is, in one case, outputting the virtual JTAG output of the virtual joint test action group JTAG device through the TDO pin; in another case, outputting the user logic JTAG output of the user logic device through the TDO pin; The circuit further includes: an external input pin for outputting a fifth signal, wherein the fifth signal, the first signal and the second signal are used to determine a fourth signal output by the AND gate.

2. A method for multiplexing JTAG pins in an FPGA chip, characterized in that: include: Under the control of the TCK clock provided by the TCK pin, a virtual JTAG output is generated through the virtual joint test action group JTAG device according to the TMS signal provided by the TMS pin and the TDI signal provided by the TDI pin; or Under the control of the TCK clock provided by the TCK pin, the user logic JTAG output is generated through the user logic device according to the TMS signal provided by the TMS pin and the TDI signal provided by the TDI pin; According to the control of the user logic, in one case, the TCK clock, the TMS signal and the TDI signal are provided to the virtual joint test action group JTAG device through a gating circuit, and the virtual JTAG output of the virtual joint test action group JTAG device is output through the TDO pin; in another case, the TCK clock, the TMS signal and the TDI signal are provided to the user logic device through a gating circuit, and the user logic JTAG output of the user logic device is output through the TDO pin; The gating circuit includes a configuration bit unit, a JTAG TAP state machine, an AND gate, a first selector and a second selector; The control according to the user logic, in one case, provides the TMS signal and the TDI signal to the virtual joint test action group JTAG device through a gating circuit, and outputs the virtual JTAG output of the virtual joint test action group JTAG device through a TDO pin; in another case, provides the TMS signal and the TDI signal to the user logic device through a gating circuit, and outputs the user logic JTAG output of the user logic device through the TDO pin, including: Outputting a first signal by configuring the bit unit, wherein the first signal is used to enable an AND gate and serves as an input signal of the AND gate; According to the TCK clock, the TMS signal, the TDI signal and the timing relationship between them, a second signal and a third signal are output through the JTAG TAP state machine, the second signal and the first signal are used to determine a fourth signal output by the AND gate, the fourth signal is used to determine a first selection result of the first selector and a second selection result of the second selector, and the third signal is sent to the virtual joint test action group JTAG device when the virtual joint test action group JTAG device is enabled, or is sent to the user logic device when the user logic device is enabled; Outputting the fourth signal through the AND gate according to the first signal and the second signal; According to the fourth signal, determining a first selection result through the first selector, wherein the first selection result is that in one case, the TCK clock, the TMS signal and the TDI signal are provided to the virtual joint test action group JTAG device; in another case, the TCK clock, the TMS signal and the TDI signal are provided to the user logic device; According to the fourth signal, determining a second selection result through the second selector, wherein the second selection result is, in one case, outputting a virtual JTAG output of the virtual joint test action group JTAG device through the TDO pin; in another case, outputting a user logic JTAG output of the user logic device through the TDO pin; Output a fifth signal via an external input pin; A fourth signal output by the AND gate is determined according to the fifth signal, the first signal, and the second signal.

3. A device for multiplexing JTAG pins in an FPGA chip, characterized in that: include: A processing unit, for generating a virtual JTAG output through a virtual joint test action group JTAG device according to a TMS signal provided by a TMS pin and a TDI signal provided by a TDI pin under the control of a TCK clock provided by a TCK pin; or The processing unit is used to generate a user logic JTAG output through a user logic device according to a TMS signal provided by a TMS pin and a TDI signal provided by a TDI pin under the control of a TCK clock provided by a TCK pin; a transceiver unit, configured to provide the TCK clock, the TMS signal and the TDI signal to the virtual joint test action group JTAG device through a gating circuit in one case according to the control of the user logic, and output the virtual JTAG output of the virtual joint test action group JTAG device through a TDO pin; and provide the TCK clock, the TMS signal and the TDI signal to the user logic device through a gating circuit in another case, and output the user logic JTAG output of the user logic device through the TDO pin; A gating circuit, for providing the TCK clock, the TMS signal and the TDI signal to the virtual joint test action group JTAG device according to the control of the user logic, in one case, to output the virtual JTAG output of the virtual joint test action group JTAG device through the TDO pin; in another case, to provide the TCK clock, the TMS signal and the TDI signal to the user logic device, to output the user logic JTAG output of the user logic device through the TDO pin; The gating circuit includes: a configuration bit unit, which is used to output a first signal, wherein the first signal is used to enable an AND gate and serves as an input signal of the AND gate; A JTAG test access port TAP state machine, configured to output a second signal and a third signal according to the TCK clock, the TMS signal, the TDI signal and a timing relationship therebetween, wherein the second signal and the first signal are used to determine a fourth signal output by the AND gate, wherein the fourth signal is used to determine a first selection result of the first selector and a second selection result of the second selector, and wherein the third signal is sent to the virtual joint test action group JTAG device when the virtual joint test action group JTAG device is enabled, or is sent to the user logic device when the user logic device is enabled; The AND gate is used to output the fourth signal according to the first signal and the second signal; The first selector is used to determine a first selection result according to the fourth signal, wherein the first selection result is that in one case, the TCK clock, the TMS signal and the TDI signal are provided to the virtual joint test action group JTAG device; in another case, the TCK clock, the TMS signal and the TDI signal are provided to the user logic device; The second selector is used to determine a second selection result according to the fourth signal, wherein the second selection result is, in one case, outputting the virtual JTAG output of the virtual joint test action group JTAG device through the TDO pin; in another case, outputting the user logic JTAG output of the user logic device through the TDO pin; An external input pin is used to output a fifth signal, and the fifth signal, the first signal and the second signal are used to determine a fourth signal output by the AND gate.

4. A device for multiplexing JTAG pins in an FPGA chip, characterized in that: The device comprises at least one processor, wherein the processor is configured to execute a program stored in a memory, and when the program is executed, the device executes: The method as claimed in claim 2.

5. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method according to claim 2 is implemented.

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