Signal output circuit and delayed signal output circuit

Abstract

The embodiments of the present application provide a signal output circuit and a delayed signal output circuit, wherein the signal output circuit comprises: a first control module, receiving a first pulse signal and an input signal, and outputting a first adjustment signal, wherein a first preset edge of the first adjustment signal has a first delay relative to a rising edge of the input signal; a second control module, receiving a second pulse signal and an input signal, and outputting a second adjustment signal, wherein a second preset edge of the second adjustment signal has a second delay relative to a falling edge of the input signal; a signal output module, receiving the first adjustment signal and the second adjustment signal, and outputting a delayed output signal, wherein a rising edge of the delayed output signal is generated based on a first preset edge of the first adjustment signal, and a falling edge of the delayed output signal is generated based on a second preset edge of the second adjustment signal; the embodiments of the present application generate a delay signal with controllable delay, and the circuit layout area is small and the power consumption of the circuit is low.

Description

Technical Field

[0001] The present application relates to the field of semiconductor circuit design, and in particular to a signal output circuit and a delayed signal output circuit. Background Art

[0002] In semiconductor circuit design, staggered signals are often used. Staggered signals refer to signals generated with a fixed delay at each interval.

[0003] For synchronous signals, clock signals are usually used to generate equally spaced interleaved signals; for asynchronous signals, delay cells are inserted to generate the required equally spaced interleaved signals, and the delay between signals can be achieved by inserting corresponding delay cells as required. Among them, when synchronous signals are used to generate equally spaced interleaved signals, the delay between equally spaced interleaved signals is an integer multiple of the clock cycle, and the controllability of the delay between equally spaced interleaved signals is poor; when asynchronous signals are used to generate equally spaced interleaved signals, although the delay between signals is well controllable, it will significantly increase the area of ​​the formed circuit layout and the power consumption of the circuit.

[0004] However, the applicant discovered that adjusting the signal delay of the equally spaced interlaced signal by the period of the pulse signal can reduce the area of ​​the circuit layout and the power consumption of the circuit, and the delay between signals does not need to be an integer multiple of the clock period. How to generate a delayed output signal based on the pulse signal is a prerequisite for optimizing the method of generating equally spaced interlaced signals. Summary of the invention

[0005] The embodiments of the present application provide a signal output circuit and a delayed signal output circuit for generating a delayed signal with controllable delay according to a first pulse signal and a second pulse signal, and the circuit layout area is small and the power consumption of the circuit is low.

[0006] To solve the above technical problems, an embodiment of the present application provides a signal output circuit, including: a first control module, receiving a first pulse signal and an input signal, and outputting a first adjustment signal, the first preset edge of the first adjustment signal has a first delay relative to the rising edge of the input signal, and the first delay is the pulse period of the first pulse signal; a second control module, receiving a second pulse signal and an input signal, and outputting a second adjustment signal, the second preset edge of the second adjustment signal has a second delay relative to the falling edge of the input signal, and the second delay is the pulse period of the second pulse signal; a signal output module, receiving the first adjustment signal and the second adjustment signal, and outputting a delayed output signal, the rising edge of the delayed output signal is generated based on the first preset edge of the first adjustment signal, and the falling edge of the delayed output signal is generated based on the second preset edge of the second adjustment signal.

[0007] Compared with the related art, a delayed output signal with controllable delay is generated according to the first pulse signal and the second pulse signal. Relative to the input signal, the delayed output signal has a first delay on the rising edge and a second delay on the falling edge. The first delay is the pulse period of the first pulse signal, and the second delay is the pulse period of the second pulse signal. Therefore, the delay time of the delayed output signal can be adjusted by adjusting the pulse periods of the first pulse signal and the second pulse signal. At the same time, the delay time of the delayed output signal does not require the connection of more delay units, thereby simplifying the circuit structure, making the circuit layout area small and the circuit power consumption low.

[0008] In addition, the pulse period of the first pulse signal is equal to the pulse period of the second pulse signal. By controlling the pulse period of the first pulse signal to be consistent with the pulse period of the second pulse signal, the delay time of the rising edge and the falling edge of the generated delayed output signal is ensured to be consistent, thereby ensuring that the delayed output signal is a delay of the input signal.

[0009] In addition, one of the pulses of the first pulse signal is aligned with the rising edge of the input signal, and one of the pulses of the second pulse signal is aligned with the falling edge of the input signal.

[0010] In addition, the first pulse signal and the second pulse signal are interlaced pulse signals.

[0011] In addition, the signal output module includes: a first receiving unit, receiving the first pulse signal and the first adjustment signal, and generating a first pulse control signal when the first adjustment signal is at a valid level, and the pulse phase of the first pulse control signal is the same as the pulse phase of the first pulse signal; a second receiving unit, receiving the second pulse signal and the second adjustment signal, and generating a second pulse control signal when the second adjustment signal is at a valid level, and the pulse phase of the second pulse control signal is the same as the pulse phase of the second pulse signal; a latch unit, receiving the first pulse control signal and the second pulse control signal, and generating a delayed output signal.

[0012] In addition, the first receiving unit is also used to receive the first control signal, and the first receiving unit is used to generate the first pulse control signal according to the first pulse signal during the period when the first adjustment signal and the first control signal are at the effective level. The stability of the output of the first receiving unit is ensured by regulating the first control signal.

[0013] In addition, the first receiving unit includes a first receiving NAND gate, which includes a first input terminal, a second input terminal and a first output terminal, the first input terminal is used to receive a first adjustment signal, the second input terminal is used to receive a first pulse signal, and the first output terminal is used to output a first pulse control signal.

[0014] In addition, the second receiving unit is also used to receive a second control signal, and the second receiving unit is used to generate a second pulse control signal according to the second pulse signal during the period when the second adjustment signal and the second control signal are at an effective level. The stability of the output of the second receiving unit is ensured by regulating the second control signal.

[0015] In addition, the second receiving unit includes a second receiving NAND gate, which includes a third input terminal, a fourth input terminal and a second output terminal. The third input terminal is used to receive the second adjustment signal, the fourth input terminal is used to receive the second pulse signal, and the second output terminal is used to output the second pulse control signal.

[0016] In addition, the latch unit includes: a latch, the latch includes a fifth input terminal, a sixth input terminal and a third output terminal, the fifth input terminal is used to receive the first pulse control signal, the sixth input terminal is used to receive the second pulse control signal, and the third output terminal is used to output a delayed output signal.

[0017] In addition, the latch unit is configured such that: when the first pulse control signal and the second pulse control signal are at different levels, the delayed output signal and the second pulse control signal are at the same level; when the first pulse control signal and the second pulse control signal are at high levels, the latch unit maintains the state.

[0018] In addition, the first control module includes: a first D flip-flop, a clock end for receiving a first pulse signal, a reset end for receiving a first reset signal, an input end for receiving an input signal, and an output end for outputting a first adjustment signal.

[0019] In addition, the second control module includes: a second D flip-flop, a clock end for receiving a second pulse signal, a reset end for receiving a second reset signal, an input end for receiving an input signal, and an output end connected in series with an inverter to output a second adjustment signal.

[0020] In addition, the signal output circuit further includes: an even number of inverters, which are connected in series with the output end of the signal output module to enhance the driving capability of the signal output module.

[0021] An embodiment of the present application also provides a delayed signal output circuit, comprising G of the above-mentioned signal output circuits, where G is an integer greater than or equal to 2; each level of the signal output circuit is used to receive the delayed output signal output by the previous level of the signal output circuit, and generate a delayed output signal of the current level based on the first pulse signal, the second pulse signal and the delayed output signal output by the previous level of the signal output circuit; wherein non-first-level signal output circuits all receive the delayed output signal output by the previous level of the signal output circuit as the input signal of the current level of the signal output circuit, and the first-level signal output circuit receives the initial input signal as the input signal of the first-level signal output circuit; the rising edge of the delayed output signal generated by the signal output circuit has a first delay with the rising edge of the delayed output signal output by the previous level of the signal output circuit; the falling edge of the delayed output signal generated by the signal output circuit has a second delay with the falling edge of the delayed output signal output by the previous level of the signal output circuit.

[0022] In addition, the pulse periods of the first pulse signal and the second pulse signal are equal.

[0023] In addition, the first control module of the signal output circuit is also used to receive a first control signal, and the second control module of the signal output circuit is also used to receive a second control signal, and the first control signal and the second control signal are inverted signals; each level of the signal output circuit is used to generate a delayed output signal of the current level based on the first control signal, the second control signal, the first pulse signal, the second pulse signal and the delayed output signal output by the previous level of the signal output circuit.

[0024] In addition, the delayed signal output circuit also includes: an initial signal output circuit, including a first control module, a second control module and a signal output module; the first control module is used to receive a first pulse signal and a first power signal, and generate a first adjustment signal according to the first pulse signal and the first power signal; the second control module is used to receive a second pulse signal and a second power signal, and generate a second adjustment signal according to the second pulse signal and the second power signal; the signal output module is used to generate an initial input signal according to the first adjustment signal and the second adjustment signal. The input signal generated by the initial signal output circuit is used to reduce the signal delay error caused by the circuit structure and ensure the accuracy of the generated delayed output signal.

[0025] Compared with the related art, a signal output circuit is used to generate a delay signal with controllable delay based on a first pulse signal and a second pulse signal. Relative to the input signal, the delay signal has a first delay on the rising edge and a second delay on the falling edge; other signal output circuits continue to delay the generated delay signal to generate an equally spaced staggered (Stagger) signal; at the same time, there is no need to connect more delay units to adjust the delay time of the delay signal, thereby simplifying the circuit structure, making the circuit layout area small and the circuit power consumption low. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 A schematic diagram of the structure of a signal output circuit provided in one embodiment of the present application;

[0027] Figure 2 A specific circuit diagram of a first control module provided in an embodiment of the present application;

[0028] Figure 3 A specific circuit diagram of a second control module provided in one embodiment of the present application;

[0029] Figure 4 A schematic diagram of the structure of a signal output module provided in one embodiment of the present application;

[0030] Figure 5 and Figure 6 A specific circuit diagram of a signal output module provided in one embodiment of the present application;

[0031] Figure 7 A schematic diagram of the timing of signals in a signal output circuit provided in an embodiment of the present application;

[0032] Figure 8 and Fig. 9 A schematic diagram of the structure of a delayed signal output circuit provided by another embodiment of the present application;

[0033] Fig.10 A specific circuit diagram of a delayed signal output circuit provided by another embodiment of the present application;

[0034] Fig.11 A specific circuit diagram of a signal output circuit in a delayed signal output circuit provided in another embodiment of the present application;

[0035] Fig.12 A schematic diagram of the timing of signals in a delayed signal output circuit provided in another embodiment of the present application. DETAILED DESCRIPTION

[0036] When using synchronous signals to generate equally spaced interleaved signals, the delay between equally spaced interleaved signals must be an integer multiple of the clock period, and the controllability of the delay between equally spaced interleaved signals is poor; when using asynchronous signals to generate equally spaced interleaved signals, although the delay between signals is well controllable, it will significantly increase the area of ​​the circuit layout and the power consumption of the circuit.

[0037] To solve the above problems, an embodiment of the present application provides a signal output circuit, including: a first control module, receiving a first pulse signal and an input signal, and outputting a first adjustment signal, the first preset edge of the first adjustment signal has a first delay relative to the rising edge of the input signal, and the first delay is the pulse period of the first pulse signal; a second control module, receiving a second pulse signal and an input signal, and outputting a second adjustment signal, the second preset edge of the second adjustment signal has a second delay relative to the falling edge of the input signal, and the second delay is the pulse period of the second pulse signal; a signal output module, receiving the first adjustment signal and the second adjustment signal, and outputting a delayed output signal, the rising edge of the delayed output signal is generated based on the first preset edge of the first adjustment signal, and the falling edge of the delayed output signal is generated based on the second preset edge of the second adjustment signal.

[0038] To make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the embodiments of the present application will be described in detail below in conjunction with the accompanying drawings. However, it will be appreciated by those skilled in the art that in the embodiments of the present application, many technical details are proposed in order to enable the reader to better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical scheme claimed in the present application can also be implemented. The division of the following embodiments is for the convenience of description, and the specific implementation of the present application should not be construed as any limitation, and the various embodiments can be combined with each other and quoted from each other without contradiction.

[0039] Figure 1 A schematic diagram of the structure of the signal output circuit provided in this embodiment, Figure 2 A specific circuit diagram of the first control module provided in this embodiment, Figure 3 A specific circuit diagram of the second control module provided in this embodiment, Figure 4 A schematic diagram of the structure of the signal output module provided in this embodiment, Figure 5 and Figure 6 A specific circuit diagram of the signal output module provided in this embodiment, Figure 7 This is a schematic diagram of the timing of signals in the signal output circuit provided in this embodiment. The signal output circuit provided in this embodiment is further described in detail below in conjunction with the accompanying drawings.

[0040] refer to Figure 1The signal output circuit 500 includes: a first control module 501, which receives a first pulse signal ActClk and an input signal ActBnk0, and outputs a first adjustment signal ActLat, wherein a first preset edge of the first adjustment signal ActLat has a first delay relative to a rising edge of the input signal ActBnk0, and the first delay is a pulse period of the first pulse signal ActClk.

[0041] In one example, the rising edge or falling edge of the first pulse signal ActClk can be used to sample the input signal ActBnk0 and then output the first adjustment signal ActLat; or the rising edge or falling edge of the first pulse signal ActClk can be detected and then the input signal ActBnk0 can be outputted with delay, thereby obtaining the first adjustment signal ActLat.

[0042] In this embodiment, the first preset edge is taken as a rising edge as an example for illustration; specifically, the input signal ActBnk0 is an external input signal (compared to the signal output circuit 500), and the signal output circuit 500 is used to generate a delayed output signal ActBnk1 according to the input signal ActBnk0; wherein, the rising edge of the delayed output signal ActBnk1 is generated based on the rising edge of the first adjustment signal ActLat, and the rising edge of the first adjustment signal ActLat has a first delay with the rising edge of the input signal ActBnk0; that is, the rising edge of the delayed output signal ActBnk1 has a first delay with the rising edge of the input signal ActBnk0, and the first delay is the pulse period of the first pulse signal ActClk, from which it can be known that the externally input first pulse signal ActClk is used to adjust the delay of the rising edge of the delayed output signal ActBnk1. It should be noted that in other embodiments, the first preset edge can also be a falling edge.

[0043] It should be noted that in the description of “the rising edge of the delayed output signal ActBnk1 is generated based on the first preset edge of the first adjustment signal ActLat”, the meaning of “based on” includes but is not limited to: the rising edge of the delayed output signal ActBnk1 is generated upon detecting the first preset edge of the first adjustment signal ActLat, or the rising edge of the delayed output signal ActBnk1 is generated after detecting that the first adjustment signal ActLat changes from a low level to a high level (a high level to a low level).

[0044] In one example, refer to Figure 2 The first control module 501 includes a first D flip-flop 511, a clock end for receiving a first pulse signal ActClk, a reset end for receiving a first reset signal fnActEn, an input end for receiving an input signal ActBnk0, and an output end for outputting a first adjustment signal ActLat.

[0045] Continue to refer Figure 1 The signal output circuit 500 also includes: a second control module 502, which receives the second pulse signal PreClk and the input signal ActBnk0, and outputs a second adjustment signal PreLat, wherein the second preset edge of the second adjustment signal PreLat has a second delay relative to the falling edge of the input signal ActBnk0, and the second delay is the pulse period of the second pulse signal PreClk.

[0046] In this embodiment, the second preset edge is taken as a rising edge for example; specifically, the falling edge of the delayed output signal ActBnk1 is generated based on the rising edge of the second adjustment signal PreLat, and the rising edge of the second adjustment signal PreLat and the falling edge of the input signal ActBnk0 have a second delay; that is, the falling edge of the delayed output signal ActBnk1 and the falling edge of the input signal ActBnk0 have a second delay, and the second delay is the pulse period of the second pulse signal PreClk, so it can be known that the externally input second pulse signal PreClk is used to adjust the delay of the falling edge of the delayed output signal ActBnk1. It should be noted that in other embodiments, the second preset edge can also be a falling edge.

[0047] It should be noted that in the description of “the falling edge of the delayed output signal ActBnk1 is generated based on the second preset edge of the second adjustment signal PreLat”, the meaning of “based on” includes but is not limited to: the falling edge of the delayed output signal ActBnk1 is generated when the second preset edge of the second adjustment signal PreLat is detected, or the falling edge of the delayed output signal ActBnk1 is generated after the second adjustment signal PreLat is detected to change from a low level to a high level (a high level to a low level).

[0048] In one example, refer to Figure 3 The second control module 502 includes a second D flip-flop 512, a clock end for receiving a second pulse signal PreClk, a reset end for receiving a second reset signal fnPreEn, an input end for receiving an input signal ActBnk0, and an output end connected in series with an inverter to output a second adjustment signal PreLat.

[0049] In this embodiment, the pulse period of the first pulse signal ActClk is equal to the pulse period of the second pulse signal PreClk, and the delay degree of the rising edge of the first adjustment signal ActLat is the same as the delay degree of the rising edge of the second adjustment signal PreLat. In other embodiments, the pulse periods of the first pulse signal and the second pulse signal may be different.

[0050] In addition, in the present embodiment, one of the pulses of the first pulse signal ActClk is aligned with the rising edge of the input signal ActBnk0, and one of the pulses of the second pulse signal PreClk is aligned with the falling edge of the input signal ActBnk0. It should be noted that the "alignment" described here is not necessarily a perfect alignment under ideal conditions, and may include slight differences in the rising / falling edges due to factors such as circuit delays. By aligning one of the pulses of the first pulse signal ActClk with the rising edge of the input signal ActBnk0, the accuracy of the first delay between the first signal edge of the first adjustment signal ActLat and the rising edge of the input signal ActBnk0 is guaranteed; by aligning one of the pulses of the second pulse signal PreClk with the falling edge of the input signal ActBnk0, the accuracy of the second delay between the second signal edge of the second adjustment signal PreLat and the falling edge of the input signal ActBnk0 is guaranteed. Continue to refer to Figure 1 The signal output circuit 500 also includes: a signal output module 503, which receives the first adjustment signal ActLat and the second adjustment signal PreLat, and outputs a delayed output signal ActBnk1, wherein the rising edge of the delayed output signal ActBnk1 is generated based on the first preset edge of the first adjustment signal ActLat, and the falling edge of the delayed output signal ActBnk1 is generated based on the second preset edge of the second adjustment signal PreLat.

[0051] Specifically, refer to Figure 4 The signal output module 503 includes: a first receiving unit 513, receiving the first pulse signal ActClk and the first adjustment signal ActLat, and generating a first pulse control signal ActN when the first adjustment signal ActLat is at an effective level, wherein the pulse phase of the first pulse control signal ActN is the same as the pulse phase of the first pulse signal ActClk; a second receiving unit 523, receiving the second pulse signal PreClk and the second adjustment signal PreLat, and generating a second pulse control signal PreN when the second adjustment signal PreLat is at an effective level, wherein the pulse phase of the second pulse control signal PreN is the same as the pulse phase of the second pulse signal PreClk. A latch unit 533, receiving the first pulse control signal ActN and the second pulse control signal PreN, and delaying the output signal ActBnk1.

[0052] In one example, when the first adjustment signal ActLat is detected to be at an effective level, a first pulse control signal ActN is generated based on the inverter through the first pulse signal ActClk; when the second adjustment signal PreLat is detected to be at an effective level, a second pulse control signal PreN is generated based on the inverter through the second pulse signal PreClk.

[0053] In one example, refer to Figure 5 The first receiving unit 513 includes a first receiving NAND gate 601, which includes a first input terminal, a second input terminal and a first output terminal, wherein the first input terminal is used to receive the first adjustment signal ActLat, the second input terminal is used to receive the first pulse signal ActClk, and the first output terminal is used to output the first pulse control signal ActN. The second receiving unit 523 includes a second receiving NAND gate 602, which includes a third input terminal, a fourth input terminal and a second output terminal, wherein the third input terminal is used to receive the second adjustment signal PreLat, the fourth input terminal is used to receive the second pulse signal PreClk, and the second output terminal is used to output the second pulse control signal PreN. The latch unit 533 includes a latch 603, which includes a fifth input terminal, a sixth input terminal and a third output terminal, wherein the fifth input terminal is used to receive the first pulse control signal ActN, the sixth input terminal is used to receive the second pulse control signal PreN, and the third output terminal is used to output the delayed output signal ActBnk1.

[0054] The latch unit 603 is configured as follows: when the first pulse control signal ActN and the second pulse control signal PreN are at different levels, the delayed output signal ActBnk1 and the second pulse control signal PreN are at the same level; when the first pulse control signal ActN and the second pulse control signal PreN are at high levels, the latch unit 603 maintains the state.

[0055] Specifically, when the first pulse signal ActN and the second pulse control signal PreN are at a high level, the latch unit 603 maintains the state; when the first pulse control signal ActN is at a high level and the second pulse signal control signal PreN is at a low level, the latch unit 603 outputs a low level; when the first pulse control signal ActN is at a low level and the second pulse signal control signal PreN is at a high level, the latch unit 603 outputs a high level.

[0056] In another example, the first receiving unit 513 is further used to receive the first control signal ActEn, and the first receiving unit 513 is used to generate the first pulse control signal ActN according to the first pulse signal ActClk during the period when the first adjustment signal ActLat and the first control signal ActEn are at the effective level. The second receiving unit 523 is further used to receive the second control signal PreEn, and the second receiving unit 523 is used to generate the second pulse control signal PreN according to the second pulse signal PreClk during the period when the second adjustment signal PreLat and the second control signal PreEn are at the effective level.

[0057] refer to Figure 6, the first receiving NAND gate 601 is also used to receive the first control signal ActEn, and the first receiving NAND gate 601 generates the first pulse control signal ActN according to the first clock signal ActClk, the first control signal ActEn and the first adjustment signal ActLat. The second receiving NAND gate 602 is also used to receive the second control signal PreEn, and the second receiving NAND gate 602 generates the second pulse control signal PreN according to the second clock signal PreClk, the second control signal PreEn and the second adjustment signal PreLat. Among them, the first control signal ActEn and the second control signal PreEn are inverted signals, the first pulse signal ActClk exists during the period when the first control signal ActEn is at an effective level, and the second pulse signal PreClk exists during the period when the second control signal PreEn is at an effective level. The first receiving NAND gate 601 and the second receiving NAND gate receive the first control signal ActEn and the second control signal PreEn respectively, so as to ensure the stability of the output of the first receiving NAND gate 601 and the second receiving NAND gate 602.

[0058] Furthermore, the first pulse signal ActClk and the second pulse signal PreClk are staggered pulse signals, that is, pulse signals generated according to inverted signals; in the present embodiment, the first pulse signal ActClk exists during the period when the first control signal ActEn is at a valid level, and the start pulse of the first pulse signal ActClk is aligned with the rising edge of the first control signal ActEn; the second pulse signal PreClk exists during the period when the second control signal PreEn is at a valid level, and the start pulse of the second pulse signal PreClk is aligned with the rising edge of the second control signal PreEn; it should be noted that the "alignment" described here is not necessarily a perfect alignment under ideal conditions, and may include slight differences in the rising / falling edges due to factors such as circuit delays.

[0059] In one example, refer to Figure 7 , the input signal ActBnk0, the first pulse signal ActClk and the second pulse signal PreClk are external input signals; it is assumed that the period of the first pulse signal ActClk is t1, and the period of the second pulse signal PreClk is t2. Figure 2, the first adjustment signal ActLat is generated based on the input signal ActBnk0 and the first pulse signal ActClk. When the first pulse signal ActClk is at a high level, the next state of the first adjustment signal ActLat is the current state of the input signal ActBnk0, resulting in a first delay between the rising edge of the first adjustment signal ActLat and the rising edge of the input signal ActBnk0. The first delay is the period of the first pulse signal ActClk, that is, the delay between the rising edge of the first adjustment signal ActLat and the rising edge of the input signal ActBnk0 is t1. Figure 3 , the second adjustment signal PreLat is generated based on the input signal ActBnk0 and the second pulse signal PreClk. When the second pulse signal PreClk is at a high level, the next state of the second adjustment signal PreLat is the current state of the input signal ActBnk0, resulting in a second delay between the rising edge of the second adjustment signal PreLat and the falling edge of the input signal ActBnk0. The second delay is the period of the second pulse signal PreClk, that is, the delay between the rising edge of the second adjustment signal PreLat and the falling edge of the input signal ActBnk0 is t2. Combined Figure 6 In order to ensure the stability of the output of the first receiving NAND gate 601 and the second receiving NAND gate 602, the first receiving NAND gate 601 is also used to receive the first control signal ActEn, and the second receiving NAND gate 602 is also used to receive the second control signal PreEn, and the first control signal ActEn and the second control signal PreEn are inverted signals. At this time, the first receiving NAND gate 601 and the second receiving NAND gate 602 respectively generate the first pulse control signal ActN and the second pulse control signal PreN. The latch unit 603 generates a delayed output signal ActBnk1 according to the first pulse control signal ActN and the second pulse control signal PreN. The rising edge of the delayed output signal ActBnk1 has a first delay with the rising edge of the input signal ActBnk0, and the first delay is the pulse period t1 of the first pulse signal ActClk; the falling edge of the delayed output signal ActBnk1 has a second delay with the falling edge of the input signal ActBnk0, and the second delay is the pulse period t2 of the second pulse signal PreClk. In this embodiment, the pulse periods of the first pulse signal ActClk and the second pulse signal PreClk are equal, that is, the signal change edge of the delayed output signal ActBnk1 is delayed by the same time relative to the signal change edge of the input signal ActBnk0. It should be noted that, Figure 7 The timing diagrams of the given signals are only used to interpret the circuit functions of the signal output circuit 500 provided in this embodiment, and do not constitute a limitation of this embodiment; in other embodiments, a corresponding delayed input signal can be generated according to other input signals; in addition, the input signal may also be inconsistent with the first control signal.

[0060] It should be noted that, in other embodiments, the signal output circuit further includes an even number of inverters, and the inverters are connected in series with the output end of the signal output module to enhance the driving capability of the signal output circuit.

[0061] Compared with the related art, a delayed output signal with controllable delay is generated according to the first pulse signal and the second pulse signal. Relative to the input signal, the delayed output signal has a first delay on the rising edge and a second delay on the falling edge. The first delay is the pulse period of the first pulse signal, and the second delay is the pulse period of the second pulse signal. Therefore, the delay time of the delayed output signal can be adjusted by adjusting the pulse periods of the first pulse signal and the second pulse signal. At the same time, the delay time of the delayed output signal does not require the connection of more delay units, thereby simplifying the circuit structure, making the circuit layout area small and the circuit power consumption low.

[0062] It is worth mentioning that all units involved in this embodiment are logical units. In practical applications, a logical unit can be a physical unit, a part of a physical unit, or a combination of multiple physical units. In addition, in order to highlight the innovative part of this application, this embodiment does not introduce units that are not closely related to solving the technical problems proposed by this application, but this does not mean that there are no other units in this embodiment.

[0063] Another embodiment of the present application relates to a delayed signal output circuit, comprising G of the above-mentioned signal output circuits, where G is an integer greater than or equal to 2; each level of the signal output circuit is used to receive the delayed output signal output by the previous level of the signal output circuit, and generate a delayed output signal of the current level based on the first pulse signal, the second pulse signal and the delayed output signal output by the previous level of the signal output circuit; wherein non-first-level signal output circuits all receive the delayed output signal output by the previous level of the signal output circuit as the input signal of the current level of the signal output circuit, and the first-level signal output circuit receives the initial input signal as the input signal of the first-level signal output circuit; the rising edge of the delayed output signal generated by the signal output circuit has a first delay with the rising edge of the delayed output signal output by the previous level of the signal output circuit; the falling edge of the delayed output signal generated by the signal output circuit has a second delay with the falling edge of the delayed output signal output by the previous level of the signal output circuit.

[0064] Figure 8 and Fig. 9 A schematic diagram of the structure of the delayed signal output circuit provided in this embodiment, Fig.10 A specific circuit diagram of the delayed signal output circuit provided in this embodiment, Fig.11 A specific circuit diagram of the signal output circuit in the delayed signal output circuit provided in this embodiment, Fig.12This is a timing diagram of signals in the delayed signal output circuit provided in the present embodiment. The delayed signal output circuit provided in the present embodiment will be described in detail below in conjunction with the accompanying drawings, and the parts that are the same or corresponding to the above embodiments will not be described in detail below.

[0065] A delayed signal output circuit comprises: G signal output circuits 500 of the above-mentioned embodiments, where G is an integer greater than or equal to 2; each level of the signal output circuit is used to receive the delayed output signal output by the previous level of the signal output circuit, and generate the delayed output signal of the current level based on the first pulse signal ActClk, the second pulse signal PreClk and the delayed output signal output by the previous level of the signal output circuit; wherein non-first level signal output circuits all receive the delayed output signal output by the previous level of the signal output circuit as the input signal of the current level of the signal output circuit, and the first level signal output circuit receives the initial input signal as the input signal of the first level of the signal output circuit; the rising edge of the delayed output signal generated by the signal output circuit has a first delay with the rising edge of the delayed output signal output by the previous level of the signal output circuit; the falling delay of the delayed output signal generated by the signal output circuit has a second delay with the falling edge of the delayed output signal output by the previous level of the signal output circuit.

[0066] In this embodiment, the pulse period of the first pulse signal ActClk is t1, the pulse period of the second pulse signal PreClk is t2, and the pulse period of the first pulse signal ActClk is equal to the pulse period of the second pulse signal PreClk; in other embodiments, the pulse periods of the first pulse signal and the second pulse signal may be different.

[0067] refer to Figure 8 In this embodiment, the delayed signal output circuit 700 includes 7 signal output circuits 500 provided in the above embodiment as an example for specific description, which does not constitute a limitation of this embodiment, specifically, a first-level signal output circuit 701, a second-level signal output circuit 702, a third-level signal output circuit 703, a fourth-level signal output circuit 704, a fifth-level signal output circuit 705, a sixth-level signal output circuit 706, and a seventh-level signal output circuit 707. In other embodiments, the delayed signal output circuit includes more than or equal to 2 signal output circuits.

[0068] Specifically, the first-stage signal output circuit 701 generates a first-stage delayed output signal ActBnk1 according to the initial input signal ActBnk0, the first pulse signal ActClk and the second pulse signal PreClk. The rising edge of the first-stage delayed output signal ActBnk1 has a first delay relative to the rising edge of the initial input signal ActBnk0, and the first delay is the pulse period t1 of the first pulse signal ActClk; the falling edge of the first-stage delayed output signal ActBnk1 has a second delay relative to the falling edge of the initial input signal ActBnk0, and the second delay is the pulse period t2 of the second pulse signal PreClk.

[0069] The second-stage signal output circuit 702 generates a second-stage delayed output signal ActBnk2 according to the first-stage delayed output signal ActBnk1, the first pulse signal ActClk and the second pulse signal PreClk. The rising edge of the second-stage delayed output signal ActBnk2 has a first delay relative to the first-stage delayed output signal ActBnk1; the falling edge of the second-stage delayed output signal ActBnk2 has a second delay relative to the first-stage delayed output signal ActBnk1.

[0070] The third-level signal output circuit 703 generates a third-level delayed output signal ActBnk3 according to the second-level delayed output signal ActBnk2, the first pulse signal ActClk and the second pulse signal PreClk. The rising edge of the third-level delayed output signal ActBnk3 has a first delay relative to the second-level delayed output signal ActBnk2; the falling edge of the third-level delayed output signal ActBnk3 has a second delay relative to the second-level delayed output signal ActBnk2.

[0071] The fourth-level signal output circuit 704 generates a fourth-level delayed output signal ActBnk4 according to the third-level delayed output signal ActBnk3, the first pulse signal ActClk and the second pulse signal PreClk. The rising edge of the fourth-level delayed output signal ActBnk4 has a first delay relative to the third-level delayed output signal ActBnk3; the falling edge of the fourth-level delayed output signal ActBnk4 has a second delay relative to the third-level delayed output signal ActBnk3.

[0072] The fifth-level signal output circuit 705 generates a fifth-level delayed output signal ActBnk5 according to the fourth-level delayed output signal ActBnk4, the first pulse signal ActClk and the second pulse signal PreClk. The rising edge of the fifth-level delayed output signal ActBnk5 has a first delay relative to the fourth-level delayed output signal ActBnk4; the falling edge of the fifth-level delayed output signal ActBnk5 has a second delay relative to the fourth-level delayed output signal ActBnk4.

[0073] The sixth-level signal output circuit 706 generates a sixth-level delayed output signal ActBnk6 according to the fifth-level delayed output signal ActBnk5, the first pulse signal ActClk and the second pulse signal PreClk. The rising edge of the sixth-level delayed output signal ActBnk6 has a first delay relative to the fifth-level delayed output signal ActBnk5; the falling edge of the sixth-level delayed output signal ActBnk6 has a second delay relative to the fifth-level delayed output signal ActBnk5.

[0074] The seventh-level signal output circuit 707 generates a seventh-level delayed output signal ActBnk7 according to the sixth-level delayed output signal ActBnk6, the first pulse signal ActClk and the second pulse signal PreClk. The rising edge of the seventh-level delayed output signal ActBnk7 has a first delay relative to the sixth-level delayed output signal ActBnk6; the falling edge of the seventh-level delayed output signal ActBnk7 has a second delay relative to the sixth-level delayed output signal ActBnk6.

[0075] refer to Fig. 9 More specifically, in this embodiment, the first control module of the signal output circuit is also used to receive the first control signal ActEn, and the second control module of the signal output circuit is also used to receive the second control signal PreEn, wherein the first pulse signal ActClk and the second pulse signal PreClk are inverted signals; each level of the signal output circuit is used to generate a delayed output signal of the current level according to the first control signal ActEn, the second control signal PreEn, the first pulse signal ActClk, the second pulse signal PreClk and the delayed output signal output by the previous level of the signal output circuit, and by receiving the first control signal ActEn and the second control signal PreEn, the stability of the output of the signal output circuit is ensured.

[0076] Continue to refer Fig. 9In this embodiment, the delayed signal output circuit 700 further includes: an initial signal output circuit 710, including a first control module, a second control module and a signal output module; the first control module is used to receive the first pulse signal ActClk and the first power signal Vdd, and generate a first adjustment signal (not shown) according to the first pulse signal ActClk and the first power signal Vdd; the second control module of the output signal output circuit is used to receive the second pulse signal PreClk and the second power signal Vss, and generate a second adjustment signal (not shown) according to the second pulse signal PreClk and the second power signal Vss; the signal output module is used to generate the initial input signal according to the first adjustment signal (not shown) and the second adjustment signal (not shown). The delayed output signal of the initial signal output circuit generated according to the first power signal Vdd and the second power signal Vss, that is, the initial input signal ActBnk0 outputted by the initial signal output circuit 710 can avoid the delay caused by the circuit elements of the signal output circuit compared with the initial input signal ActBnk0 directly inputted from the outside. The circuit of the initial signal output circuit 710 here may be consistent with the signal output circuit described above, and will not be described in detail here, but this embodiment is not limited to this.

[0077] In one example, refer to Fig.10 and Fig.11 , the figure takes the delayed signal output circuit 700 composed of four signal output circuits as an example for introduction. The first clock terminal ActClk of the signal output circuit is used to receive the first pulse signal ActClk; the second clock terminal PreClk of the signal output circuit is used to receive the second pulse signal PreClk; the first control terminal ActEn of the signal output circuit is used to receive the first control signal ActEn; the second control terminal PreEn of the signal output circuit is used to receive the second control signal PreEn; the signal output terminal ActBnk of the signal output circuit is used to output the delayed output signal of the current stage; the signal output circuit also includes a first signal terminal ActEnPre and a second signal terminal PreEnPre (a signal input terminal of the signal output circuit), combined with Fig.11 The first signal terminal ActEnPre of the initial signal output circuit is used to receive the first power signal Vdd, and the second signal terminal PreEnPre of the initial signal output circuit is used to receive the second power signal Vss; the first signal terminal ActEnPre and the second signal terminal PreEnPre of other signal output circuits are used to receive the delayed output signal output by the previous stage signal output circuit.

[0078] refer to Fig. 9 and Fig.12According to the previous embodiment, the first-stage signal output circuit 701 generates a first-stage delayed output signal ActBnk1 according to the initial input signal ActBnk0, the second-stage signal output circuit 702 generates a second-stage delayed output signal ActBnk2 according to the first-stage delayed output signal ActBnk1, the third-stage signal output circuit 703 generates a third-stage delayed output signal ActBnk3 according to the second-stage delayed output signal ActBnk2, and the fourth-stage signal output circuit 704 generates a third-stage delayed output signal ActBnk3 according to the third-stage delayed output signal ActBnk4. A fourth-level delayed output signal ActBnk4 (not shown) is generated, the fifth-level signal output circuit 705 generates a fifth-level delayed output signal ActBnk5 (not shown) according to the fourth-level delayed output signal ActBnk4, the sixth-level signal output circuit 706 generates a sixth-level delayed output signal ActBnk6 (not shown) according to the fifth-level delayed output signal ActBnk5, and the seventh-level signal output circuit 707 generates a seventh-level delayed output signal ActBnk7 (not shown) according to the sixth-level delayed output signal ActBnk6.

[0079] Compared with the related art, a signal output circuit is used to generate a delay signal with controllable delay according to a first pulse signal and a second pulse signal. Relative to the input signal, the delay signal has a first delay on the rising edge and a second delay on the falling edge; other signal output circuits continue to delay the generated delay signal, thereby generating an equally spaced staggered (Stagger) signal; at the same time, there is no need to connect more delay units to adjust the delay time of the delay signal, thereby simplifying the circuit structure, making the circuit layout area small and the circuit power consumption low.

[0080] It is worth mentioning that all units involved in this embodiment are logical units. In practical applications, a logical unit can be a physical unit, a part of a physical unit, or a combination of multiple physical units. In addition, in order to highlight the innovative part of this application, this embodiment does not introduce units that are not closely related to solving the technical problems proposed by this application, but this does not mean that there are no other units in this embodiment.

[0081] Since the above embodiments correspond to this embodiment, this embodiment can be implemented in conjunction with the above embodiments. The relevant technical details mentioned in the above embodiments are still valid in this embodiment, and the technical effects that can be achieved in the above embodiments can also be achieved in this embodiment. In order to reduce repetition, they are not repeated here. Accordingly, the relevant technical details mentioned in this embodiment can also be applied in the above embodiments.

[0082] Those skilled in the art will appreciate that the above embodiments are specific embodiments for implementing the present application, and in actual applications, various changes may be made thereto in form and detail without departing from the spirit and scope of the present application.

Claims

1. A signal output circuit, characterized in that: include: A first control module receives a first pulse signal and an input signal, and outputs a first adjustment signal, wherein a first preset edge of the first adjustment signal has a first delay relative to a rising edge of the input signal, and the first delay is a pulse period of the first pulse signal; a second control module, receiving a second pulse signal and the input signal, and outputting a second adjustment signal, wherein a second preset edge of the second adjustment signal has a second delay relative to a falling edge of the input signal, and the second delay is a pulse period of the second pulse signal; A signal output module receives the first adjustment signal and the second adjustment signal, and outputs a delayed output signal, wherein a rising edge of the delayed output signal is generated based on a first preset edge of the first adjustment signal, and a falling edge of the delayed output signal is generated based on a second preset edge of the second adjustment signal.

2. The signal output circuit according to claim 1, characterized in that: A pulse period of the first pulse signal is equal to a pulse period of the second pulse signal.

3. The signal output circuit according to claim 1, characterized in that: One pulse of the first pulse signal is aligned with a rising edge of the input signal, and one pulse of the second pulse signal is aligned with a falling edge of the input signal.

4. The signal output circuit according to claim 3, characterized in that: The first pulse signal and the second pulse signal are interlaced pulse signals.

5. The signal output circuit according to claim 1, characterized in that: The signal output module comprises: a first receiving unit, receiving the first pulse signal and the first adjustment signal, and generating a first pulse control signal during a period when the first adjustment signal is at a valid level, wherein a pulse phase of the first pulse control signal is the same as a pulse phase of the first pulse signal; a second receiving unit, receiving the second pulse signal and the second adjustment signal, and generating a second pulse control signal during a period when the second adjustment signal is at a valid level, wherein a pulse phase of the second pulse control signal is the same as a pulse phase of the second pulse signal; A latch unit receives the first pulse control signal and the second pulse control signal, and generates the delayed output signal.

6. The signal output circuit according to claim 5, characterized in that: The first receiving unit is further configured to receive a first control signal, and the first receiving unit is configured to generate the first pulse control signal according to the first pulse signal during a period in which the first adjustment signal and the first control signal are at valid levels.

7. The signal output circuit according to claim 5, characterized in that: The first receiving unit includes a first receiving NAND gate, which includes a first input terminal, a second input terminal and a first output terminal, the first input terminal is used to receive the first adjustment signal, the second input terminal is used to receive the first pulse signal, and the first output terminal is used to output the first pulse control signal.

8. The signal output circuit according to claim 5, characterized in that: The second receiving unit is further configured to receive a second control signal, and the second receiving unit is configured to generate the second pulse control signal according to the second pulse signal during a period in which the second adjustment signal and the second control signal are at valid levels.

9. The signal output circuit according to claim 5, characterized in that: The second receiving unit includes a second receiving NAND gate, which includes a third input terminal, a fourth input terminal and a second output terminal, the third input terminal is used to receive the second adjustment signal, the fourth input terminal is used to receive the second pulse signal, and the second output terminal is used to output the second pulse control signal.

10. The signal output circuit according to claim 5, characterized in that: The latch unit includes: a latch, the latch includes a fifth input terminal, a sixth input terminal and a third output terminal, the fifth input terminal is used to receive the first pulse control signal, the sixth input terminal is used to receive the second pulse control signal, and the third output terminal is used to output the delayed output signal.

11. The signal output circuit according to claim 10, characterized in that: The latch unit is configured as: When the first pulse control signal and the second pulse control signal are at different levels, the delayed output signal and the second pulse control signal are at the same level; When the first pulse control signal and the second pulse control signal are at a high level, the latch unit maintains a state.

12. The signal output circuit according to claim 1, characterized in that: The first control module includes: a first D flip-flop, a clock end for receiving the first pulse signal, a reset end for receiving a first reset signal, an input end for receiving the input signal, and an output end for outputting the first adjustment signal.

13. The signal output circuit according to claim 1, characterized in that: The second control module includes: a second D flip-flop, a clock end for receiving the second pulse signal, a reset end for receiving the second reset signal, an input end for receiving the input signal, and an output end connected in series with an inverter to output the second adjustment signal.

14. The signal output circuit according to claim 1, characterized in that: Also includes: An even number of inverters are connected in series with the output end of the signal output module.

15. A delayed signal output circuit, characterized in that: Comprising G signal output circuits according to any one of claims 1 to 14, wherein G is an integer greater than or equal to 2; Each stage of the signal output circuit is used to receive the delayed output signal output by the previous stage of the signal output circuit, and generate the delayed output signal of the current stage based on the first pulse signal, the second pulse signal and the delayed output signal output by the previous stage of the signal output circuit; Among them, the non-first-stage signal output circuits all receive the delayed output signal output by the previous-stage signal output circuit as the input signal of the current-stage signal output circuit, and the first-stage signal output circuit receives the initial input signal as the input signal of the first-stage signal output circuit; The rising edge of the delayed output signal generated by the signal output circuit has a first delay with the rising edge of the delayed output signal output by the previous stage signal output circuit; There is a second delay between the falling edge of the delayed output signal generated by the signal output circuit and the falling edge of the delayed output signal output by the previous stage signal output circuit.

16. The delayed signal output circuit according to claim 15, characterized in that: The pulse periods of the first pulse signal and the second pulse signal are equal.

17. The delayed signal output circuit according to claim 15, characterized in that: The first control module of the signal output circuit is further used to receive a first control signal, and the second control module of the signal output circuit is further used to receive a second control signal, wherein the first control signal and the second control signal are inverted signals; Each level of signal output circuit is used to generate the delayed output signal of the current level according to the first control signal, the second control signal, the first pulse signal, the second pulse signal and the delayed output signal output by the previous level of signal output circuit.

18. The delayed signal output circuit according to claim 15, characterized in that: Also includes: An initial signal output circuit comprises a first control module, a second control module and a signal output module; The first control module is used to receive a first pulse signal and a first power signal, and generate the first adjustment signal according to the first pulse signal and the first power signal; The second control module is used to receive a second pulse signal and a second power signal, and generate the second adjustment signal according to the second pulse signal and the second power signal; The signal output module is used to generate the initial input signal according to the first adjustment signal and the second adjustment signal.

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