Preparation method of optical modulator based on high aspect ratio silicon dioxide micro-nano structure

Abstract

The present disclosure provides a method for preparing an optical modulator based on a silicon dioxide micro-nano structure with a high aspect ratio, comprising: etching the front of a silicon wafer to form a silicon micro-nano structure array; etching or corroding the back of a silicon wafer to completely release the silicon micro-nano structure array, and forming a support structure at the periphery of the silicon micro-nano structure array; thermally oxidizing the silicon wafer to oxidize silicon into silicon dioxide; depositing a transparent electrode layer on the surface of the silicon wafer subjected to thermal oxidation; taking another glass wafer, processing a filling liquid inlet and outlet on the glass wafer, and depositing a transparent electrode layer on one side of the glass wafer; bonding the side of the glass wafer with the transparent electrode layer deposited thereon to the support structure at the periphery of the silicon dioxide micro-nano structure array to form a closed cavity. The present disclosure utilizes etching combined with a thermal oxidation process to achieve the preparation of a silicon dioxide micro-nano structure array with a high aspect ratio, thereby obtaining an optical modulator with a high aspect ratio.

Description

Technical Field

[0001] The present invention relates to the technical field of micro-nano electromechanical system manufacturing, and in particular to a method for preparing an optical modulator based on a high aspect ratio silicon dioxide micro-nano structure. Background Art

[0002] Lensless imaging technology has become an important development direction for visual inspection equipment due to its advantages such as being lighter, more integrated, lower cost, and more stable. Existing lensless technologies attempt to use optical devices such as coded masks, diffractive optical elements, and optical modulators to replace physical lenses to complete the functions of light transmission and scene focusing. Optical modulators based on glass microstructure arrays have preliminarily verified the feasibility of optical modulator transmittance adjustment, and the aspect ratio of the glass microstructure array directly affects the spatial resolution and spatial modulation range of optical imaging, but the aspect ratio of existing glass microstructure arrays is difficult to meet the needs of a larger spatial modulation range.

[0003] The processes currently used to prepare high aspect ratio silicon dioxide micro-nano structures mainly include dry etching process and glass thermal reflow process. Among them, the dry etching process obtains high aspect ratio micro-nano structures by reactive ion etching of glass or silicon dioxide layer. This process is often slow and costly. The glass thermal reflow process uses anodic bonding plus high temperature annealing or glass powder filling and reflow, which is an effective means to prepare glass microstructures, but there are still problems such as relatively long processing time and difficult control of the glass structure release process, which restricts the possibility of preparing high aspect ratio micro-nano structures. Summary of the invention

[0004] 1. Technical issues to be resolved

[0005] In view of this, the main purpose of the present disclosure is to provide a method for preparing an optical modulator based on a high aspect ratio silicon dioxide micro-nano structure, so as to at least partially solve the above technical problems.

[0006] (II) Technical solution

[0007] According to one aspect of the present disclosure, a method for preparing an optical modulator based on a high aspect ratio silicon dioxide micro-nanostructure is provided, comprising:

[0008] Etching the front side of the silicon wafer to form a silicon micro-nano structure array;

[0009] Etching or corroding the back side of the silicon wafer to completely release the silicon micro-nano structure array on the front side of the silicon wafer, and forming a supporting structure around the silicon micro-nano structure array;

[0010] Thermally oxidizing the silicon wafer on which the silicon micro-nano structure array is completely released and the support structure is formed, oxidizing the silicon micro-nano structure array into a silicon dioxide micro-nano structure array, and oxidizing the silicon on the surface of the support structure into silicon dioxide;

[0011] Depositing a transparent electrode layer on the surface of a silicon wafer subjected to thermal oxidation treatment;

[0012] Taking another glass disc, processing a filling liquid inlet and outlet on the glass disc, and depositing a transparent electrode layer on one side of the glass disc; and

[0013] The side of the glass wafer with the transparent electrode layer deposited thereon is bonded to the supporting structure around the silicon dioxide micro-nanostructure array to form a closed cavity.

[0014] In some embodiments, the etching of the front side of the silicon wafer to form a silicon micro-nano structure array includes: selecting a double-surface polished silicon wafer, using a metal layer on the front side of the silicon wafer as a mask, and adopting a deep reactive ion etching process (Deep-Reactive Ion Etching, D-RIE) or a metal-assisted chemical etching process (Metal-Assisted Chemical Etching, MACE) to etch a silicon micro-nano structure array of equal size and consistent spacing on the silicon wafer.

[0015] In some embodiments, the thickness of the double-surface polished silicon wafer is 200 μm to 500 μm; the metal layer used as a mask is made of titanium / gold or silver, with a thickness of 5 nm to 100 nm; wherein the metal layer can be made of silver alone; since gold is easy to fall off when the metal layer is made of gold alone, the metal layer is made of titanium / gold, and titanium is used as a bonding layer to prevent gold from falling off. In the silicon micro-nano structure array, the width of the silicon groove is 10 nm to 10 μm, and the spacing between adjacent silicon grooves is 10 nm to 10 μm.

[0016] In some embodiments, after forming the silicon micro-nano structure array, the method further includes: removing the metal layer mask in the silicon micro-nano structure array.

[0017] In some embodiments, the etching or corrosion of the back side of the silicon wafer completely releases the silicon micro-nano structure array on the front side of the silicon wafer, and at the same time forms a support structure around the periphery of the silicon micro-nano structure array, including: etching a cavity on the back side of the silicon wafer using an etching or corrosion process until the silicon micro-nano structure array on the front side of the silicon wafer is completely released, and at the same time forms a support structure around the periphery of the silicon micro-nano structure array.

[0018] In some embodiments, the etching process adopts a deep reactive ion etching process D-RIE, and the corrosion process adopts a wet corrosion process of potassium hydroxide KOH or tetramethylammonium hydroxide TMAH solution; the supporting structure is a square ring structure, and the silicon micro-nano structure arrays are all located in the square ring structure, and the thickness of the supporting structure is consistent with the thickness of the silicon wafer.

[0019] In some embodiments, the silicon wafer from which the silicon micro-nano structure array is completely released and the supporting structure is formed is subjected to thermal oxidation treatment to oxidize the silicon micro-nano structure array into a silicon dioxide micro-nano structure array, and at the same time, the silicon on the surface of the supporting structure is oxidized into silicon dioxide, including: placing the silicon wafer from which the silicon micro-nano structure array is completely released and the supporting structure is formed into an oxidation furnace for one or more thermal oxidation treatments, the thermal oxidation temperature being 850°C to 1100°C, until the silicon in the silicon micro-nano structure array is completely oxidized into silicon dioxide, that is, the silicon micro-nano structure array is oxidized into a silicon dioxide micro-nano structure array, and at the same time, the silicon on the surface of the supporting structure is oxidized into silicon dioxide.

[0020] In some embodiments, after the silicon wafer with the silicon micro-nano structure array completely released and formed into a support structure is subjected to thermal oxidation treatment, the method further includes: adjusting the size of the silicon dioxide micro-nano structure array by hydrofluoric acid wet etching.

[0021] In some embodiments, the transparent electrode layer deposited on the surface of the silicon wafer subjected to thermal oxidation treatment and the transparent electrode layer deposited on one side of the glass wafer are made of the same material. The material used for the transparent electrode layer is indium tin oxide (ITO) or aluminum doped zinc oxide (AZO), and the thickness of the transparent electrode layer is 1 nm to 50 nm.

[0022] In some embodiments, the transparent electrode layer is deposited on the surface of the thermally oxidized silicon wafer by atomic layer deposition (ALD); and the transparent electrode layer is deposited on one side of the glass wafer by atomic layer deposition ALD or sputtering.

[0023] In some embodiments, the filling liquid inlet and outlet are processed on the glass wafer by wet etching, laser drilling or sandblasting.

[0024] In some embodiments, the step of bonding the side of the glass wafer on which the transparent electrode layer is deposited to the supporting structure around the silicon dioxide micro-nano structure array is performed by anodic bonding or polyimide bonding.

[0025] According to another aspect of the present disclosure, there is provided an optical modulator based on a high aspect ratio silica micro-nano structure, which is prepared using the method for preparing an optical modulator based on a high aspect ratio silica micro-nano structure.

[0026] (III) Beneficial effects

[0027] It can be seen from the above technical solutions that the method for preparing an optical modulator based on a high aspect ratio silicon dioxide micro-nanostructure provided by the present disclosure has at least the following beneficial effects:

[0028] 1. By using the present disclosure, etching combined with thermal oxidation process is used to realize the preparation of silicon dioxide micro-nano structure array with high aspect ratio, and silicon dioxide micro-nano structure array with high aspect ratio can be obtained, thereby obtaining an optical modulator with high aspect ratio.

[0029] 2. By utilizing the present disclosure, an etching combined with a thermal oxidation process is used to obtain a glass microstructure array, thereby reducing the structural instability caused by the internal stress generated by the thermal reflow of the glass, and reducing the steps of etching or corroding the silicon structure. The molding quality of the micro-nano structure is higher and the process scheme is relatively simpler.

[0030] 3. The etching combined with thermal oxidation process used in the preparation of silicon dioxide micro-nanostructure arrays using the present disclosure is fully compatible with the Micro-Electro-Mechanical Systems (MEMS) process and is suitable for batch manufacturing. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The above and other objects, features and advantages of the present disclosure will become more apparent through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0032] Figure 1 The present invention is a flow chart of a method for preparing an optical modulator based on a high aspect ratio silicon dioxide micro-nanostructure according to an embodiment of the present disclosure.

[0033] Figure 2 FIG. 4 is a schematic diagram of manufacturing a high aspect ratio silicon dioxide micro-nanostructure array on a silicon wafer according to an embodiment of the present disclosure.

[0034] Figure 3 A schematic diagram of etching or corroding the back side of a silicon wafer according to an embodiment of the present disclosure to completely release the silicon micro-nano structure array and simultaneously forming a support structure around the silicon micro-nano structure array.

[0035] Figure 4 It is a schematic diagram of performing thermal oxidation treatment on a silicon wafer after the silicon micro-nano structure array is completely released and a support structure is formed according to an embodiment of the present disclosure.

[0036] Figure 5 It is a schematic diagram of depositing a transparent electrode layer on the surface of a silicon micro-nano structure array and depositing a transparent electrode layer on one side of a glass wafer according to an embodiment of the present disclosure.

[0037] Figure 6 The schematic diagram is a diagram of bonding one side of a glass wafer with a transparent electrode layer deposited thereon to a supporting structure at the periphery of a silicon dioxide micro-nanostructure array to form an optical modulator with a closed cavity according to an embodiment of the present disclosure.

[0038] [Description of Reference Numerals]

[0039] 100-silicon wafer; 101-silicon groove;

[0040] 201-cavity;

[0041] 301-silicon dioxide;

[0042] 401, 402-transparent electrodes;

[0043] 501- glass disc; 502- filling liquid inlet and outlet. DETAILED DESCRIPTION

[0044] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present disclosure. In the following detailed description, for ease of explanation, many specific details are set forth to provide a comprehensive understanding of the embodiments of the present disclosure. However, it is apparent that one or more embodiments may also be implemented without these specific details. In addition, in the following description, descriptions of known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.

[0045] All terms (including technical and scientific terms) used herein have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification, and should not be interpreted in an idealized or overly rigid manner.

[0046] Moreover, the shapes and sizes of the components in the figures do not reflect the real size and proportion, but only illustrate the contents of the embodiments of the present disclosure. In addition, in the claims, any reference symbols between brackets shall not be constructed as limiting the claims.

[0047] Furthermore, the word "comprising" or "including" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements.

[0048] In view of the defects and shortcomings of the current dry etching process and glass thermal reflow process, the present invention utilizes etching combined with a thermal oxidation process to achieve the preparation of a high aspect ratio silicon dioxide micro-nano structure array, which can obtain a high aspect ratio silicon dioxide micro-nano structure array, and then obtain a high aspect ratio optical modulator.

[0049] In the preparation method of an optical modulator based on a high aspect ratio silicon dioxide micro-nano structure provided in the present invention, the etching combined with thermal oxidation process uses a deep reactive ion etching process D-RIE or a metal-assisted chemical etching process MACE to first etch out a silicon micro-nano structure, and then the prepared silicon micro-nano structure is thermally oxidized to obtain a silicon dioxide micro-nano structure. This process has the advantages of good compatibility with a micro-electromechanical system MEMS process and a relatively easy preparation process.

[0050] like Figure 1 As shown, Figure 1 The method for preparing an optical modulator based on a high aspect ratio silicon dioxide micro-nanostructure according to an embodiment of the present disclosure is a flow chart, and the method comprises the following steps:

[0051] Step S1: etching the front side of the silicon wafer to form a silicon micro-nano structure array;

[0052] Step S2: etching or corroding the back side of the silicon wafer to completely release the silicon micro-nano structure array on the front side of the silicon wafer, and forming a support structure around the silicon micro-nano structure array;

[0053] Step S3: thermally oxidizing the silicon wafer from which the silicon micro-nano structure array is completely released and the support structure is formed, oxidizing the silicon micro-nano structure array into a silicon dioxide micro-nano structure array, and oxidizing the silicon on the surface of the support structure into silicon dioxide;

[0054] Step S4: depositing a transparent electrode layer on the surface of the silicon wafer subjected to thermal oxidation treatment;

[0055] Step S5: taking another glass disc, processing a filling liquid inlet and outlet on the glass disc, and depositing a transparent electrode layer on one side of the glass disc;

[0056] Step S6: bonding the side of the glass wafer on which the transparent electrode layer is deposited to the supporting structure around the silicon dioxide micro-nano structure array to form a closed cavity.

[0057] In an embodiment of the present disclosure, etching the front side of the silicon wafer in step S1 to form a silicon micro-nano structure array includes: selecting a double-surface polished silicon wafer, using a metal layer as a mask on the front side of the silicon wafer, and using a deep reactive ion etching process D-RIE or a metal-assisted chemical etching process MACE to etch a silicon micro-nano structure array of equal size and consistent spacing on the silicon wafer. The thickness of the double-surface polished silicon wafer is 200μm to 500μm, and optionally, the thickness of the silicon wafer is 300μm. The metal layer used as a mask is titanium / gold or silver, and the thickness is 5nm to 100nm. Among them, the metal layer can be made of silver alone; since gold is easy to fall off when the metal layer is made of gold alone, the metal layer is made of titanium / gold, and titanium is used as a bonding layer to prevent gold from falling off. In the silicon micro-nano structure array, the silicon grooves adopt a hollow cylindrical structure or a hollow polygonal columnar structure, for example, a plurality of silicon grooves with equal width and consistent spacing constitute the silicon micro-nano structure array; or the silicon grooves in the silicon micro-nano structure array adopt a silicon array structure containing a cylindrical body or a silicon array structure containing a polygonal columnar body, for example, the gaps between a plurality of cylindrical silicon or polygonal columnar silicon constitute the silicon micro-nano structure array. The width of the silicon groove is 10nm to 10μm, and the spacing between adjacent silicon grooves is 10nm to 10μm.

[0058] In the embodiment of the present disclosure, after etching the front side of the silicon wafer to form the silicon micro-nano structure array in step S1, the step further includes: removing the metal layer mask in the silicon micro-nano structure array.

[0059] In an embodiment of the present disclosure, the back side of the silicon wafer is etched or corroded in step S2 to completely release the silicon micro-nano structure array on the front side of the silicon wafer, and at the same time, a support structure is formed around the silicon micro-nano structure array, including: etching a cavity on the back side of the silicon wafer using an etching or corrosion process until the silicon micro-nano structure array on the front side of the silicon wafer is completely released, and at the same time, a support structure is formed around the silicon micro-nano structure array.

[0060] In this step, the etching process adopts a deep reactive ion etching process D-RIE, and the corrosion process adopts a wet etching process of potassium hydroxide KOH or tetramethylammonium hydroxide TMAH solution. The support structure is a square ring structure, and the silicon micro-nano structure arrays are all located in the square ring structure. The thickness of the support structure is consistent with the thickness of the silicon wafer.

[0061] In an embodiment of the present disclosure, step S3 is described in which the silicon wafer with the silicon micro-nano structure array completely released and the supporting structure formed is subjected to thermal oxidation treatment to oxidize the silicon micro-nano structure array into a silicon dioxide micro-nano structure array, and at the same time, the silicon on the surface of the supporting structure is oxidized into silicon dioxide, including: placing the silicon wafer with the silicon micro-nano structure array completely released and the supporting structure formed into an oxidation furnace for one or more thermal oxidation treatments, the thermal oxidation temperature being 850°C to 1100°C, until the silicon in the silicon micro-nano structure array is completely oxidized into silicon dioxide, that is, the silicon micro-nano structure array is oxidized into a silicon dioxide micro-nano structure array, and at the same time, the silicon on the surface of the supporting structure is oxidized into silicon dioxide.

[0062] In this step, after the silicon wafer that completely releases the silicon micro-nano structure array and forms the support structure is subjected to thermal oxidation treatment, the size of the silicon dioxide micro-nano structure array is adjusted by hydrofluoric acid wet etching. Here, the size of the silicon dioxide micro-nano structure array is mainly adjusted, and the size of the silicon dioxide micro-nano structure array can be adjusted by hydrofluoric acid wet etching. Specifically, the size of the silicon dioxide micro-nano structure array can be adjusted in one step by hydrofluoric acid wet etching of silicon dioxide. It is also possible to adjust the size of the silicon dioxide micro-nano structure array by thermal oxidation, wet etching, re-thermal oxidation, re-wet etching and other multiple cycles in the process of silicon in the silicon dioxide micro-nano structure array being oxidized to silicon dioxide, and then thermal oxidation to form a silicon dioxide micro-structure array of suitable size. Of course, if the size of the silicon dioxide micro-nano structure array is suitable after thermal oxidation, the size of the silicon dioxide micro-nano structure array may not be adjusted.

[0063] In an embodiment of the present disclosure, the transparent electrode layer deposited on the surface of the silicon wafer subjected to thermal oxidation treatment in step S4 and the transparent electrode layer deposited on one side of the glass wafer are made of the same material. Optionally, the material used for the transparent electrode layer is indium tin oxide ITO or aluminum-doped zinc oxide AZO, and the thickness of the transparent electrode layer is 1nm to 50nm. The transparent electrode layer is deposited on the surface of the silicon wafer subjected to thermal oxidation treatment by atomic layer deposition ALD, and the transparent electrode layer is deposited on one side of the glass wafer by atomic layer deposition ALD or sputtering.

[0064] In an embodiment of the present disclosure, the step S5 of processing the filling liquid inlet and outlet on the glass wafer is implemented by wet etching, laser drilling or sandblasting.

[0065] In the embodiment of the present disclosure, in the step of bonding the side of the glass wafer with the transparent electrode layer deposited thereon to the support structure outside the silicon dioxide micro-nanostructure array in step S6, anodic bonding or polyimide bonding is used for bonding. When anodic bonding is used, if the bonding fails, it is necessary to remove the bonding surface of the support structure and the glass wafer, remove the thermal oxidation layer and the transparent electrode layer near the bonding surface of the support structure, and remove the transparent electrode layer near the bonding surface of the glass wafer.

[0066] based on Figure 1 The flowchart of the method for preparing an optical modulator based on a high aspect ratio silicon dioxide micro-nano structure according to an embodiment of the present disclosure is shown, Figures 2 to 6 The process flow chart of preparing an optical modulator based on a high aspect ratio silicon dioxide micro-nano structure according to an embodiment of the present disclosure is shown, which specifically includes:

[0067] like Figure 2 As shown, Figure 2 The schematic diagram of making a high aspect ratio silicon micro-nano structure array on a silicon wafer according to an embodiment of the present disclosure shows a schematic diagram of the metal-assisted chemical etching result of the silicon wafer in the first step of the silicon dioxide micro-nano structure array processing method of the present disclosure. The silicon wafer 100 can be double-surface polished, with a thickness of 200μm to 500μm, and optionally a thickness of 300μm. A metal layer such as titanium / gold, silver, etc. is used as a mask on the upper surface of the silicon wafer 100, and a metal-assisted chemical etching process MACE is used to etch a silicon micro-nano structure array of equal size and consistent spacing on the silicon wafer. The silicon micro-nano structure is a hole structure, the width of the silicon groove 101 is 10nm to 10μm, and the spacing between adjacent silicon grooves is 10nm to 10μm. After the silicon micro-nano structure array is formed, the metal layer mask in the silicon micro-nano structure array is removed.

[0068] like Figure 3 As shown, Figure 3 In order to etch or corrode the back of the silicon wafer according to the embodiment of the present disclosure, completely release the silicon micro-nano structure array, and at the same time form a schematic diagram of a support structure on the periphery of the silicon micro-nano structure array, a schematic diagram of the silicon micro-nano structure array release process result in the second step of the silicon dioxide micro-nano structure array processing method of the embodiment of the present disclosure is shown. A cavity 201 is etched on the back of the silicon wafer using an etching process such as a deep reactive ion etching process until the silicon micro-nano structure on the upper surface is completely released, and at the same time a support structure is formed on the periphery of the silicon micro-nano structure array.

[0069] like Figure 4 As shown, Figure 4The schematic diagram of thermal oxidation treatment of a silicon wafer in which a silicon micro-nano structure array is completely released and a support structure is formed according to an embodiment of the present disclosure is shown, and a schematic diagram of the thermal oxidation result of the third step of the silicon dioxide micro-nano structure array processing method of the present disclosure embodiment is shown. The silicon wafer 100 with the silicon micro-nano structure on the upper surface completely released is placed in an oxidation furnace for thermal oxidation treatment. The thermal oxidation process parameters are a temperature of 850°C to 1100°C, and the time is adjusted according to demand until the silicon in the silicon micro-nano structure array is completely oxidized to silicon dioxide 301. The size of the silicon dioxide micro-nano structure array after thermal oxidation of silicon in the silicon micro-nano structure array can be adjusted by hydrofluoric acid wet etching. Specifically, the size of the silicon dioxide micro-nano structure array can be adjusted in one step by hydrofluoric acid wet etching of silicon dioxide. In addition, in the process of silicon in the silicon micro-nano structure array being oxidized to silicon dioxide, the size of the silicon micro-nano structure array can also be adjusted by thermal oxidation, wet etching, re-thermal oxidation, re-wet etching and other multiple cycles, and then thermal oxidation is formed to form a silicon dioxide micro-structure array of suitable size. Of course, if the size of the silicon dioxide micro-nano structure array after thermal oxidation is appropriate, the size of the silicon dioxide micro-nano structure array may not be adjusted.

[0070] like Figure 5 As shown, Figure 5 The schematic diagram of depositing a transparent electrode layer on the surface of a silicon dioxide micro-nano structure array and depositing a transparent electrode layer on one side of a glass wafer according to an embodiment of the present disclosure shows a schematic diagram of the transparent electrode deposition result on the glass surface of the optical modulator preparation process based on the silicon dioxide micro-nano structure array according to the embodiment of the present disclosure. A layer of transparent electrode 401 is deposited on the surface of a silicon wafer 100 having a silicon dioxide micro-nano structure array to completely cover its surface. Take another glass wafer 501, and process a filling liquid inlet and outlet 502 on the glass wafer 501 by wet etching, machining, sandblasting and other processes, and select one side of the glass wafer 501 to deposit a layer of transparent electrode 402. The thickness of the transparent electrodes 401 and 402 is preferably 1nm to 50nm, the deposition method is preferably atomic layer deposition ALD, and the transparent electrode material is preferably indium tin oxide ITO or aluminum-doped zinc oxide AZO. Optionally, atomic layer deposition ALD is used to deposit a transparent electrode layer on the surface of a silicon wafer subjected to thermal oxidation, and atomic layer deposition ALD or sputtering is used to deposit a transparent electrode layer on one side of a glass wafer.

[0071] like Figure 6 As shown, Figure 6The schematic diagram of bonding one side of a glass wafer with a transparent electrode layer deposited thereon to a supporting structure outside a silicon dioxide micro-nano structure array to form an optical modulator with a closed cavity according to an embodiment of the present disclosure is shown, and the schematic diagram of the silicon / glass bonding packaging result of the optical modulator preparation process based on the silicon dioxide micro-nano structure array according to an embodiment of the present disclosure is shown. The packaging method is preferably anodic bonding, and after packaging, a closed cavity is formed between the silicon dioxide micro-nano structure array and the glass wafer, which is used to store a filling liquid such as glycerin, thereby forming an optical modulator with a closed cavity.

[0072] So far, the embodiments of the present disclosure have been described in detail in conjunction with the accompanying drawings. It should be noted that the implementation methods not shown or described in the drawings or the body of the specification are all forms known to ordinary technicians in the relevant technical field and are not described in detail. In addition, the above definitions of each element and method are not limited to the various specific structures, shapes or methods mentioned in the embodiments, and ordinary technicians in the field can simply change or replace them.

[0073] Based on the above description, those skilled in the art should have a clear understanding of the method for preparing an optical modulator based on a silicon dioxide micro-nanostructure array provided by the present disclosure.

[0074] In summary, the method for preparing an optical modulator based on a high aspect ratio silicon dioxide micro-nano structure provided by the present disclosure can obtain a silicon dioxide micro-nano structure array with a high aspect ratio by using etching combined with a thermal oxidation process, thereby obtaining an optical modulator with a high aspect ratio. Therefore, the optical modulator prepared by this process has better performance.

[0075] Unless otherwise indicated, the numerical parameters in this specification and the appended claims are approximate values ​​and can vary according to the desired properties obtained through the content of the present disclosure. Specifically, all numbers used in the specification and claims to express the content of the composition, reaction conditions, etc., should be understood to be modified by the term "about" in all cases. In general, the meaning of the expression is to include a variation of ±10% in some embodiments, ±5% in some embodiments, ±1% in some embodiments, and ±0.5% in some embodiments by a specific number.

[0076] The ordinal numbers used in the specification and claims, such as "step S1", "step S2", "step S3", etc., to modify the corresponding elements, do not themselves mean that the elements have any ordinal numbers, nor do they represent the order of one element and another element, or the order of the manufacturing method. The use of these ordinal numbers is only used to make a component with a certain name clearly distinguishable from another component with the same name.

[0077] Similarly, it should be understood that in order to streamline the present disclosure and aid in understanding one or more of the various disclosed aspects, in the above description of the exemplary embodiments of the present disclosure, the various features of the present disclosure are sometimes grouped together into a single embodiment, figure, or description thereof. However, this disclosed method should not be interpreted as reflecting the following intention: the claimed disclosure requires more features than the features explicitly recited in each claim. More specifically, as reflected in the claims below, the disclosed aspects are less than all the features of the single embodiment disclosed above. Therefore, the claims that follow the specific embodiment are hereby expressly incorporated into the specific embodiment, with each claim itself serving as a separate embodiment of the present disclosure.

[0078] The specific embodiments described above further illustrate the purpose, technical solutions and beneficial effects of the present disclosure. It should be understood that the above description is only a specific embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure should be included in the protection scope of the present disclosure.

Claims

1. A method for preparing an optical modulator based on a high aspect ratio silicon dioxide micro-nano structure, characterized in that: include: Etching the front side of a silicon wafer to form a silicon micro-nano structure array; wherein the silicon wafer is a double-surface polished silicon wafer with a thickness of 200 μm to 500 μm, and in the silicon micro-nano structure array, the width of a silicon groove is 10 nm to 10 μm, and the spacing between adjacent silicon grooves is 10 nm to 10 μm; Etching or corroding the back side of the silicon wafer to completely release the silicon micro-nano structure array on the front side of the silicon wafer, and forming a supporting structure around the silicon micro-nano structure array; Thermally oxidizing the silicon wafer on which the silicon micro-nano structure array is completely released and the support structure is formed, oxidizing the silicon micro-nano structure array into a silicon dioxide micro-nano structure array, and oxidizing the silicon on the surface of the support structure into silicon dioxide; Depositing a transparent electrode layer on the surface of a silicon wafer subjected to thermal oxidation treatment; Taking another glass disc, processing a filling liquid inlet and outlet on the glass disc, and depositing a transparent electrode layer on one side of the glass disc; and Bonding one side of the glass wafer with the transparent electrode layer deposited thereon to the supporting structure around the silicon dioxide micro-nanostructure array to form a closed cavity; Among them, the silicon wafer with the silicon micro-nano structure array completely released and the supporting structure formed is subjected to thermal oxidation treatment to oxidize the silicon micro-nano structure array into a silicon dioxide micro-nano structure array, and at the same time oxidize the silicon on the surface of the supporting structure into silicon dioxide, including: placing the silicon wafer with the silicon micro-nano structure array completely released and the supporting structure formed into an oxidation furnace for one or more thermal oxidation treatments, the thermal oxidation temperature is 850°C~1100°C, until the silicon in the silicon micro-nano structure array is completely oxidized into silicon dioxide, that is, the silicon micro-nano structure array is oxidized into a silicon dioxide micro-nano structure array, and at the same time, the silicon on the surface of the supporting structure is oxidized into silicon dioxide.

2. The method for preparing an optical modulator based on a high aspect ratio silicon dioxide micro-nano structure according to claim 1, characterized in that: The etching of the front side of the silicon wafer to form a silicon micro-nano structure array comprises: A double-surface polished silicon wafer is selected, and a metal layer is used as a mask on the front side of the silicon wafer. A deep reactive ion etching process D-RIE or a metal assisted chemical etching process MACE is used to etch a silicon micro-nano structure array with equal size and consistent spacing on the silicon wafer.

3. The method for preparing an optical modulator based on a high aspect ratio silicon dioxide micro-nano structure according to claim 2, characterized in that: The metal layer used as a mask is made of titanium / gold or silver, and has a thickness of 5nm-100nm.

4. The method for preparing an optical modulator based on a high aspect ratio silicon dioxide micro-nano structure according to claim 1, characterized in that: After the silicon micro-nano structure array is formed, the method further comprises: The metal layer mask in the silicon micro-nano structure array is removed.

5. The method for preparing an optical modulator based on a high aspect ratio silicon dioxide micro-nano structure according to claim 1, characterized in that: The etching or corroding of the back side of the silicon wafer completely releases the silicon micro-nano structure array on the front side of the silicon wafer, and at the same time forms a support structure around the silicon micro-nano structure array, including: An etching or corrosion process is used to etch a cavity on the back of the silicon wafer until the silicon micro-nano structure array on the front of the silicon wafer is completely released, and a support structure is formed on the periphery of the silicon micro-nano structure array.

6. The method for preparing an optical modulator based on a high aspect ratio silicon dioxide micro-nano structure according to claim 5, characterized in that: The etching process adopts a deep reactive ion etching process D-RIE, and the corrosion process adopts a wet corrosion process of potassium hydroxide KOH or tetramethylammonium hydroxide TMAH solution; The support structure is a square ring structure, the silicon micro-nano structure arrays are all located in the square ring structure, and the thickness of the support structure is consistent with the thickness of the silicon wafer.

7. The method for preparing an optical modulator based on a high aspect ratio silicon dioxide micro-nano structure according to claim 1, characterized in that: After the silicon wafer on which the silicon micro-nano structure array is completely released and the supporting structure is formed is subjected to thermal oxidation treatment, the method further comprises: The size of the silicon dioxide micro-nanostructure array is adjusted by hydrofluoric acid wet etching.

8. The method for preparing an optical modulator based on a high aspect ratio silicon dioxide micro-nano structure according to claim 1, characterized in that: The transparent electrode layer deposited on the surface of the silicon wafer subjected to thermal oxidation treatment and the transparent electrode layer deposited on one side of the glass wafer are made of the same material.

9. The method for preparing an optical modulator based on a high aspect ratio silicon dioxide micro-nano structure according to claim 8, characterized in that: The material used for the transparent electrode layer is indium tin oxide ITO or aluminum-doped zinc oxide AZO, and the thickness of the transparent electrode layer is 1nm-50nm.

10. The method for preparing an optical modulator based on a high aspect ratio silicon dioxide micro-nano structure according to claim 1, characterized in that: Depositing a transparent electrode layer on the surface of the thermally oxidized silicon wafer adopts atomic layer deposition (ALD); The transparent electrode layer is deposited on one side of the glass wafer by atomic layer deposition (ALD) or sputtering.

11. The method for preparing an optical modulator based on a high aspect ratio silicon dioxide micro-nano structure according to claim 1, characterized in that: The filling liquid inlet and outlet are processed on the glass wafer by wet etching, laser drilling or sandblasting.

12. The method for preparing an optical modulator based on a high aspect ratio silicon dioxide micro-nano structure according to claim 1, characterized in that: In the step of bonding the side of the glass wafer on which the transparent electrode layer is deposited to the supporting structure around the silicon dioxide micro-nano structure array, bonding is performed by anodic bonding or polyimide bonding.

13. An optical modulator based on a high aspect ratio silica micro-nano structure, prepared by the method for preparing an optical modulator based on a high aspect ratio silica micro-nano structure according to any one of claims 1 to 12.

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