Ethernet card

Abstract

The present application relates to an Ethernet card, including: a board; a processor, a communication module, a PCle4.0 interface, a storage module and a clock module are configured on the board; the communication module, the PCle4.0 interface, the storage module and the clock module are all electrically connected to the processor; the board is also configured with a power input module, a first level conversion chip, a second level conversion chip, a third level conversion chip, a fourth level conversion chip and a fifth level conversion chip; the output end of the power output module is electrically connected to the first level conversion chip, the second level conversion chip, the third level conversion chip and the fourth level conversion chip; the output end of the first level conversion chip is electrically connected to the fifth level conversion chip, the storage module, the clock module and the communication module, and the PCle4.0 interface; the second level conversion chip, the third level conversion chip, the fourth level conversion chip and the fifth level conversion chip are all electrically connected to the processor. It can stably receive the power supply of the power supply, so that the network card can work stably.

Description

Technical Field

[0001] The present application relates to the field of communication information technology, and in particular to an Ethernet card. Background Art

[0002] A network card is a network interface controller, also known as a network adapter or a local area network receiver. It is the most basic, important and indispensable connection device in a computer network system. Existing Ethernet cards cannot stably receive power. Summary of the invention

[0003] In view of this, the present application proposes an Ethernet card, which can stably receive power from a power source so that the network card can work stably.

[0004] According to one aspect of the present application, there is provided an Ethernet card, comprising: a board card;

[0005] The board is equipped with a processor, a communication module, a PCle4.0 interface, a storage module and a clock module;

[0006] The processor is an E810 processor;

[0007] The communication module, the PCle4.0 interface, the storage module and the clock module are all electrically connected to the processor;

[0008] The communication module is electrically connected to the processor via a QSFP28 interface;

[0009] The board is also equipped with a power input module, a first level conversion chip, a second level conversion chip, a third level conversion chip, a fourth level conversion chip and a fifth level conversion chip;

[0010] The input end of the power input module is suitable for being electrically connected to a power supply, and the output end of the power output module is electrically connected to the input end of the first level conversion chip, the input end of the second level conversion chip, the input end of the third level conversion chip, and the input end of the fourth level conversion chip;

[0011] The output end of the first level conversion chip is electrically connected to the input end of the fifth level conversion chip, the storage module, the clock module, the communication module, and the PCle4.0 interface;

[0012] An output terminal of the second level conversion chip, an output terminal of the third level conversion chip, an output terminal of the fourth level conversion chip, and an output terminal of the fifth level conversion chip are all electrically connected to the processor.

[0013] In a possible implementation, the VIN pin of the first level conversion chip is electrically connected to the output end of the power input module, and is used to receive the 12V voltage output by the power input module;

[0014] The SW pin of the first level conversion chip is connected to a first inductor and outputs a 3.3V voltage as an output terminal of the first level conversion chip;

[0015] A first resistor and a first capacitor are connected in series between the BST pin of the first level conversion chip and the SW pin of the first level conversion chip;

[0016] The CR pin of the first level conversion chip is electrically connected to one end of the first inductor that is not connected to the SW pin of the first level conversion chip, and a second capacitor is connected in series.

[0017] In a possible implementation, the VIN pin of the first level conversion chip and the FREQ / MODE pin of the first conversion chip are combined and electrically connected to the output end of the power input module;

[0018] A plurality of capacitors and a second resistor connected in parallel are connected in series between the VIN pin of the first level conversion chip and the FREQ / MODE pin of the first level conversion chip;

[0019] A plurality of capacitors connected in parallel are externally connected to the output end of the first level conversion chip, and the other ends of the plurality of capacitors connected in parallel are suitable for grounding.

[0020] In a possible implementation, a third resistor and a third capacitor are connected in parallel between one end of the first inductor that is not connected to the SW pin of the first level conversion chip and the FB pin of the first level conversion chip;

[0021] One end of the third resistor and the third capacitor connected to the FB pin of the first level conversion chip is also electrically connected to a fourth resistor;

[0022] The other end of the fourth resistor is grounded;

[0023] A fifth resistor is connected in series between the VCC pin of the first level conversion chip and the PG pin of the first level conversion chip.

[0024] In a possible implementation, the VIN pin of the second level conversion chip is electrically connected to the output end of the power input module, and is used to receive the 12V voltage output by the power input module;

[0025] The SW pin of the second level conversion chip is connected to a second inductor and outputs a 1.1V voltage as an output terminal of the second level conversion chip;

[0026] A sixth resistor and a fourth capacitor are connected in series between the BST pin of the second level conversion chip and the SW pin of the second level conversion chip;

[0027] The CR pin of the second level conversion chip is electrically connected to one end of the second inductor that is not connected to the SW pin of the second level conversion chip, and a fifth capacitor is connected in series.

[0028] In a possible implementation, the VIN pin of the third level conversion chip is electrically connected to the output end of the power input module, and is used to receive the 12V voltage output by the power input module;

[0029] The SW pin of the third level conversion chip is connected to a third inductor and outputs a 0.9V voltage as the output terminal of the third level conversion chip;

[0030] A sixth capacitor is electrically connected between the BST pin of the third level conversion chip and the SW pin of the third level conversion chip.

[0031] In a possible implementation, the VIN pin of the fourth level conversion chip is electrically connected to the output end of the power input module, and is used to receive the 12V voltage output by the power input module;

[0032] The SW pin of the fourth power conversion chip is connected to a fourth inductor and outputs a 0.8V voltage as the output terminal of the fourth level conversion chip;

[0033] A seventh capacitor is electrically connected between the BST pin of the fourth level conversion chip and the SW pin of the fourth level conversion chip.

[0034] In a possible implementation, the VIN pin of the fifth level conversion chip is electrically connected to the output end of the first level conversion chip, and is used to receive the 3.3V voltage output by the output end of the first level conversion chip;

[0035] The VOUT pin of the fifth level conversion chip outputs a 1.8V voltage as the output end of the fifth level conversion chip;

[0036] Two or more capacitors and an eighth capacitor are sequentially connected in series between the VOUT pin of the fifth level conversion chip and the BYPASS pin of the fifth level conversion chip.

[0037] In a possible implementation, two communication modules are provided, and both of the two communication modules are electrically connected to the output end of the first level conversion chip and the processor.

[0038] In a possible implementation, the storage module is a 128Mb SPI FLASH and is electrically connected to the processor via a SPI interface.

[0039] The Ethernet card of the embodiment of the present application is provided with a board, and the board is provided with a processor, a communication module, a PCle4.0 interface, a storage module, a clock module, a power input module, a first level conversion chip, a second level conversion chip, a third level conversion chip, a fourth level conversion chip and a fifth level conversion chip, wherein the board has an E810 processor, and the power is input through the power input module, and a 12V voltage is generated. The first level conversion chip, the second level conversion chip, the third level conversion chip and the fourth level conversion chip receive the 12V voltage of the power input module, and the first level conversion chip converts the voltage and outputs it to the first level conversion chip and the communication module, the PCle4.0 interface, the storage module, and the clock module to power the above-mentioned electronic devices. The second level conversion chip, the third level conversion chip and the fourth level conversion chip convert the same voltage into different voltages and output them to the processor, thereby facilitating power supply to different states of the processor. In summary, the Ethernet card of the embodiment of the present application can stably receive the power supply of the power supply through the above-mentioned circuit structure, so that the network card can work stably.

[0040] Other features and aspects of the present application will become apparent from the following detailed description of exemplary embodiments with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate exemplary embodiments, features, and aspects of the present application and, together with the description, serve to explain the principles of the present application.

[0042] Figure 1 A block diagram of an Ethernet card according to an embodiment of the present application is shown;

[0043] Figure 2 A circuit diagram showing a first level conversion chip of an Ethernet card according to an embodiment of the present application;

[0044] Figure 3 A circuit diagram showing a second level conversion chip of an Ethernet card according to an embodiment of the present application;

[0045] Figure 4 A circuit diagram showing a third level conversion chip of the Ethernet card of an embodiment of the present application;

[0046] Figure 5 A circuit diagram showing a fourth level conversion chip of an Ethernet card according to an embodiment of the present application;

[0047] Figure 6A circuit diagram showing a fifth level conversion chip of the Ethernet card of an embodiment of the present application;

[0048] Figure 7 A circuit diagram showing a storage module of an Ethernet card according to an embodiment of the present application;

[0049] Figure 8 A circuit diagram showing a clock module of an Ethernet card according to an embodiment of the present application;

[0050] Fig. 9 A circuit diagram showing a communication module of an Ethernet card according to an embodiment of the present application;

[0051] Fig.10 A circuit diagram of a power input module of an Ethernet card according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0052] Various exemplary embodiments, features and aspects of the present application will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise specified.

[0053] Among them, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention or simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0054] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0055] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0056] In addition, in order to better illustrate the present application, numerous specific details are given in the following specific embodiments. It should be understood by those skilled in the art that the present application can also be implemented without certain specific details. In some examples, methods, means, components and circuits well known to those skilled in the art are not described in detail in order to highlight the subject matter of the present application.

[0057] Figure 1 A board block diagram of an Ethernet card according to an embodiment of the present application is shown. Figure 2 A circuit diagram of a first level conversion chip of an Ethernet card according to an embodiment of the present application is shown. Figure 3 A circuit diagram of a second level conversion chip of an Ethernet card according to an embodiment of the present application is shown. Figure 4 A circuit diagram of a third level conversion chip of the Ethernet card according to an embodiment of the present application is shown. Figure 5 A circuit diagram of a fourth level conversion chip of an Ethernet card according to an embodiment of the present application is shown. Figure 6 A circuit diagram of a fifth level conversion chip of the Ethernet card according to an embodiment of the present application is shown. Figure 7 A circuit diagram of a storage module of an Ethernet card according to an embodiment of the present application is shown. Figure 8 A circuit diagram of a clock module of an Ethernet card according to an embodiment of the present application is shown. Fig. 9 A circuit diagram of a communication module of an Ethernet card according to an embodiment of the present application is shown. Fig.10 FIG. 1 is a circuit diagram of a power input module of an Ethernet card according to an embodiment of the present application. Figures 1 to 10 As shown, the Ethernet card includes: a board, which is equipped with a processor, a communication module, a PCle4.0 interface, a storage module and a clock module. The processor is an E810 processor, and the electronic device includes a communication module, a PCle4.0 interface, a storage module and a clock module. The communication module, the PCle4.0 interface, the storage module and the clock module are all electrically connected to the processor, and the communication module is electrically connected to the processor through a QSFP28 interface. The board is also equipped with a power input module, a first level conversion chip, a second level conversion chip, a third level conversion chip, a fourth level conversion chip and a fifth level conversion chip. The input end of the power input module is suitable for being electrically connected to the power supply, and the power output module is electrically connected to the input end of the first level conversion chip, the input end of the second level conversion chip, the input end of the third level conversion chip and the input end of the fourth level conversion chip. The output end of the first level conversion chip is electrically connected to the input end of the fifth level conversion chip, the storage module, the clock module, the communication module, and the PCle4.0 interface. An output terminal of the second level conversion chip, an output terminal of the third level conversion chip, an output terminal of the fourth level conversion chip, and an output terminal of the fifth level conversion chip are all electrically connected to the processor.

[0058] The Ethernet card of the embodiment of the present application is provided with a board, and the board is provided with a processor, a communication module, a PCle4.0 interface, a storage module, a clock module, a power input module, a first level conversion chip, a second level conversion chip, a third level conversion chip, a fourth level conversion chip and a fifth level conversion chip, wherein the board has an E810 processor, and the power is input through the power input module, and a 12V voltage is generated. The first level conversion chip, the second level conversion chip, the third level conversion chip and the fourth level conversion chip receive the 12V voltage of the power input module, and the first level conversion chip converts the voltage and outputs it to the first level conversion chip and the communication module, the PCle4.0 interface, the storage module, and the clock module to power the above-mentioned electronic devices. The second level conversion chip, the third level conversion chip and the fourth level conversion chip convert the same voltage into different voltages and output them to the processor, thereby facilitating power supply to different states of the processor. In summary, the Ethernet card of the embodiment of the present application can stably receive the power supply of the power supply through the above-mentioned circuit structure, so that the network card can work stably.

[0059] Here, it should be pointed out that in one possible implementation, a heat sink is attached to the board, thereby avoiding excessive temperature during operation, enhancing the heat dissipation of the embodiment of the present application, and the board can adopt a 6-8 layer PCB board.

[0060] Here, it should also be pointed out that, in a possible implementation, a tin layer is sprayed on the surface of the board, thereby preventing the bare copper of the board from being oxidized and maintaining solderability.

[0061] Here, it should also be noted that, in a possible implementation, the size of the board is 167.5 mm x 63.9 mm.

[0062] It should also be pointed out here that in a possible implementation, the communication module and PCle4.0 interface both use 5μ immersion gold, which has more reliable contact and less loss, and can effectively reduce packet loss and data delay.

[0063] In a possible implementation, the VIN pin of the first level conversion chip is electrically connected to the output end of the power input module, and is used to receive the 12V voltage output by the power input module. The SW pin of the first level conversion chip is externally connected to the first inductor L2 and outputs a 3.3V voltage as the output end of the first level conversion chip. A first resistor R360 and a first capacitor C419 are connected in series between the BST pin of the first level conversion chip and the SW pin of the first level conversion chip. The CR pin of the first level conversion chip is electrically connected to one end of the first inductor that is not connected to the SW pin of the first level conversion chip, and is connected in series with a second capacitor C420.

[0064] Here, it should be pointed out that, in a possible implementation, the model of the first inductor L2 is: 4.7UH-FMDS6024-4R7M.

[0065] Furthermore, in a possible implementation, the VIN pin of the first level conversion chip and the FREQ / MODE pin of the first conversion chip are combined and electrically connected to the output end of the power input module. A plurality of parallel capacitors and a second resistor R90 are connected in series between the VIN pin of the first level conversion chip and the FREQ / MODE pin of the first conversion chip. A plurality of parallel capacitors are externally connected to the output end of the first level conversion chip, and the other ends of the plurality of parallel capacitors are suitable for grounding.

[0066] In a possible implementation, a third resistor R104 and a third capacitor C130 are connected in parallel between the end of the first inductor L2 that is not connected to the SW pin of the first level conversion chip and the FB pin of the first level conversion chip. The third resistor R104 and the third capacitor C130 are also electrically connected to the end of the FB pin of the first level conversion chip, and the other end of the fourth resistor R88 is grounded. A fifth resistor R359 is connected in series between the VCC pin of the first level conversion chip and the PG pin of the first level conversion chip.

[0067] Here, it should be pointed out that in a possible implementation, a capacitor C418 is externally connected to the SS pin of the first level conversion chip, the GND pin of the first level conversion chip is grounded, and the other end of the capacitor C418 is electrically connected to the GND pin of the first level conversion chip.

[0068] Here, it should also be pointed out that, in a possible implementation, a capacitor C204 is externally connected to the VCC pin of the first level conversion chip, and the other end of the capacitor C204 is grounded.

[0069] In a possible implementation, the VIN pin of the second level conversion chip is electrically connected to the output end of the power input module, and is used to receive the 12V voltage output by the power input module. The SW pin of the second level conversion chip is externally connected to the second inductor L13 and then outputs a 1.1V voltage as the output end of the second level conversion chip. A sixth resistor R365 and a fourth capacitor C433 are connected in series between the BST pin of the second level conversion chip and the SW pin of the second level conversion chip. The CR pin of the second level conversion chip is electrically connected to one end of the second inductor that is not connected to the SW pin of the second level conversion chip, and is connected in series with a fifth capacitor C434.

[0070] Here, it should be pointed out that, in a possible implementation, the model of the second inductor L13 is: 2.2UH-FMDS6024-2R2M.

[0071] Here, it should also be pointed out that, in a possible implementation, the VIN pin of the second level conversion chip and the FREQ / MODE pin of the second level conversion chip are combined and electrically connected to the output end of the power input module. And a plurality of parallel capacitors and a resistor R363 are connected in series between the VIN pin of the second level conversion chip and the FREQ / MODE pin of the second level conversion chip. A plurality of parallel capacitors are externally connected at the output end of the second level conversion chip, and the other ends of the plurality of parallel capacitors are suitable for grounding.

[0072] Here, it should also be pointed out that, in a possible implementation, a resistor R364 and a capacitor C426 are connected in parallel between one end of the second inductor L13 connected by the SW pin of the second level conversion chip and the FB pin of the second level conversion chip. A resistor R361 is also electrically connected to one end of the resistor R364 and the capacitor C426 connected to the FB pin of the second level conversion chip, and the other end of the resistor R361 is grounded. A resistor R362 is connected in series between the VCC pin of the second level conversion chip and the PG pin of the second level conversion chip.

[0073] Here, it should also be pointed out that, in a possible implementation, a capacitor C424 is externally connected to the VCC pin of the second level conversion chip, and the other end of the capacitor C424 is grounded.

[0074] It should also be pointed out here that in a possible implementation, a capacitor C423 is externally connected to the SS pin of the second level conversion chip, the GND pin of the second level conversion chip is grounded, and the other end of the capacitor C423 is electrically connected to the GND pin of the second level conversion chip.

[0075] In a possible implementation, the VIN pin of the third level conversion chip is electrically connected to the output end of the power input module, and is used to receive the 12V voltage output by the power input module. The SW pin of the third level conversion chip is externally connected to the third inductor L3 and outputs a 0.9V voltage as the output end of the third level conversion chip. A sixth capacitor C440 is electrically connected between the BST pin of the third level conversion chip and the SW pin of the third level conversion chip.

[0076] It should be noted here that, in a possible implementation, the model of the third inductor L13 is: 0.57 μH-IHLP4040DZERR56MD.

[0077] Here, it should be noted that, in a possible implementation, a plurality of capacitors arranged in parallel are externally connected to the VIN pin of the third level conversion chip, and the other ends of the plurality of capacitors arranged in parallel are grounded. A plurality of capacitors arranged in parallel are externally connected to the output end of the third level conversion chip, and one end of the capacitors arranged in parallel here is electrically connected to the third inductor L13, and the other end is grounded.

[0078] It should also be pointed out here that, in a possible implementation, a resistor R378 and a capacitor C443 are also electrically connected between the SW pin of the third level conversion chip and the FB pin of the third level conversion chip, and one end of the resistor R378 and the capacitor C443 are electrically connected to the third inductor L3, and the other end is electrically connected to the resistor R377, and the other end of the resistor R377 is grounded.

[0079] Here, it should also be pointed out that, in a possible implementation, the PGOOD pin of the third level conversion chip is externally connected to a resistor R379 and a capacitor C439 arranged in series, and the VCC pin of the third level conversion chip is electrically connected between the resistor R379 and the capacitor C439. The MODE pin of the third level conversion chip is externally connected to a resistor R376, and the CS pin of the third level conversion chip is externally connected to a resistor R380. The TPK / REF pin of the third level conversion chip is externally connected to a capacitor C441 and a capacitor C442 arranged in parallel. And the capacitor C439, the resistor R376, the resistor R380, the other end of the capacitor C441 and the capacitor C442 arranged in parallel, the RGND pin of the third level conversion chip, and the AGND pin of the third level conversion chip are combined and grounded.

[0080] In a possible implementation, the VIN pin of the fourth level conversion chip is electrically connected to the output end of the power input module, and is used to receive the 12V voltage output by the power input module. The SW pin of the fourth power conversion chip is connected to the fourth inductor L14 and then outputs a 0.8V voltage as the output end of the fourth level conversion chip. A seventh capacitor C456 is electrically connected between the BST pin of the fourth level conversion chip and the SW pin of the fourth level conversion chip.

[0081] It should be noted here that, in a possible implementation, the model of the fourth inductor L14 is: 0.57 μH-IHLP4040DZERR56MD1.

[0082] Here, it should also be noted that, in a possible implementation, a plurality of capacitors arranged in parallel are externally connected to the VIN pin of the fourth level conversion chip, and the other ends of the plurality of capacitors arranged in parallel are grounded. A plurality of capacitors arranged in parallel are externally connected to the output end of the fourth level conversion chip, and one end of the capacitors arranged in parallel here is electrically connected to the fourth inductor L14, and the other end is grounded.

[0083] It should also be pointed out here that, in a possible implementation, a resistor R385 and a capacitor C458 are also electrically connected between the SW pin of the fourth level conversion chip and the FB pin of the fourth level conversion chip, and one end of the resistor R385 and the capacitor C458 are electrically connected to the fourth inductor L14, and the other end is electrically connected to the resistor R384, and the other end of the resistor R384 is grounded.

[0084] Here, it should also be pointed out that, in a possible implementation, the PGOOD pin of the fourth level conversion chip is externally connected to a resistor R381 and a capacitor C449 arranged in series, and the VCC pin of the fourth level conversion chip is electrically connected between the resistor R381 and the capacitor C449. The MODE pin of the fourth level conversion chip is externally connected to a resistor R383, and the CS pin of the fourth level conversion chip is externally connected to a resistor R382. The TPK / REF pin of the fourth level conversion chip is externally connected to a capacitor C455 and a capacitor C457 arranged in parallel. And the capacitor C449, the resistor R381, the other end of the resistor R381, the capacitor C455 and the capacitor C457 arranged in parallel, the RGND pin of the fourth level conversion chip, and the AGND pin of the fourth level conversion chip are combined and grounded.

[0085] In a possible implementation, the VIN pin of the fifth level conversion chip is electrically connected to the output end of the first level conversion chip, and is used to receive the 3.3V voltage outputted by the output end of the first level conversion chip. The VOUT pin of the fifth level conversion chip outputs a 1.8V voltage as the output end of the fifth level conversion chip. Two or more capacitors and an eighth capacitor C462 are sequentially connected in series between the VOUT pin of the fifth level conversion chip and the BYPASS pin of the fifth level conversion chip.

[0086] Here, it should be pointed out that, in a possible implementation, a capacitor C120 and a capacitor C466 are sequentially connected in series and in parallel between the VOUT pin of the fifth level conversion chip and the BYPASS pin of the fifth level conversion chip.

[0087] Here, it should also be noted that in a possible implementation, the VIN pin of the fifth level conversion chip is externally connected to a capacitor CT15 and a capacitor C162 arranged in parallel. The GND pin of the fifth level conversion chip and the other ends of the capacitor CT15 and the capacitor C162 arranged in parallel are combined and grounded.

[0088] In a possible implementation, two communication modules are provided, and both communication modules are electrically connected to the output end of the first level conversion chip and the processor. Moreover, both communication modules are 100G network interfaces for network communication.

[0089] In a possible implementation, the storage module is a 128Mb SPI FLASH and is electrically connected to the processor via a SPI interface.

[0090] Here, it should be noted that, in a possible implementation, the storage module includes a storage chip, and the CS# pin, WP# pin and HOLD# pin of the storage chip are all electrically connected to the output end of the first level conversion chip for accessing a 3.3V voltage. A resistor R78 is externally connected to the SCK pin of the storage chip. A resistor R184 is electrically connected between the WP# pin of the storage chip and the output end of the first level conversion chip, and a resistor R72 is electrically connected between the CS# pin of the storage chip and the output end of the first level conversion chip. A capacitor C160 is externally connected to the VCC pin of the storage chip. A resistor R183 is electrically connected between the HOLD# pin of the storage chip and the output end of the first level conversion chip, and one end of the resistor R183 that is not electrically connected to the HOLD# pin of the storage chip is electrically connected between the VCC pin of the storage chip and the capacitor C160. A resistor R182 is externally connected to the SCK pin of the storage chip.

[0091] Here, it should also be noted that, in a possible implementation, the clock module includes a clock generator, which generates a 156.25M differential clock. The VCC pin of the clock generator is electrically connected to the output end of the first level conversion chip for receiving a 3.3V voltage, and the VCC pin of the clock generator is also externally connected to a capacitor C282. The OE pin of the clock generator is externally connected to a resistor R255, the OUTPUT pin of the clock generator is externally connected to a resistor R269, and the OUTPUT-N pin of the clock generator is externally connected to a resistor R263.

[0092] The embodiments of the present application have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or improvements to the technology in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. An Ethernet card, characterized in that: include: Boards; The board is equipped with a processor, a communication module, a PCle4.0 interface, a storage module and a clock module; The processor is an E810 processor; The communication module, the PCle4.0 interface, the storage module and the clock module are all electrically connected to the processor; The communication module is electrically connected to the processor via a QSFP28 interface; The board is also equipped with a power input module, a first level conversion chip, a second level conversion chip, a third level conversion chip, a fourth level conversion chip and a fifth level conversion chip; The input end of the power input module is suitable for being electrically connected to a power supply, and the output end of the power output module is electrically connected to the input end of the first level conversion chip, the input end of the second level conversion chip, the input end of the third level conversion chip, and the input end of the fourth level conversion chip; The output end of the first level conversion chip is electrically connected to the input end of the fifth level conversion chip, the storage module, the clock module, the communication module, and the PCle4.0 interface; The output end of the second level conversion chip, the output end of the third level conversion chip, the output end of the fourth level conversion chip and the output end of the fifth level conversion chip are all electrically connected to the processor; Wherein, the VIN pin of the first level conversion chip is electrically connected to the output end of the power input module, and is used to receive the 12V voltage output by the power input module; The SW pin of the first level conversion chip is connected to a first inductor and outputs a 3.3V voltage as an output terminal of the first level conversion chip; A first resistor and a first capacitor are connected in series between the BST pin of the first level conversion chip and the SW pin of the first level conversion chip; The CR pin of the first level conversion chip is electrically connected to the end of the first inductor that is not connected to the SW pin of the first level conversion chip, and is connected in series with a second capacitor; The VIN pin of the first level conversion chip and the FREQ / MODE pin of the first level conversion chip are combined and electrically connected to the output end of the power input module; A plurality of capacitors and a second resistor connected in parallel are connected in series between the VIN pin of the first level conversion chip and the FREQ / MODE pin of the first level conversion chip; A plurality of capacitors connected in parallel are externally connected to the output end of the first level conversion chip, and the other ends of the plurality of capacitors connected in parallel are suitable for grounding; A third resistor and a third capacitor are connected in parallel between one end of the first inductor that is not connected to the SW pin of the first level conversion chip and the FB pin of the first level conversion chip; One end of the third resistor and the third capacitor connected to the FB pin of the first level conversion chip is also electrically connected to a fourth resistor; The other end of the fourth resistor is grounded; A fifth resistor is connected in series between the VCC pin of the first level conversion chip and the PG pin of the first level conversion chip; The VIN pin of the second level conversion chip is electrically connected to the output end of the power input module, and is used to receive the 12V voltage output by the power input module; The SW pin of the second level conversion chip is connected to a second inductor and outputs a 1.1V voltage as the output terminal of the second level conversion chip; A sixth resistor and a fourth capacitor are connected in series between the BST pin of the second level conversion chip and the SW pin of the second level conversion chip; The CR pin of the second level conversion chip is electrically connected to one end of the second inductor that is not connected to the SW pin of the second level conversion chip, and a fifth capacitor is connected in series.

2. The Ethernet card according to claim 1, wherein: The VIN pin of the third level conversion chip is electrically connected to the output end of the power input module, and is used to receive the 12V voltage output by the power input module; The SW pin of the third level conversion chip is connected to a third inductor and outputs a 0.9V voltage as the output terminal of the third level conversion chip; A sixth capacitor is electrically connected between the BST pin of the third level conversion chip and the SW pin of the third level conversion chip.

3. The Ethernet card according to claim 1, wherein: The VIN pin of the fourth level conversion chip is electrically connected to the output end of the power input module, and is used to receive the 12V voltage output by the power input module; The SW pin of the fourth level conversion chip is connected to a fourth inductor and outputs a 0.8V voltage as the output terminal of the fourth level conversion chip; A seventh capacitor is electrically connected between the BST pin of the fourth level conversion chip and the SW pin of the fourth level conversion chip.

4. The Ethernet card according to claim 1, wherein: The VIN pin of the fifth level conversion chip is electrically connected to the output end of the first level conversion chip, and is used to receive the 3.3V voltage output by the output end of the first level conversion chip; The VOUT pin of the fifth level conversion chip outputs a 1.8V voltage as the output end of the fifth level conversion chip; Two or more capacitors and an eighth capacitor are sequentially connected in series between the VOUT pin of the fifth level conversion chip and the BYPASS pin of the fifth level conversion chip.

5. The Ethernet card according to claim 1, wherein: Two communication modules are provided, and both of the two communication modules are electrically connected to the output end of the first level conversion chip and the processor.

6. The Ethernet card according to claim 1, characterized in that: The storage module is a 128Mb SPIFLASH and is electrically connected to the processor via a SPI interface.

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