A three-dimensional memory, preparation method and data operation method

Abstract

The invention discloses a three-dimensional memory, a preparation method and a data operation method. The three-dimensional memory is composed of a multi-layer structure periodically arranged in a vertical direction. The multi-layer structure comprises a first wire layer, a first capacitor layer, a first gate tube layer, a second wire layer, a second capacitor layer and a second gate tube layer. The first wire layer is composed of a plurality of mutually parallel wires. The first gate tube layer is composed of an array composed of a plurality of gate tubes evenly distributed. The first capacitor layer is composed of an array composed of a plurality of capacitors evenly distributed. The lower electrode of each capacitor in the first capacitor layer is connected to the upper electrode of a gate tube in the first gate tube layer. The invention can stack 1S1C storage units in the vertical direction, and can greatly improve the storage density of the 1S1C memory.

Description

Technical Field

[0001] The present invention belongs to the field of memory technology, and more specifically, relates to a three-dimensional memory, a preparation method and a data operation method. Background Art

[0002] In the computer structure of the von Neumann system, DRAM (dynamic random access memory) plays a connecting role between external memory and CPU, and plays a very important role in the stability of the computer system. DRAM adopts a 1T1C structure, that is, it is composed of a transistor and a storage unit in series. Since the transistor is a three-port device, its peripheral control circuit needs to consume a large area, and the three-port device is not suitable for three-dimensional stacking, making it difficult for DRAM to achieve high-density storage through three-dimensional integration. This is also the most critical factor restricting DRAM performance.

[0003] In order to solve the problem of low DRAM storage density, the academic and industrial circles in the field of memory have explored many new types of memory that may replace DRAM. Among them, the 1S1C storage unit composed of an OTS gate tube and a capacitor connected in series mentioned in Chinese invention patent CN202111280349.1 is comparable to DRAM in terms of read, write, and erase speeds and power consumption. It is a new storage technology that is very likely to replace DRAM. However, there is no research on its three-dimensional integrated structure and whether it can realize the read, write, and erase functions of data after three-dimensional integration.

[0004] The traditional crossbar structure is usually used in resistive random access memory. The storage unit does not have high requirements on the polarity of the operating pulse. The pulse can be applied from the top electrode of the storage device or from the bottom electrode of the storage device. For the 1S1C storage unit, data is stored by relying on the polarity of the charge stored on the capacitor, and the data written each time is related to the threshold voltage and holding voltage of the selection device. The threshold voltage and holding voltage of the selection tube have deviations in the positive and negative directions. Therefore, the 1S1C memory is very sensitive to the polarity of the applied pulse. When performing read and write operations, the pulse application method must be precisely controlled. Summary of the invention

[0005] In view of the defects of the prior art, the purpose of the present invention is to propose a three-dimensional memory, aiming to solve the problem of low storage density of the 1S1C memory planar structure.

[0006] The three-dimensional memory provided by the present invention is composed of a multi-layer structure periodically arranged in a vertical direction, wherein the multi-layer structure comprises a first wire layer, a first capacitor layer, a first gate tube layer, a second wire layer, a second capacitor layer and a second gate tube layer; the first wire layer is composed of a plurality of parallel wires; the first gate tube layer comprises a plurality of gate tubes, and the lower electrode of each gate tube in the first gate tube layer is connected to a wire in the first wire layer; the first capacitor layer comprises a plurality of capacitors, and the lower electrode of each capacitor in the first capacitor layer is connected to the upper electrode of a gate tube in the first gate tube layer; The second conductor layer includes a plurality of parallel conductors, and the upper electrode of each capacitor in the first capacitor layer is connected to a conductor in the second conductor layer; the second selection tube layer includes a plurality of selection tubes, and the lower electrode of each selection tube in the second selection tube layer is connected to a conductor in the second conductor layer; the second capacitor layer includes a plurality of capacitors, and the lower electrode of each capacitor in the second capacitor layer is connected to the upper electrode of a selection tube in the second selection tube layer, and the upper electrode of each capacitor in the second capacitor layer is connected to a conductor in the first conductor layer of the next periodically arranged multilayer structure.

[0007] The first gate tube layer and the second gate tube layer are both composed of an array of a plurality of gate tubes evenly distributed; the first capacitor layer and the second capacitor layer are both composed of an array of a plurality of capacitors evenly distributed.

[0008] Furthermore, the second conductor layer is composed of a plurality of conductors which are parallel to each other and form a certain angle with the conductors of the first conductor layer in the horizontal direction.

[0009] The angle is preferably greater than 0 and less than or equal to 90 degrees.

[0010] Furthermore, the capacitor in the first capacitor layer is the same as the capacitor in the second capacitor layer, and the gate tube in the first gate tube layer is the same as the gate tube in the second gate tube layer.

[0011] The gate tubes in the first gate tube layer and the second gate tube layer both have bidirectional conduction characteristics and have a forward threshold voltage Vth+ and a forward holding voltage Vhold+ in the forward direction, and a reverse threshold voltage Vth- and a reverse holding voltage Vhold- in the reverse direction.

[0012] The present invention also provides a data operation method based on the above three-dimensional memory, wherein the data operation method includes a data reading operation method and a data writing operation method:

[0013] (1) Determine the layer of the three-dimensional memory in which the storage unit to be operated is located; specifically, according to the address instruction transmitted by the memory control module, the address instruction can be decoded to obtain the physical address position of the storage unit, and the physical address position will include the layer of the three-dimensional memory in which the storage unit is located.

[0014] (2) When a data read operation is required, if it is the nth layer, a positive read voltage Vread+ is applied to the word line electrode connected to the top electrode of the memory cell, and a reverse read voltage Vread- is applied to the bit line electrode connected to the bottom electrode of the memory cell; if it is the n+1th layer, a positive read voltage Vread+ is applied to the bit line electrode connected to the top electrode of the memory cell, and a reverse read voltage Vread- is applied to the word line electrode connected to the bottom electrode of the memory cell;

[0015] When a data write operation is required, if it is the nth layer, a forward write voltage Vwrite+ is applied to the word line electrode connected to the top electrode of the memory cell, and a reverse write voltage Vwrite- is applied to the bit line electrode connected to the bottom electrode of the memory cell; if it is the n+1th layer, a forward write voltage Vwrite+ is applied to the bit line electrode connected to the top electrode of the memory cell, and a reverse write voltage Vwrite- is applied to the word line electrode connected to the bottom electrode of the memory cell;

[0016] The nth layer unit and the n+1th layer unit share a word line, the n+1th layer unit and the n+2th layer unit share a bit line, and n is a positive integer greater than or equal to 1, and generally less than or equal to 1000.

[0017] Furthermore, by applying a forward write voltage Vwrite+ and a reverse write voltage Vwrite- at both ends of the storage cell respectively, a voltage difference Vwrite is formed at both ends of the storage cell. When the voltage difference at both ends of the gate tube in the selected storage cell is greater than the threshold voltage Vth of the gate tube, the gate tube is turned on to charge the capacitor so that the capacitor voltage Vc in the storage cell reaches a specific value. By designing two different Vwrites, two different capacitor voltages Vc are obtained, one of which is marked as state 0 and the other is marked as state 1, thereby realizing the function of data storage.

[0018] Among them, the data reading operation method includes applying a specific voltage (here Vread+ and Vread-) to the wires in the first wire layer connected to the selected storage cell and the wires in the second wire layer connected to the selected storage cell, so as to form a voltage difference Vread at both ends of the selected storage cell, so as to open the gate tube in the storage cell in state 0 and not open the gate tube in the storage cell in state 1, and judge the data state of the storage cell by sensing the change of the current in the wire; when reading and writing data, the voltage applied to the wire will not open the gate tube in the unselected storage cell.

[0019] Further preferably, the data reading operation and the data writing operation can be implemented not only as bit-by-bit operations but also as whole-row operations, wherein the whole-row operations include: applying a word line voltage V1 to a conductor common to the memory cells in the row (the application of the word line voltage V1 will not turn on the gate tube in the memory cell), and then applying a bit line voltage V2 to another conductor connected to the corresponding memory cell according to the operation to be performed on each memory cell, wherein the bit line voltage V2 and the word line voltage V1 work together to turn on the gate tube in the memory cell, thereby completing the reading and writing operations.

[0020] The present invention also provides a method for preparing the three-dimensional memory, comprising the following steps:

[0021] (1) forming a first electrode layer consisting of a plurality of parallel strip electrodes on a substrate of a memory cell;

[0022] (2) forming a first insulating layer on the first electrode layer;

[0023] (3) selectively etching and removing the first insulating layer, leaving a plurality of hole arrays penetrating the first insulating layer, wherein the holes are all located directly above the strip electrodes of the first electrode layer; specifically, the hole array may be in the shape of a square, a rectangle or a parallelogram;

[0024] (4) forming a first gate tube layer, a second electrode layer and a first dielectric layer in sequence in the hole;

[0025] (5) forming a third electrode layer composed of a plurality of unconnected and parallel strip electrodes, which is perpendicular to the strip electrodes of the first electrode layer in a horizontal direction, and the hole is located at the intersection of the first electrode layer and the third electrode layer;

[0026] (6) repeating steps (2) to (5) in sequence, and the position of the holes formed in each layer is offset by 2d in the horizontal direction from the holes formed in the previous layer, until the target number of three-dimensional memory layers is obtained; wherein d is the characteristic size of the hole;

[0027] (7) Etching out the interface of each electrode layer to obtain the three-dimensional memory.

[0028] Through the above technical solutions conceived by the present invention, compared with the prior art, the present invention can achieve the following beneficial effects:

[0029] (1) The proposed memory structure is relatively simple. When a multi-layer 1S1C memory needs to be prepared, it is only necessary to simply repeat the previous steps to stack the 1S1C memory cells in the vertical direction, which can greatly improve the storage density of the 1S1C memory; as well as the structural integrity of the memory cells in the crossbar structure, and make all memory cells have better state uniformity.

[0030] (2) The proposed memory structure can realize independent addressing of each storage unit, implement bit-by-bit operations, and also implement whole-row operations, enriching the application scenarios of the memory.

[0031] (3) An operation method for the crossbar structure of 1S1C memory is proposed, because the polarity difference of the gate tube in the 1S1C memory will cause the 1S1C memory to have different responses when the same voltage is applied in the forward and reverse directions. In the traditional crossbar structure, after the memory cell is selected, only V / 2 is applied to the word line and -V / 2 is applied to the bit line, and it does not matter whether the top electrode or the bottom electrode of the memory cell is connected to the word line. In the present invention, the voltage applied to the word line and the bit line is adjusted by judging the number of layers where the memory cell is located, thereby overcoming the polarity difference of the gate device and making the data consistency of the memory cell better.

[0032] (4) The proposed 1S1C memory preparation method staggers the positions of holes in the same area in the vertical direction, avoiding the influence of the surface unevenness caused by the preparation and filling of the holes in the lower layer on the shape of the holes in the upper layer, thereby ensuring the stability of the 1S1C memory performance as the number of stacked layers increases. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 is a schematic diagram of the structure of a three-dimensional memory provided by an embodiment of the present invention;

[0034] Figure 2 Schematic diagram of applying a write-0 pulse to a three-dimensional memory provided by an embodiment of the present invention;

[0035] Figure 3 Schematic diagram of applying a write 1 pulse to a three-dimensional memory provided by an embodiment of the present invention;

[0036] Figure 4 is a schematic diagram of applying a read pulse to a three-dimensional memory provided by an embodiment of the present invention;

[0037] Figure 5 is a flowchart of a method for manufacturing a three-dimensional memory provided by an embodiment of the present invention;

[0038] Figure 6 It is a top view of a partial area of ​​a 1S1C memory in a three-dimensional memory provided by an embodiment of the present invention.

[0039] In all the drawings, the same reference numerals are used to represent the same elements or structures, wherein: 1 is a bit line, 2 is a word line, 3 is a gate tube, 4 is a capacitor, 21 is a word line voltage, 22 is a capacitor voltage, 23 is a bit line voltage, and 42 is a current flowing through the memory cell. DETAILED DESCRIPTION

[0040] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0041] Figure 1 The structure of a three-dimensional memory provided by an embodiment of the present invention is shown. For the convenience of description, only the part related to the embodiment of the present invention is shown. The following is a detailed description in conjunction with the accompanying drawings:

[0042] The memory uses a gate tube 3 and a capacitor 4 connected in series to form the most basic storage unit. One end of each storage unit is connected to the word line 2, and the other end is connected to the bit line 1. The storage unit is arranged at the intersection of the word line 2 and the bit line 1 to form a crossbar structure. Two adjacent storage units in the vertical direction share the same word line or bit line. If the three-dimensional memory is structurally divided into a word line layer, a bit line layer, and a storage unit layer, then the three-dimensional memory will be a storage unit layer above the word line layer in the vertical direction, a bit line layer above the storage unit layer, a next storage unit layer above the bit line layer, and a next word line layer above the storage unit layer. This is regarded as a structural period and is stacked periodically in the vertical direction to achieve three-dimensional data storage.

[0043] In this three-dimensional memory, all storage cells are made of the same material, the same structure, and are manufactured under the same process conditions, so that the storage cells have good consistency.

[0044] In this three-dimensional memory, the gate tube has a bidirectional conduction characteristic, and there are a threshold voltage Vth and a holding voltage Vhold in both the forward and reverse directions. When the voltage across the gate tube exceeds the threshold voltage Vth, the gate tube switches from a high-resistance state to a low-resistance state. When the voltage across the gate tube in the low-resistance state is lower than the holding voltage Vhold, the gate tube switches from a low-resistance state to a high-resistance state.

[0045] The storage unit composed of this type of gate tube and capacitor in series has the following characteristics: when a voltage Vin is applied across the storage unit so that the voltage across the gate tube is greater than the threshold voltage Vth, the gate tube is turned on and the capacitor is charged. The voltage Vc on the capacitor is related to the voltage Vin applied across the storage unit. Therefore, by designing two different Vins, two different capacitor voltages Vc are obtained, and one Vc is marked as storage state 0 and the other Vc is marked as storage state 1, the function of data storage can be realized.

[0046] When operating a memory cell in a three-dimensional memory, voltages need to be applied to the word line and bit line connected to the memory cell respectively. The voltage difference between the word line voltage and the bit line voltage will be loaded on the memory cell, thereby enabling the memory cell to be operated.

[0047] When data is written to a storage cell in the three-dimensional memory, the voltage difference between the word line voltage and the bit line voltage can turn on the gate tube of the selected storage cell, and the capacitor is charged to the corresponding capacitor voltage Vc. For the unselected storage cell, the gate tube is in a closed state, and its capacitor voltage Vc will not be affected.

[0048] When a data reading operation is performed on a storage cell in a three-dimensional memory, the voltage difference between the word line voltage and the bit line voltage is loaded to both ends of the storage cell, which can turn on the gate tube in the storage cell in state 0 and turn off the gate tube in the storage cell in state 1. The data state of the storage cell is determined by sensing the change in the current in the wire.

[0049] This three-dimensional memory can not only realize bit-by-bit operations, but also whole-row operations. When a whole-row operation is required, it is necessary to first apply a specific voltage to the word line shared by the memory cells in the row, and then apply a specific voltage to another wire connected to the corresponding memory cell according to the operation to be performed on each memory cell.

[0050] In the 1S1C memory of the present invention, there is a difference in the conduction of the gate tube in the forward and reverse directions, which is specifically manifested in that the threshold voltage Vth and the holding voltage Vhold of the gate tube in the forward and reverse directions have a difference of about 0.2V. In the crossbar structure adopted by the present invention, the memory cell is set at the intersection of the word line and the bit line, and the adjacent memory cells share the word line or the bit line. The lower electrode of the first layer of memory cells is connected to the word line, and the upper electrode is connected to the bit line. The lower electrode of the second layer of memory cells is connected to the bit line, and the upper electrode is connected to the word line. The practice in conventional memory is that when a certain memory cell is selected for operation, it does not matter whether the upper and lower electrodes of the memory cell are connected to the word line or the bit line. A voltage of V / 2 is directly applied to the word line, and a voltage of -V / 2 is applied to the bit line. Because the conventional memory using the crossbar structure is based on resistance storage, it does not pay attention to polarity. In 1S1C memory, polarity is quite sensitive. For example, when performing a write 1 operation, if a fixed word line applies a voltage of V / 2 and a fixed bit line applies a voltage of -V / 2, then for the cells whose upper electrodes are connected to the word line and the cells whose upper electrodes are connected to the bit line, the voltages on the write capacitors will be different due to the different directions in which the gate tubes are opened, thus affecting the uniformity of the overall state of the memory cell and easily causing data storage errors. The same phenomenon also exists for the read operation. If the read voltage values ​​applied to the word line and the bit line are fixed, the forward and reverse data readings will also be different due to the different forward and reverse conduction voltages of the gate tubes. This difference will reduce the read margin when designing the read circuit and easily cause read errors.

[0051] Therefore, in the present invention, different voltages are applied to the word lines and the bit lines according to the number of layers where the memory cells are located (ie, whether they are located in odd layers or even layers).

[0052] Read operation: if it is the nth layer, Vread+ is applied to the word line electrode connected to the top electrode of the memory cell, and Vread- is applied to the bit line electrode connected to the bottom electrode of the memory cell; if it is the n+1th layer, Vread+ is applied to the bit line electrode connected to the top electrode of the memory cell, and Vread- is applied to the word line electrode connected to the bottom electrode of the memory cell;

[0053] Write operation: if it is the nth layer, Vwrite+ is applied to the word line electrode connected to the top electrode of the memory cell, and Vwrite- is applied to the bit line electrode connected to the bottom electrode of the memory cell; if it is the n+1th layer, Vwrite+ is applied to the bit line electrode connected to the top electrode of the memory cell, and Vwrite- is applied to the word line electrode connected to the bottom electrode of the memory cell;

[0054] The nth layer unit and the n+1th layer unit share a word line, and the n+1th layer unit and the n+2th layer unit share a bit line;

[0055] Applying Vwrite+ and Vwrite- at both ends of the storage unit can form a voltage difference Vwrite at both ends of the storage unit, so that the voltage difference at both ends of the gate tube in the selected storage unit is greater than the threshold voltage Vth of the gate tube, the gate tube is turned on, and the capacitor is charged, so that the capacitor voltage Vc in the storage unit reaches a specific value. By designing two different Vwrites, two different capacitor voltages Vc are obtained, one of which is marked as state 0, and the other is marked as state 1, to achieve the function of data storage;

[0056] The data reading operation method includes applying a specific voltage (herein, Vread+ and Vread-) to a wire in a first wire layer connected to a selected storage cell and a wire in a second wire layer connected to a selected storage cell, so as to form a voltage difference Vread at both ends of the selected storage cell, so as to enable the gate tube in the storage cell in state 0 to be turned on and the gate tube in the storage cell in state 1 to be turned off, and the data state of the storage cell is determined by sensing the change of the current in the wire;

[0057] When reading and writing data, the voltage applied to the wire will not turn on the gate transistors in the unselected memory cells.

[0058] The following is further described in detail in conjunction with the preferred embodiments:

[0059] Embodiment 1:

[0060] An embodiment of the present invention provides a three-dimensional memory, wherein a gate threshold voltage Vth is selected to be 4V, and a holding voltage Vhold is selected to be 3V.

[0061] like Figure 2 As shown, when the data to be written is 0, the word line voltage 21 is set to 2.2V and the bit line voltage 23 is set to -2.2V. Since the initial capacitor voltage 22 is 0V, a voltage difference of 4.4V is formed at both ends of the gate tube, which is greater than the threshold voltage of 4V. The gate tube is turned on and the capacitor is charged. When the capacitor voltage 22 reaches 1.4V, the voltage at both ends of the gate tube begins to be less than the holding voltage of 3V, the gate tube is turned off, and the capacitor voltage 22 is maintained at 1.4V.

[0062] like Figure 3 As shown, when the data 1 to be written is set, the word line voltage 21 is -2.2V, and the bit line voltage 23 is 2.2V. Because the initial capacitor voltage 22 is 0V, a 4.4V voltage difference is formed at both ends of the gate tube, which is greater than the threshold voltage of 4V. The gate tube is turned on and the capacitor is charged. When the capacitor voltage 22 reaches -1.4V, the voltage at both ends of the gate tube begins to be less than the holding voltage of 3V, the gate tube is turned off, and the capacitor voltage 22 is maintained at -1.4V.

[0063] In this way, the capacitor voltage of 1.4V can be used to represent state 0, and the capacitor voltage of -1.4V can be used to represent state 1, realizing the function of data storage. When performing data writing operations, the voltage applied to the word line and the bit line is 2.2V or -2.2V, and the voltage of the capacitor in the storage unit is 1.4V or -1.4V. Therefore, for the half-selected unit and the unselected unit, the voltage across the gate tube is less than 4V, which is less than the threshold voltage. The gate tube will not be opened, and the stored data information will not be affected.

[0064] like Figure 4 As shown, when performing a data reading operation, the word line voltage 21 is 1.5V and the bit line voltage 23 is -1.5V, so that a voltage difference of 3V is generated across the storage unit. If the cell being read is in state 0, that is, the capacitor voltage is 1.4V, the voltage across the gate tube is 1.6V, which is less than the threshold voltage, the gate tube will not open, and no read current will be generated; if the cell being read is in state 1, that is, the capacitor voltage is -1.4V, the voltage across the gate tube is 4.4V, which is greater than the threshold voltage, the gate tube will open, and a read current 42 with a large amplitude will be generated. Therefore, by sensing whether a large current is generated in the word line and the bit line, the data storage state of the selected storage unit can be determined.

[0065] When performing data reading operations, the voltage applied to the word line and bit line is 1.5V or -1.5V, and the voltage of the capacitor in the storage cell is 1.4V or -1.4V. Therefore, for half-selected cells and unselected cells, the voltage across the gate tube is less than 4V, which is less than the threshold voltage. The gate tube will not open and the data information stored in it will not be affected.

[0066] Data reading and data writing can also realize the whole row operation. When performing data reading operation, the word line voltage shared by the row of cells is set to 1.5V, and then the voltage on the bit line connected to each cell is set to -1.5V. By reading the magnitude of the current on each bit line, the storage state of the storage cell can be sensed; when performing data writing operation, the word line voltage shared by the row of cells is first set to 2.2V, and then the bit line voltage connected to the storage cell that needs to be written to 0 is set to -2.2V, and the write 0 operation can be completed. Then the word line voltage shared by the row of cells is set to -2.2V, and then the bit line voltage connected to the storage cell that needs to be written to 1 is set to 2.2V, and the write 1 operation can be completed. Through the above method, the row operation of the storage cell can be realized.

[0067] Embodiment 2:

[0068] The method for preparing a three-dimensional memory provided by an embodiment of the present invention comprises the following steps:

[0069] (1) Using magnetron sputtering to grow multiple parallel strip electrodes W with a thickness of 100 nm on a silicon substrate;

[0070] (2) Using PECVD to grow a layer of SiO2 as an insulating layer with a thickness of 100 nm;

[0071] (3) selectively etching a number of small holes in SiO2 by dry etching, the small holes are etched to the electrode tungsten, the small holes are arranged in a square shape, and each small hole is located directly above the strip electrode;

[0072] (4) Using magnetron sputtering, 20 nm GeTe9 and 100 nm W were grown in the small hole in sequence;

[0073] (5) 20 nm SiO2 is grown in the small hole using PECVD;

[0074] (6) growing a plurality of parallel strip electrodes W by magnetron sputtering, with a thickness of 100 nm, wherein the strip electrodes W are perpendicular to the strip electrodes W grown in step (1);

[0075] (7) Repeat (2) to (6), and the position of the holes formed in each layer is offset by 2d in the horizontal direction compared with the holes formed in the previous layer (d is the characteristic size of the hole);

[0076] (8) Use dry etching to etch out the pads of each electrode layer in turn.

[0077] like Figure 6 As shown, it is a schematic top view of a partial area of ​​the 1S1C memory of the present invention. The area shown in the figure is a top view of a certain intersection area of ​​a word line electrode and a bit line electrode. The memory cells are all provided with the intersection area of ​​the word line electrode and the bit line electrode. In the figure, three circular holes at different positions can be seen, indicating that the holes of each layer are at different positions in the horizontal direction. Because the 1S1C memory proposed by the present invention is realized by etching holes in the insulating layer and filling the holes with functional layer materials, after the holes in each layer are filled with materials, the surface formed will have depressions or protrusions. Therefore, when the second layer of 1S1C memory is still etched at this position in the horizontal direction to form holes, the shape of the obtained holes will be affected by the shape of the previous holes, resulting in the performance of the 1S1C memory cells with a higher number of layers being affected, and the error of the shape will be accumulated. The higher the number of layers, the worse the shape of the holes will be. Therefore, in the present invention, the hole position of each layer is offset by 2 hole feature sizes compared with the previous layer. Because the edge morphology of the hole will also be affected, this will avoid the influence of the surface morphology caused by the previous layer on the performance of the 1S1C unit of the subsequent layer. The above are preferred embodiments of the present invention. Any changes made according to the technical solution of the present invention, as long as the resulting functions do not exceed the scope of the technical solution of the present invention, belong to the protection scope of the present invention.

[0078] It will be easily understood by those skilled in the art that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A three-dimensional memory, characterized in that: The three-dimensional memory is composed of a multi-layer structure periodically arranged in a vertical direction, wherein the multi-layer structure includes a first wire layer, a first capacitor layer, a first gate tube layer, a second wire layer, a second capacitor layer, and a second gate tube layer; The first conductor layer is composed of a plurality of conductors parallel to each other; The first gate tube layer includes a plurality of gate tubes, and the lower electrode of each gate tube in the first gate tube layer is connected to a wire in the first wire layer; The first capacitor layer includes a plurality of capacitors, and the lower electrode of each capacitor in the first capacitor layer is connected to the upper electrode of a gate tube in the first gate tube layer; The second conductor layer includes a plurality of parallel conductors, and the upper electrode of each capacitor in the first capacitor layer is connected to a conductor in the second conductor layer; The second gate tube layer includes a plurality of gate tubes, and the lower electrode of each gate tube in the second gate tube layer is connected to a wire in the second wire layer; The second capacitor layer includes a plurality of capacitors, and the lower electrode of each capacitor in the second capacitor layer is connected to the upper electrode of a gate tube in the second gate tube layer, and the upper electrode of each capacitor in the second capacitor layer is connected to a wire in the first wire layer of the multilayer structure arranged in the next period; each pair of capacitors and gate tubes connected share the connected electrodes; the lower electrode of each gate tube is the wire connected thereto; and the upper electrode of each capacitor is the wire connected thereto.

2. The three-dimensional memory according to claim 1, characterized in that: The first gate tube layer and the second gate tube layer are both composed of an array of a plurality of gate tubes evenly distributed; The first capacitor layer and the second capacitor layer are both composed of arrays consisting of a plurality of capacitors evenly distributed.

3. The three-dimensional memory according to claim 1, wherein: The second conductor layer is composed of a plurality of conductors which are parallel to each other and form a certain angle with the conductors of the first conductor layer in the horizontal direction.

4. The three-dimensional memory according to claim 3, characterized in that: The angle is greater than 0 and less than or equal to 90 degrees.

5. The three-dimensional memory according to claim 1, wherein: The capacitor in the first capacitor layer is the same as the capacitor in the second capacitor layer, and the gate tube in the first gate tube layer is the same as the gate tube in the second gate tube layer.

6. The three-dimensional memory according to any one of claims 1 to 5, characterized in that: The gate tubes in the first gate tube layer and the second gate tube layer both have bidirectional conduction characteristics and have a forward threshold voltage Vth+ and a forward holding voltage Vhold+ in the forward direction, and a reverse threshold voltage Vth- and a reverse holding voltage Vhold- in the reverse direction.

7. A data operation method based on the three-dimensional memory according to any one of claims 1 to 6, characterized in that: The data operation method includes a data reading operation method and a data writing operation method: (1) determining the layer of the three-dimensional memory in which the storage unit to be operated is located; (2) When a data read operation is required, if it is the nth layer, a positive read voltage Vread+ is applied to the word line electrode connected to the top electrode of the memory cell, and a reverse read voltage Vread- is applied to the bit line electrode connected to the bottom electrode of the memory cell; if it is the n+1th layer, a positive read voltage Vread+ is applied to the bit line electrode connected to the top electrode of the memory cell, and a reverse read voltage Vread- is applied to the word line electrode connected to the bottom electrode of the memory cell; When a data write operation is required, if it is the nth layer, a forward write voltage Vwrite+ is applied to the word line electrode connected to the top electrode of the memory cell, and a reverse write voltage Vwrite- is applied to the bit line electrode connected to the bottom electrode of the memory cell; if it is the n+1th layer, a forward write voltage Vwrite+ is applied to the bit line electrode connected to the top electrode of the memory cell, and a reverse write voltage Vwrite- is applied to the word line electrode connected to the bottom electrode of the memory cell; The nth layer unit and the n+1th layer unit share a word line, the n+1th layer unit and the n+2th layer unit share a bit line, and n is a positive integer greater than or equal to 1, and generally less than or equal to 1000.

8. The data operation method according to claim 7, characterized in that: A forward write voltage Vwrite+ and a reverse write voltage Vwrite- are applied to both ends of the storage unit respectively, so that a voltage difference Vwrite is formed at both ends of the storage unit. When the voltage difference at both ends of the gate tube in the selected storage unit is greater than the threshold voltage Vth of the gate tube, the gate tube is turned on to charge the capacitor, so that the capacitor voltage Vc in the storage unit reaches a specific value Vwrite-Vhold. By designing two different Vwrites, two different capacitor voltages Vc are obtained, one of which is marked as state 0, and the other is marked as state 1, so as to realize the function of data storage; wherein when the capacitor is charged, the voltage at both ends of the gate tube will drop, and when the voltage at both ends of the gate tube drops to less than Vhold, the charging will stop, and the corresponding capacitor voltage at this time is the specific value Vwrite-Vhold.

9. The data operation method according to claim 7, characterized in that: Data read and write operations can be implemented either bit-by-bit or row-wide. The whole row operation includes: applying a word line voltage V1 to a conductor shared by the memory cells in the row, and applying a bit line voltage V2 to another conductor connected to the corresponding memory cell according to the operation to be performed by each memory cell.

10. A method for preparing a three-dimensional memory according to any one of claims 1 to 6, characterized in that: The steps include: (1) forming a first electrode layer consisting of a plurality of parallel strip electrodes on a substrate of a memory cell; (2) forming a first insulating layer on the first electrode layer; (3) selectively etching away the first insulating layer, leaving a plurality of hole arrays penetrating the first insulating layer, wherein the holes are all located directly above the strip electrodes of the first electrode layer; (4) forming a first gate tube layer, a second electrode layer and a first dielectric layer in sequence in the hole; (5) forming a third electrode layer composed of a plurality of mutually unconnected and parallel strip electrodes, which is perpendicular to the strip electrodes of the first electrode layer in a horizontal direction, and the hole is located at the intersection of the first electrode layer and the third electrode layer; (6) repeating steps (2) to (5) in sequence, and the position of the holes formed in each layer is offset by 2d in the horizontal direction from the holes formed in the previous layer, until the target number of three-dimensional memory layers is obtained; where d is the characteristic size of the hole; (7) Etching out the interface of each electrode layer to obtain the three-dimensional memory.

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