Data transmission circuit, method, chip and electronic device based on signal conversion

Abstract

The application provides a data transmission circuit and method based on signal conversion, a chip and an electronic device, and belongs to the field of circuits.The data transmission circuit based on signal conversion comprises a first conversion module and a second conversion module.The first conversion module is used for receiving a parallel signal from a first clock domain and converting the parallel signal into a serial signal of a second clock domain, wherein the frequency of the first clock domain is less than the frequency of the second clock domain.The second conversion module is used for receiving the serial signal and converting the serial signal into the parallel signal.The scheme realizes the transmission of the parallel signal from the first conversion module to the second conversion module within a first clock cycle.By applying the data transmission circuit based on signal conversion to transmit signals between FPGAs, a large number of signals can be transmitted from one FPGA to another FPGA within a clock cycle, thereby reducing the difficulty of circuit design and timing convergence.

Description

Technical Field

[0001] This application relates to the technical field of circuits, and more specifically, to a data transmission circuit, method, chip, and electronic device based on signal conversion. Background Technology

[0002] As chip designs become increasingly larger, a single FPGA (Field Programmable Gate Array) is often insufficient to accommodate a circuit design. Therefore, a circuit design needs to be divided into multiple sub-circuits, with each sub-circuit corresponding to an FPGA.

[0003] For synchronization circuits involving multiple FPGAs, a large number of signals need to be transmitted from one FPGA to another within a single clock cycle. However, current computing methods struggle to transmit such large numbers of signals within a single clock cycle, increasing the difficulty of circuit design and timing closure, and making it challenging to segment the synchronization circuit. Summary of the Invention

[0004] This application provides a data transmission circuit, method, chip, and electronic device based on signal conversion to solve the problem in the prior art that it is difficult to transmit a large number of signals from one FPGA to another within one clock cycle.

[0005] This application provides a data transmission circuit based on signal conversion, including a first conversion module and a second conversion module. The first conversion module is used to receive a parallel signal from a first clock domain and convert the parallel signal into a serial signal from a second clock domain, wherein the frequency of the first clock domain is less than the frequency of the second clock domain. The second conversion module is used to receive the serial signal and convert the serial signal into the parallel signal.

[0006] In this embodiment, by converting a parallel signal from a relatively low-frequency first clock domain into a faster-frequency second clock domain, the serial signal can be transmitted to the second conversion module more quickly due to the faster transmission rate in the faster clock domain. The second conversion module then converts the serial signal back into a parallel signal, thus enabling the parallel signal to be transmitted from the first conversion module to the second conversion module within one first clock cycle. By applying this signal conversion-based data transmission circuit between FPGAs, a large number of signals can be transmitted from one FPGA to another within one clock cycle, thereby reducing the difficulty of circuit design and timing convergence.

[0007] In conjunction with the technical solution provided in the first aspect above, in some possible implementations, when the parallel signal is an N-bit parallel signal, the frequency of the second clock domain is not less than N times the frequency of the first clock domain, where N is a positive integer greater than or equal to 2.

[0008] In this embodiment, since the frequency of the second clock domain is not less than N times the frequency of the first clock domain, the first conversion module can transmit the serial signal to the second conversion module within one slow clock domain cycle after converting the parallel signal into a serial signal. This enables the parallel signal converted by the second conversion module to meet the requirements of the synchronization circuit and improves the applicability of this solution.

[0009] In conjunction with the technical solution provided in the first aspect above, in some possible implementations, the second conversion module includes: a counter for numbering the received serial signals; and a conversion unit for obtaining the position of each serial signal in the parallel signal based on the numbering of each serial signal by the counter, and converting the serial signal into the parallel signal based on the position of each serial signal in the parallel signal.

[0010] In this embodiment, since the position of each serial signal in the parallel signal is determined by a counter number, when converting the serial signal to a parallel signal, it is only necessary to transmit each serial signal to its corresponding position in the parallel signal to obtain the parallel signal. This eliminates the need for methods like shift registers that generate parallel signals by placing the most recently received serial data in the least significant bit and pushing other serial signals to higher positions, thus reducing the data processing load on the second conversion module.

[0011] In conjunction with the technical solution provided in the first aspect above, in some possible implementations, the data transmission circuit based on signal conversion further includes: a signal delay module, used to receive the serial signal, and use a preset tap value to delay the received serial signal, and send the delayed serial signal to the second conversion module.

[0012] In this embodiment, the received serial signal is delayed by a signal delay module, which can prevent metastability and improve the reliability of data transmission.

[0013] In conjunction with the technical solution provided in the first aspect above, in some possible implementations, the signal delay module is further configured to receive a training serial signal, and delay the training serial signal using an initial tap value, wherein the training serial signal is obtained by conversion based on an initial training parallel signal; correspondingly, the second conversion module is further configured to convert the signal-delayed training serial signal into a target training parallel signal; the signal delay module is further configured to modify the initial tap value, and delay the next received training serial signal using the modified initial tap value, until the target training parallel signal converted by the second conversion module meets the cutoff condition; the signal delay module is further configured to obtain the preset tap value based on the initial tap value obtained each time it is modified.

[0014] In this embodiment, the signal delay module is trained by training the serial signal to obtain a preset tap value, thereby ensuring that no metastability occurs after the received serial signal is delayed using the preset tap value.

[0015] In conjunction with the technical solution provided in the first aspect above, in some possible implementations, the cutoff condition includes: after the target training parallel signal is consistent with the initial training parallel signal, the target training parallel signal becomes inconsistent with the initial training parallel signal.

[0016] In this embodiment, when the target training parallel signal is inconsistent with the initial training parallel signal, the signal delay module no longer modifies the initial tap value, thereby obtaining the range of the initial tap value corresponding to when the target training parallel signal is consistent with the initial training parallel signal, and thus obtaining an accurate preset tap value.

[0017] In conjunction with the technical solution provided in the first aspect above, in some possible implementations, the training serial signal includes two alternately transmitted serial signals.

[0018] In this embodiment, by using two alternately transmitted serial signals as training serial signals, the problem of the second conversion module being unable to detect a new training serial signal due to data transmission errors after receiving the training serial signal can be prevented, thus avoiding the problem of always maintaining the training serial signal before the data transmission error occurred.

[0019] In conjunction with the technical solution provided in the first aspect above, in some possible implementations, the first conversion module is further configured to convert the parallel signal into a serial signal in the second clock domain, and then send the serial signal after delaying it by a specified number of second clock domain periods; correspondingly, the second conversion module is specifically configured to receive the serial signal after delaying it by the specified number of second clock domain periods.

[0020] In this embodiment, the first conversion module delays the serial signal by a specified number of second clock domain cycles before sending the serial signal to the second conversion module, so that the second conversion module receives the serial signal after a specified number of second clock domain cycles, which can effectively reduce the workload of the second conversion module.

[0021] In conjunction with the technical solution provided in the first aspect above, in some possible implementations, after the first conversion module converts the parallel signal into a serial signal in the second clock domain, it is further used to convert the serial signal into a DDR (Double Data Rate) signal, and then convert the DDR signal into a differential signal for transmission to the second conversion module.

[0022] In this embodiment, converting the serial signal into a DDR signal can further improve the data transmission rate. At the same time, converting the DDR signal into a differential signal can reduce the impact of external electromagnetic interference on signal transmission and improve the reliability of data transmission.

[0023] Secondly, this application provides a chip comprising: a first FPGA for converting a parallel signal in a first clock domain into a serial signal in a second clock domain, wherein the frequency of the first clock domain is less than the frequency of the second clock domain; and a second FPGA connected to the first FPGA for receiving the serial signal and converting the serial signal into the parallel signal.

[0024] Thirdly, this application provides an electronic device, including a signal conversion-based data transmission circuit provided by any possible implementation of the first aspect embodiment and / or in combination with the first aspect embodiment, as well as a first module and a second module, wherein the first module and the second module transmit data through the signal conversion-based data transmission circuit.

[0025] Fourthly, this application provides a data transmission method based on signal conversion, applied to an electronic device including a first FPGA and a second FPGA, wherein the first FPGA is connected to the second FPGA, and the method includes: the first FPGA converting a parallel signal in a first clock domain into a serial signal in a second clock domain, wherein the frequency of the first clock domain is less than the frequency of the second clock domain; and the second FPGA receiving the serial signal and converting the serial signal into the parallel signal.

[0026] In conjunction with the technical solution provided in the fourth aspect above, in some possible implementations, the second FPGA receives the serial signal and converts the serial signal into the parallel signal, including: the second FPGA receives the serial signal, uses a preset tap value to delay the received serial signal, and converts the delayed serial signal into the parallel signal.

[0027] In conjunction with the technical solution provided in the fourth aspect above, in some possible implementations, the method further includes: the second FPGA receiving a training serial signal, delaying the training serial signal using an initial tap value, and converting the delayed training serial signal into a target training parallel signal, wherein the training serial signal is obtained based on the initial training parallel signal; the second FPGA modifying the initial tap value, and delaying the next received training serial signal using a shift value of the modified initial tap value, and converting the delayed training serial signal into a target training parallel signal, until the converted target training parallel signal meets the cutoff condition; the second FPGA obtaining the preset tap value based on the initial tap value obtained from each modification.

[0028] In conjunction with the technical solution provided in the fourth aspect above, in some possible implementations, the cutoff condition includes: after the target training parallel signal is consistent with the initial training parallel signal, the target training parallel signal becomes inconsistent with the initial training parallel signal.

[0029] In conjunction with the technical solution provided in the fourth aspect above, in some possible implementations, the training serial signal includes two alternately transmitted training serial signals. Attached Figure Description

[0030] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0031] Figure 1 This is a structural block diagram of a data transmission circuit based on signal conversion, as shown in an embodiment of this application.

[0032] Figure 2 This is a signal timing diagram of a serial signal shown in an embodiment of this application;

[0033] Figure 3 This is a signal timing diagram illustrating a signal transmission process according to an embodiment of this application;

[0034] Figure 4 This is a block diagram illustrating another data transmission circuit based on signal conversion, as shown in an embodiment of this application.

[0035] Figure 5 This is a structural block diagram illustrating a chip including a first FPGA and a second FPGA, as shown in an embodiment of this application.

[0036] Figure 6 This is a structural block diagram of an electronic device shown in an embodiment of this application;

[0037] Figure 7 This is a schematic flowchart illustrating a data transmission method based on signal conversion, as shown in an embodiment of this application. Detailed Implementation

[0038] The terms “first”, “second”, etc., are used only for distinguishing descriptions and do not indicate a sequence number, nor should they be interpreted as indicating or implying relative importance.

[0039] In the description of this application, unless otherwise expressly specified and limited, the terms "set" and "connection" shall be interpreted broadly, for example, as a fixed connection, a detachable connection, or an integral connection; as a mechanical connection or an electrical connection; as a direct connection or an indirect connection through an intermediate medium; or as a connection within two components.

[0040] The technical solution of this application will now be clearly and completely described with reference to the accompanying drawings.

[0041] Please see Figure 1 , Figure 1 The present application provides a structural block diagram of a data transmission circuit based on signal conversion, which includes a first conversion module and a second conversion module.

[0042] The first conversion module is used to receive parallel signals from a first clock domain and convert the parallel signals into serial signals from a second clock domain, wherein the frequency of the first clock domain is less than the frequency of the second clock domain.

[0043] The second conversion module is used to receive serial signals and convert them into parallel signals.

[0044] The frequencies of the first and second clock domains can be set according to actual needs, as long as the frequency of the first clock domain is less than the frequency of the second clock domain. For example, the frequency of the first clock domain is 200Hz, and the frequency of the second clock domain is 10MHz.

[0045] The first conversion module and the second conversion module can be located in the same FPGA, or they can be located in different FPGAs. For example, the first conversion module can be located in the first FPGA, and the second conversion module can be located in the second FPGA. This example is for illustrative purposes only and should not be construed as limiting the scope of this application.

[0046] It is understandable that, in order for the parallel signal converted by the second conversion module to meet the requirements of the synchronization circuit, when the parallel signal is an N-bit parallel signal, the frequency of the second clock domain is not less than N times the frequency of the first clock domain, where N is an integer greater than or equal to 2.

[0047] For example, when the parallel signal is a 4-bit parallel signal, if the frequency of the first clock domain is 10MHz, then the frequency of the second clock domain needs to be greater than 40MHz. The part greater than 40MHz is used for ending the last bit of the serial-to-parallel conversion, sending the packet header, timing relaxation, etc.

[0048] In one implementation, after the first conversion module converts the parallel signal into a serial signal, it can continue to convert the serial signal into a DDR signal, and then convert the DDR signal into a differential signal for transmission, thereby reducing the impact of external electromagnetic interference on signal transmission.

[0049] To facilitate the second conversion module's recognition of the serial signal, a preset data header can be added before the serial signal. For example, the data header could be "11". For instance, when the serial signal is "1010", the serial signal transmitted from the first conversion module to the second conversion module could be "111010". In this case, when the second conversion module detects the "11" in the serial signal, it can determine that the following "1010" is the required data. The examples of data headers and serial signals provided here are for illustrative purposes only and should not be construed as limiting the scope of this application.

[0050] To reduce the workload of the second conversion module, after the first conversion module converts the parallel signal into a serial signal in the second clock domain, in one implementation, the first conversion module can delay for several second clock domain cycles before sending the serial signal to the second conversion module. Correspondingly, the second conversion module receives the serial signal after a specified number of second clock domain cycles.

[0051] For example, the first conversion module could delay the serial signal by two second clock domain cycles before sending it to the second conversion module, and the second conversion module could similarly delay the reception of the serial signal by two second clock domain cycles. For easier understanding, please refer to [link to relevant documentation]. Figure 2 ,like Figure 2As shown, the serial signal "111010" is delayed by two second clock domain cycles before being transmitted. This delay of two second clock domain cycles is merely an example for ease of understanding and should not be taken as a limitation of this application.

[0052] To better understand the data transmission process described above, please refer to [link / reference]. Figure 3 , Figure 3 This is a timing diagram of the signal transmission process.

[0053] like Figure 3 As shown, the first conversion module converts the parallel signal 0xA from the first clock domain into a serial signal "1010" in the second clock domain and adds a data header "11". Then, the serial signal "111010" with the data header added is delayed by two second clock domain cycles and sent to the second conversion module.

[0054] After receiving the serial signal "111010", the second conversion module converts the serial signal into a parallel signal OxA in the first clock domain, thus completing the transmission of the parallel signal OxA from the first conversion module to the second conversion module.

[0055] It is understandable that when the second conversion module converts the serial signal into a parallel signal, it can use a shift register to generate a parallel signal, placing the latest received serial data in the least significant bit and shifting other serial signals to higher positions, thereby converting the serial signal into a parallel signal.

[0056] For example, when the parallel signal is a 4-bit parallel signal, after receiving the first serial signal, the first serial signal is transmitted to the least significant bit of the parallel signal, i.e., the fourth bit; after receiving the second serial signal, the first serial signal is shifted from the fourth bit to the third bit, and the second serial signal is transmitted to the least significant bit of the parallel signal; after receiving the third serial signal, the first serial signal is shifted from the third bit to the second bit, the second serial signal is shifted from the fourth bit to the third bit, and the third serial signal is transmitted to the least significant bit of the parallel signal; after receiving the fourth serial signal, the first serial signal is shifted from the second bit to the first bit, the second serial signal is shifted from the third bit to the second bit, the third serial signal is shifted from the fourth bit to the third bit, and the third serial signal is transmitted to the least significant bit of the parallel signal, thus obtaining a 4-bit parallel signal.

[0057] Alternatively, the second conversion module may further include a counter and a conversion unit. The counter is used to number the received serial signals. The conversion unit is used to determine the position of each serial signal in the parallel signal based on the numbering of each serial signal by the counter, and to convert the serial signal into the parallel signal based on the position of each serial signal in the parallel signal.

[0058] Since the position of each serial signal in the parallel signal is determined by the counter number, when converting the serial signal into a parallel signal, it is only necessary to transmit each serial signal to its corresponding position in the parallel signal according to the number in each serial signal to obtain the parallel signal.

[0059] For example, if the parallel signal is a 4-bit parallel signal, when the first serial signal is received, the counter assigns the serial signal number 1 to the parallel signal, and the conversion unit uses the serial signal numbered 1 as the first bit of the parallel signal; when the second serial signal is received, the counter assigns the serial signal number 2 to the parallel signal, and the conversion unit uses the serial signal numbered 2 as the second bit of the parallel signal; when the third serial signal is received, the counter assigns the serial signal number 3 to the parallel signal, and the conversion unit uses the serial signal numbered 3 as the third bit of the parallel signal; when the fourth serial signal is received, the counter assigns the serial signal number 4 to the parallel signal, and the conversion unit uses the serial signal numbered 4 as the fourth bit of the parallel signal, thus obtaining a 4-bit parallel signal.

[0060] The aforementioned numbering can be binary encoding. For example, when the parallel signal is a 4-bit parallel signal, the first parallel signal can be numbered 00, the second parallel signal can be numbered 01, the third parallel signal can be numbered 10, and the fourth parallel signal can be numbered 11. This example is for illustrative purposes only and should not be construed as a limitation of this application.

[0061] Since the rising edge of a serial signal is not steep, when the second conversion module receives and samples the serial signal, it must ensure that the sampling does not capture the middle of the rising or falling edge. Therefore, a signal delay module is incorporated into the signal conversion-based data transmission circuit. This module delays the received serial signal, preventing metastability and improving data transmission reliability.

[0062] Specifically, the signal delay module receives the serial signal and delays it using a preset tap value before sending the delayed serial signal to the second conversion module. The tap value is a dynamically set counting parameter that adjusts the signal delay time.

[0063] For example, if the preset tap value represents a delay of 1 ps (picosecond), then the signal delay module will delay all received serial signals by 1 ps.

[0064] It is understandable that the specific value of the preset tap value can be pre-set, or it can be obtained by training the initial tap value using a training serial signal.

[0065] Optionally, the signal delay module can be a Xilinx primitive module, which can fine-tune the initial tap value of the serial data by configuring parameters.

[0066] The method of training an initial tap value using a training serial signal to obtain a preset tap value can be as follows: A signal delay module receives the training serial signal and delays it using the initial tap value, wherein the training serial signal is obtained by conversion based on an initial training parallel signal. A second conversion module is further used to convert the signal-delayed training serial signal into a target training parallel signal. The signal delay module is also used to modify the initial tap value and use the shift value of the modified initial tap value to delay the next received training serial signal until the target training parallel signal converted by the second conversion module meets the cutoff condition. The signal delay module is also used to obtain the preset tap value based on the initial tap value obtained from each modification.

[0067] When modifying the initial tap value of the signal delay module, it can be done by increasing or decreasing a fixed value each time, such as increasing it by 7 ps. If the initial tap value represents a delay of 0 ps, ​​then after the first modification, the modified initial tap value represents a delay of 7 ps. Similarly, after the second modification, the modified initial tap value represents a delay of 14 ps, and so on. This example is for illustrative purposes only and should not be construed as a limitation of this application.

[0068] Optionally, the above cutoff condition can be that the target training parallel signal is consistent with the initial training parallel signal.

[0069] For example, the signal delay module uses the initial tap value to delay the training serial signal. After the second conversion module converts the signal-delayed training serial signal into the target training parallel signal, if the target training parallel signal is consistent with the initial training parallel signal, the initial tap value is used as the preset tap value.

[0070] If the target training parallel signal is inconsistent with the initial training parallel signal, the signal delay module modifies the initial tap value and uses the modified initial tap value to delay the next received training serial signal. If the second conversion module converts the signal-delayed training serial signal to obtain the target training parallel signal that is consistent with the initial training parallel signal, the modified initial tap value is used as the preset tap value.

[0071] If the target training parallel signal is inconsistent with the initial training parallel signal, the signal delay module modifies the initial tap value again until the converted target training parallel signal meets the cutoff condition.

[0072] Optionally, the cutoff condition can also be that after the target training parallel signal and the initial training parallel signal are consistent, the target training parallel signal becomes inconsistent with the initial training parallel signal. That is, the current target training parallel signal is inconsistent with the initial training parallel signal, and there was a previous instance where the converted target training parallel signal was consistent with the initial training parallel signal.

[0073] For example, the signal delay module uses an initial tap value to delay the training serial signal. The second conversion module converts the signal-delayed training serial signal into a target training parallel signal. The signal delay module modifies the initial tap value and uses the modified initial tap value to delay the next received training serial signal, so that the second conversion module converts the signal-delayed training serial signal into a target training parallel signal. It is determined whether the target training parallel signal is consistent with the initial training parallel signal. If they are inconsistent, and there has been a previous instance where the target training parallel signal and the initial training parallel signal were consistent, a preset tap value is obtained based on the initial delay tap value corresponding to each previous instance where the target training parallel signal and the initial training parallel signal were consistent.

[0074] If the target training parallel signal is consistent with the initial training parallel signal, or if the target training parallel signal has never been consistent with the initial training parallel signal before, the signal delay module modifies the initial tap value again and uses the modified initial tap value to delay the next received training serial signal, so that the second conversion module converts the signal-delayed training serial signal into the target training parallel signal, until the converted target training parallel signal meets the cutoff condition.

[0075] Specifically, when determining that the target training parallel signal is inconsistent with the initial training parallel signal, and prior to this, the target training parallel signal has been consistent with the initial training parallel signal, if only one such instance occurred before, then the corresponding initial delay tap value is used as the preset tap value. If only two instances occurred before, then the average of the two corresponding initial delay tap values ​​is used as the preset tap value. If the number of instances where the target training parallel signal was consistent with the initial training parallel signal is greater than three, then the average of the initial delay tap value corresponding to the first instance of consistency and the last instance of consistency can be used as the preset tap value; or, the average of the initial delay tap values ​​corresponding to each instance of consistency can be used as the initial delay tap value.

[0076] Understandably, a processor can be incorporated into the signal conversion-based data transmission circuit to determine whether the target training parallel signal matches the initial training parallel signal. In this case, the processor is connected to the second conversion module to receive the target training parallel signal converted by the second conversion module and compare it with the pre-acquired initial training parallel signal. The specific structure of the signal conversion-based data transmission circuit is as follows: Figure 4 As shown.

[0077] Optionally, the initial tap value can also be modified through the processor control signal delay module.

[0078] The data transmission circuit based on signal conversion provided in this application embodiment can be used for data transmission between component A and component B.

[0079] In one implementation, component A and component B transmit data via a signal conversion-based data transmission circuit. Specifically, component A is connected to a first conversion module, which receives the parallel signal sent by component A and converts it into a serial signal in a second clock domain. A second conversion module is connected to component B, receives the serial signal sent by the first conversion module, converts the serial signal into a parallel signal, and then sends it to component B.

[0080] In another implementation, the first conversion module can be integrated into component A, and the second conversion module can be integrated into component B. In this case, the first conversion module converts the parallel signal in component A into a serial signal in the second clock domain, and the second conversion module receives the serial signal sent by the first conversion module and converts the serial signal into a serial signal, thereby realizing data transmission between component A and component B.

[0081] The aforementioned component A and component B can be any two circuits, devices, or electronic devices that need to transmit data. For example, component A and component B can be two different chips or two different FPGAs.

[0082] Based on the same technical concept, this application also provides a chip including a first FPGA and a second FPGA. The first FPGA is used to convert a parallel signal in a first clock domain into a serial signal in a second clock domain, wherein the frequency of the first clock domain is lower than the frequency of the second clock domain. The second FPGA is connected to the first FPGA and is used to receive the serial signal and convert it into a parallel signal.

[0083] The first FPGA can either convert a parallel signal in the first clock domain generated by itself into a serial signal in the second clock domain, or it can receive a parallel signal in the first clock domain from the outside and convert it into a serial signal in the second clock domain.

[0084] Optionally, the first FPGA may include the first conversion module described above, and the second FPGA may include the second conversion module described above, so that the first FPGA and the second FPGA can implement the above functions. For ease of understanding, please refer to [link to documentation]. Figure 5 .

[0085] The chip including the first FPGA and the second FPGA provided in this application embodiment has the same implementation principle and technical effect as the aforementioned data transmission circuit embodiment based on signal conversion. For the sake of brevity, any parts not mentioned in this embodiment can be referred to the corresponding content in the aforementioned data transmission circuit embodiment based on signal conversion.

[0086] It is understood that the aforementioned data transmission circuit can also be applied within electronic devices to complete data transmission between different modules within the electronic device. Based on this, this application also provides an electronic device, including a signal conversion-based data transmission circuit, a first module, and a second module. For ease of understanding, please refer to [link to relevant documentation]. Figure 6 .

[0087] The first module and the second module transmit data through a data transmission circuit based on signal conversion. Specifically, the first module is connected to the first conversion module, which receives the parallel signal sent by the first module and converts it into a serial signal in the second clock domain. The second conversion module is connected to the second module, which receives the serial signal sent by the first conversion module, converts the serial signal into a parallel signal, and then sends it to the second module.

[0088] The data transmission circuit based on signal conversion in this application embodiment has the same implementation principle and technical effect as the aforementioned data transmission circuit based on signal conversion embodiment. For the sake of brevity, any parts not mentioned in this embodiment can be referred to the corresponding content in the aforementioned data transmission circuit based on signal conversion embodiment.

[0089] Please see Figure 7 , Figure 7 This is a flowchart illustrating a data transmission method based on signal conversion, provided in an embodiment of this application. This data transmission method is applied to an electronic device including a first FPGA and a second FPGA, wherein the first FPGA and the second FPGA are connected. The following will be combined with... Figure 7 The steps involved are explained.

[0090] S100: The first FPGA converts the parallel signal in the first clock domain into a serial signal in the second clock domain.

[0091] The frequency of the first clock domain is lower than the frequency of the second clock domain.

[0092] S200: The second FPGA receives the serial signal and converts the serial signal into a parallel signal.

[0093] In one implementation, the specific process of the second FPGA receiving a serial signal and converting the serial signal into a parallel signal can be as follows: the second FPGA receives the serial signal, uses a preset tap value to delay the received serial signal, and converts the delayed serial signal into a parallel signal.

[0094] Optionally, the specific process of obtaining the aforementioned preset tap value can be as follows: the second FPGA receives the training serial signal, delays the training serial signal using the initial tap value, and converts the delayed training serial signal into a target training parallel signal, wherein the training serial signal is obtained based on the initial training parallel signal; the second FPGA modifies the initial tap value, delays the next received training serial signal using the modified initial tap value, and converts the delayed training serial signal into a target training parallel signal, until the converted target training parallel signal meets the cutoff condition; the second FPGA obtains the preset tap value based on the initial tap value obtained from each modification.

[0095] Optionally, the cutoff condition can be that after the target training parallel signal is consistent with the initial training parallel signal, the target training parallel signal becomes inconsistent with the initial training parallel signal.

[0096] To prevent the second FPGA from failing to detect a new training serial signal after receiving the training serial signal due to a data transmission error, thus causing it to always retain the training serial signal before the data transmission error occurred, the first FPGA can send two parallel training signals alternately. That is, the training serial signal received by the second FPGA includes two alternately sent training serial signals.

[0097] The specific implementation method for obtaining the preset tap value has been clearly described above, and will not be repeated here for the sake of brevity.

[0098] The data transmission method based on signal conversion provided in this application has the same implementation principle and technical effect as the aforementioned data transmission circuit embodiment. For the sake of brevity, any parts not mentioned in the method embodiment can be referred to the corresponding content in the aforementioned data transmission circuit embodiment.

[0099] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A signal conversion-based data transmission circuit, characterized by comprising: include: A first conversion module is configured to receive a parallel signal from a first clock domain and convert the parallel signal into a serial signal from a second clock domain, wherein the frequency of the first clock domain is less than the frequency of the second clock domain. The second conversion module is used to receive the serial signal and convert the serial signal into the parallel signal; A signal delay module is used to receive the serial signal, delay the received serial signal using a preset tap value, and send the delayed serial signal to the second conversion module. The second conversion module includes: A counter is used to number each bit of the received serial signal; The conversion unit is used to obtain the position of each serial signal in the parallel signal based on the number of each serial signal by the counter, and to convert the serial signal into the parallel signal based on the position of each serial signal in the parallel signal.

2. The data transmission circuit based on signal conversion according to claim 1, characterized in that, When the parallel signal is an N-bit parallel signal, the frequency of the second clock domain is not less than or equal to N times the frequency of the first clock domain, where N is an integer greater than or equal to 2.

3. The data transmission circuit based on signal conversion according to claim 1, characterized in that, The signal delay module is also used to receive the training serial signal and delay the training serial signal using an initial tap value, wherein the training serial signal is obtained by conversion based on the initial training parallel signal. The second conversion module is also used to convert the delayed training serial signal into a target training parallel signal; The signal delay module is also used to modify the initial tap value and use the modified initial tap value to delay the next received training serial signal until the target training parallel signal converted by the second conversion module meets the cutoff condition. The signal delay module is also used to obtain the preset tap value based on the initial tap value obtained from each modification.

4. The signal conversion based data transmission circuit of claim 3, wherein, The cutoff conditions include: After the target training parallel signal becomes consistent with the initial training parallel signal, a discrepancy arises between the target training parallel signal and the initial training parallel signal.

5. The signal conversion based data transmission circuit of claim 3, wherein, The training serial signal consists of two alternately transmitted serial signals.

6. The data transmission circuit based on signal conversion according to claim 1, characterized in that, The first conversion module is further configured to convert the parallel signal into a serial signal in the second clock domain, and then delay the serial signal by a specified number of second clock domain periods before sending it. Accordingly, the second conversion module is specifically used to receive the serial signal with a delay of the specified number of second clock domain cycles.

7. The signal conversion based data transmission circuit of claim 1, wherein, After the first conversion module converts the parallel signal into a serial signal in the second clock domain, it is also used to convert the serial signal into a DDR signal, and then convert the DDR signal into a differential signal and transmit it to the second conversion module.

8. A chip, characterized by include: A first FPGA is used to convert a parallel signal in a first clock domain into a serial signal in a second clock domain, wherein the frequency of the first clock domain is less than the frequency of the second clock domain. A second FPGA is connected to the first FPGA. The second FPGA is used to receive the serial signal and delay the received serial signal using a preset tap value, converting the delayed serial signal into the parallel signal. The second FPGA includes a second conversion module. The second conversion module includes: A counter is used to number each bit of the received serial signal; The conversion unit is used to obtain the position of each serial signal in the parallel signal based on the number of each serial signal by the counter, and to convert the serial signal into the parallel signal based on the position of each serial signal in the parallel signal.

9. An electronic device, comprising: include: The data transmission circuit based on signal conversion as described in any one of claims 1-7; First module; The second module, the first module and the second module transmit data through the signal conversion-based data transmission circuit.

10. A data transmission method based on signal conversion, characterized by, An electronic device comprising a first FPGA and a second FPGA, wherein the first FPGA is connected to the second FPGA, the method comprising: The first FPGA converts a parallel signal in a first clock domain into a serial signal in a second clock domain, wherein the frequency of the first clock domain is less than the frequency of the second clock domain. The second FPGA receives the serial signal and uses a preset tap value to delay the received serial signal, converting the delayed serial signal into the parallel signal. The second FPGA includes a second conversion module; The second conversion module includes a counter and a conversion unit. The counter is used to number each received serial signal. The conversion unit is used to obtain the position of each serial signal in the parallel signal based on the numbering of each serial signal by the counter, and to convert the serial signal into the parallel signal based on the position of each serial signal in the parallel signal.

11. The method of claim 10, wherein, The method further includes: The second FPGA receives the training serial signal, delays the training serial signal using an initial tap value, and converts the delayed training serial signal into a target training parallel signal, wherein the training serial signal is obtained based on the initial training parallel signal. The second FPGA modifies the initial tap value and uses the modified initial tap value to delay the next received training serial signal, and converts the delayed training serial signal into a target training parallel signal until the converted target training parallel signal meets the cutoff condition. The second FPGA obtains the preset tap value based on the initial tap value obtained from each modification.

12. The method of claim 11, wherein, The cutoff conditions include: After the target training parallel signal becomes consistent with the initial training parallel signal, a discrepancy arises between the target training parallel signal and the initial training parallel signal.

13. The method of claim 11, wherein, The training serial signal consists of two alternately transmitted serial signals.

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