A MOS device based on HVCMOS platform and its manufacturing method

Abstract

The invention discloses a MOS device based on an HVCMOS platform and a manufacturing method thereof, and relates to the technical field of semiconductor integrated circuit manufacturing. The method comprises: manufacturing a first well region and a second well region on a substrate; manufacturing a hard mask on all well region sides; injecting impurities above the second well region so that an N-drift region is formed below a field oxygen isolation region in the second well region; manufacturing field oxides in all field oxygen isolation regions; removing the hard mask, and while performing N-type impurity anti-penetration injection into an active region for forming a source, a drain and a gate of a first MOS device in the first well region, simultaneously performing N-type impurity anti-penetration injection into an active region for forming a source and a drain in the second well region; manufacturing a gate and performing annealing activation after N+ ions are injected into a P-ion region; and obtaining a manufactured MOS device after forming a source, a drain and a gate on the first MOS device and the second MOS device. The method effectively reduces the manufacturing cost of the MOS device.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor integrated circuit manufacturing, and in particular to a MOS device based on a HVCMOS platform and a manufacturing method thereof. Background Art

[0002] High voltage complementary metal oxide semiconductor (HVCMOS) devices are a process platform that integrates high voltage metal-oxide-semiconductor field-effect transistors (MOSFET) and low voltage MOSFET devices. The chips produced using this process platform can integrate low voltage 5V CMOS devices for core logic control in the same chip, and also integrate high voltage MOSFET devices for I / O interface, level shift, or high voltage power switch. Compared with the conventional low voltage CMOS process, high voltage resistant devices are added, and its process flow and high voltage device structure are different from those of the conventional low voltage CMOS process.

[0003] In HVCMOS devices, the high voltage MOSFET of one of the devices is a high voltage N-type metal oxide semiconductor (Highvoltage NMOS, HVNMOS), such as Figure 1 As shown, compared with the low-voltage device, the high-voltage NMOS has an additional N-type drift region ND. The withstand voltage between the N-type drift region ND and the P-well region below it determines the source-drain breakdown voltage of the HVNMOS device. At the junction of the N+ region and the ND region, the interface of the PN junction is not smooth, and there is a peak electric field in the X region. In practical applications, the gate is usually not directly grounded. When the gate voltage exceeds its threshold voltage Vt, the HVNMOS is turned on, and a large current is generated between the source and the drain. And the current will increase with the increase of gate voltage. In the path of this current from drain to source, the current density is the largest in the N+ region due to the shallow junction depth. Under the high bias voltage at the drain end, the dense current will generate hot carriers, which will induce premature breakdown at the peak electric field in the X region and burn the HVNMOS. In order to solve the above problems, the conventional approach is to add an N-type drift region formed by high-voltage photolithography and high-energy injection under the source and drain respectively, so as to eliminate the peak electric field under the N+ region. However, this method requires an additional photolithography and high-energy ion injection, which increases the manufacturing cost of the device. Summary of the invention

[0004] Based on this, it is necessary to provide a MOS device based on the HVCMOS platform and a manufacturing method thereof to address the above technical problems, so as to solve the problem that in the existing HVNMOS device manufacturing process, an additional photolithography and high-energy ion implantation are required, resulting in increased manufacturing costs of the device.

[0005] In a first aspect, the present invention provides a method for manufacturing a MOS device based on a HVCMOS platform, comprising:

[0006] providing a substrate;

[0007] Fabricating a first well region of a first MOS device at a first voltage level and a second well region of a second MOS device at a second voltage level on the substrate;

[0008] Making hard masks on all well region sides to form active regions covered by masks and field oxygen isolation regions not covered by masks;

[0009] Implanting impurities above the second well region so that an N-drift region is formed below the field oxygen isolation region in the second well region;

[0010] Forming field oxides in all field oxide isolation regions, wherein the field oxides extend into all well regions by a preset distance and protrude from all well regions and extend upward;

[0011] The hard mask is removed, and when N-type impurity anti-penetration injection is performed on the active area in the first well region for forming the source, drain and gate of the first MOS device, N-type impurity anti-penetration injection is performed on the active area in the second well region for forming the source and drain, so that an N-type buffer doping region is formed between the two N-drift regions of the source and between the two N-drift regions of the drain;

[0012] A gate is manufactured and annealed and activated after N+ ions are injected into the P- ion region, wherein the doping concentration of the P- ions and the doping concentration of the N- ions are both lower than the doping concentration of the N+ ions, so that the annealed P- ion region wraps the N+ ion region;

[0013] After forming a source, a drain and a gate on the first MOS device and the second MOS device, a manufactured MOS device is obtained.

[0014] The above scheme has the following beneficial effects:

[0015] The MOS device manufacturing method based on the HVCMOS platform of the present invention performs P-ion anti-punch-through injection on the source active region and the drain active region of the MOS device at the second voltage level during P-ion anti-punch-through injection to form a P-ion region, thereby weakening the peak electric field under the N+ region; the method does not require the use of special high-energy ion injection equipment, and effectively reduces the manufacturing cost of the device.

[0016] Optionally, the first well region includes a P-well region and an N-well region, and after removing the hard mask, N-ion anti-penetration implantation and threshold voltage adjustment implantation are performed on the N-well region.

[0017] Optionally, a hard mask is formed on all sides of the well region to form an active region covered by the mask and a field oxygen isolation region not covered by the mask, including:

[0018] Growing a pad oxide layer on all well region sides of the substrate by thermal oxidation, and growing silicon nitride on the pad oxide layer by low pressure chemical vapor deposition to form a mask;

[0019] The mask is photoetched with a preset pattern to form the hard mask, the area covered by the mask is the active area, and the area not covered by the mask is the field oxygen isolation area.

[0020] Optionally, impurities are implanted above the second well region so that an N-drift region is formed below the field oxygen isolation region in the second well region, including:

[0021] Phosphorus impurities are injected into a set area above the second well region, so that the phosphorus impurities pass through the pad oxide layer in the second well region but not through the active area covered by the hard mask, and extend downward in the field oxygen isolation area not covered by the mask to form an N-drift region.

[0022] Optionally, the implantation dose of the phosphorus impurities is in the range of 5E12-2E13, and the implantation energy is less than 100Kev.

[0023] Optionally, the implantation energy of the P-ion anti-punch-through implantation is in the range of 300Kev-800Kev, and the implantation dose is in the range of 1E12-1E13.

[0024] Optionally, the doping concentration of the N+ ions is 1E20 / cm 3 Magnitude.

[0025] In a second aspect, the present invention provides a MOS device based on a HVCMOS platform, comprising:

[0026] A substrate, on which a MOS device of a first voltage level and a MOS device of a second voltage level are arranged;

[0027] The MOS device at the first voltage level includes a first well region disposed on the substrate, and the MOS device at the second voltage level includes a second well region disposed on the substrate; a source, a drain and a gate are disposed in the first well region and the second well region respectively;

[0028] N-drift regions are respectively arranged on both sides of the source and drain of the second well region, and a mixed region of P- ions and N+ ions is formed between the two N-drift regions of the source and between the two N-drift regions of the drain;

[0029] A field oxide layer is disposed above the N-drift region at intervals, extends into all the well regions by a preset distance, and protrudes from all the well regions to extend upward.

[0030] The above scheme has the following beneficial effects:

[0031] The MOS device based on the HVCMOS platform of the present invention sets a P- ion and N+ ion mixing region between two N- drift regions of the source of the MOS device at the second voltage level and between two N- drift regions of the drain, which effectively weakens the peak electric field under the N+ region and improves the withstand voltage level of the MOS device.

[0032] Optionally, the depths of the first well region and the second well region are greater than 3 μm.

[0033] Optionally, the depth of the P- ion and N+ ion mixed zone ranges from 0.5 μm to 1.0 μm. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative labor.

[0035] Figure 1 It is a structural schematic diagram of a HVCMOS device in the prior art;

[0036] Figure 2 It is a flow chart of a method for manufacturing a MOS device based on a HVCMOS platform provided in one embodiment of the present invention;

[0037] Figure 3-1 is a schematic diagram of manufacturing a well region on a substrate provided in one embodiment of the present invention;

[0038] Figure 3-2 is a schematic diagram of manufacturing a hard mask on a substrate provided in one embodiment of the present invention;

[0039] Figure 3-3 is a schematic diagram of manufacturing an N-drift region provided in one embodiment of the present invention;

[0040] Figure 3-4 is a schematic diagram of a field oxide manufacturing method provided in one embodiment of the present invention;

[0041] Figure 3-5 is a schematic diagram of anti-penetration ion implantation provided in one embodiment of the present invention;

[0042] Figure 3-6 is a schematic diagram of gate manufacturing provided in one embodiment of the present invention;

[0043] Figure 3-7 is a schematic diagram of a metal layer for making a source electrode, a drain electrode and a gate electrode provided in one embodiment of the present invention;

[0044] Figure 4 It is a schematic diagram of a MOS device structure based on a HVCMOS platform provided in one embodiment of the present invention;

[0045] The symbols are explained as follows:

[0046] 1. Substrate; 2. Pad oxide layer; 3. Hard mask; 4. Photoresist; 5. Field oxide; 6. Gate; 7. Insulating dielectric layer. DETAILED DESCRIPTION

[0047] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all of the embodiments.

[0048] It should be understood that the embodiments set forth below represent the necessary information to enable those skilled in the art to implement the embodiments and illustrate the best mode for implementing the embodiments. After reading the following description in light of the accompanying drawings, those skilled in the art will understand the concepts of the present disclosure and will recognize applications of these concepts not specifically mentioned herein. It should be understood that these concepts and applications fall within the scope of the present disclosure and the appended claims.

[0049] It should also be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, the first element may be referred to as the second element, and similarly, the second element may be referred to as the first element without departing from the scope of the present disclosure. As used herein, the term "and / or" includes any and all combinations of one or more related listed items.

[0050] It should also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or intervening elements may be present. Conversely, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements.

[0051] It should also be understood that the terms "upper", "lower", "left", "right", "front", "back", "bottom", "middle", "middle", "top", etc. may be used herein to describe various elements, and the indicated orientation or position relationship is based on the orientation or position relationship shown in the accompanying drawings, which is only for the convenience of describing the present invention and simplifying the description, and does not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore these elements should not be limited by these terms.

[0052] These terms are only used to distinguish one element from another element. For example, a first element can be referred to as an "upper" element, and similarly, a second element can be referred to as an "upper" element according to the relative orientation of these elements without departing from the scope of the present disclosure.

[0053] It is further understood that the terms “comprises,” “includes,” “including” and / or “comprising” when used herein specify the presence of stated features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof.

[0054] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. It will be further understood that the terms used herein should be interpreted as having a meaning consistent with their meaning in the context of this specification and the relevant technology, and will not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0055] In one embodiment, a method is provided as follows Figure 2 A method for manufacturing a MOS device based on a HVCMOS platform is shown, the method comprising:

[0056] Step S100: providing a substrate.

[0057] In this embodiment, the substrate is a wafer.

[0058] Step S200: forming a first well region of a first MOS device at a first voltage level and a second well region of a second MOS device at a second voltage level on a substrate.

[0059] See also Figure 3-1, on the above-mentioned substrate 1, by means of photolithography and ion implantation, a first well region of a first MOS device at a first voltage level, namely, a P well region of a low voltage MOS device LVNMOS and an N well region of a low voltage MOS device LVPMOS, is manufactured; and a second well region of a second MOS device at a second voltage level, namely, a P well region of a high voltage MOS device HVNMOS, is manufactured.

[0060] In this embodiment, the second voltage level is greater than the first voltage level, and the first well region includes a P well region and an N well region, and is not limited to Figure 3-1 The depth of the first well region and the second well region is greater than 3.0 μm, thereby increasing the threshold voltage of the MOS device.

[0061] Step S300: forming hard masks on all well region sides to form active regions covered by masks and field oxygen isolation regions not covered by masks.

[0062] See also Figure 3-2 After the first well region and the second well region are formed on the substrate, a pad oxide layer 2 is formed on all well region sides of the substrate by thermal oxidation growth, and then silicon nitride (SiN) is grown on top of the pad oxide layer 2 by low pressure chemical vapor deposition (Low Pressure Chemical Vapor Deposition, LPVCD) as a mask; low pressure chemical vapor deposition is widely used for silicon oxide, nitride, and polysilicon deposition. The process is performed in a tube furnace and requires a very high temperature.

[0063] The mask is photoetched using a photomask having an active region pattern to expose the field oxide region to obtain a hard mask 3, thereby forming an active region covered by the mask and a field oxide isolation region not covered by the mask.

[0064] In this embodiment, the pad oxide layer is silicon dioxide (SiO2) and its thickness ranges from 150 -300 , and the thickness range of the hard mask formed by SiN is: 1500 -3000 The main function of the oxide pad in the manufacturing process is to act as a buffer. It is usually used as a pad for silicon nitride (SiN) to offset the stress of SiN and prevent the photoresist from contaminating the wafer surface.

[0065] Step S400: implanting impurities above the second well region to form an N-drift region below the field oxygen isolation region in the second well region.

[0066] See also Figure 3-3, a photoresist 4 is arranged on the hard mask 3 manufactured as above, the photoresist 4 completely covers the MOS device area of ​​the first voltage level and the partial area of ​​the MOS device of the second voltage level, and only exposes the source and drain areas of the MOS device of the second voltage level, and the photoresist 4 can be made of thermoplastic plastic (pr); then, phosphorus (P) impurities are photolithographically and implanted in the area exposed by the photoresist 4, and the implantation dose range is 5E12-2E13, and the implantation energy is less than 100Kev, so that the phosphorus ions can penetrate the area exposed by the hard mask 3, that is, the SiO2 of the pad oxide layer, but cannot penetrate the SiN covered area of ​​the hard mask 3; thereby, an N-drift region ND is formed by extending downward below the field oxygen isolation area of ​​the pad oxide layer 2 without mask coverage; the function of the N-drift region ND is to improve the breakdown voltage of the HVNMOS device, and the existence of the N-drift region ND also plays a buffering role between the source and the drain.

[0067] Step S500: forming field oxides in all field oxide isolation regions, wherein the field oxides extend into all well regions by a preset distance and protrude from all well regions and extend upward.

[0068] See also Figure 3-4 , remove the above photoresist, and use the local oxidation isolation of silicon (Locos) technology to form a field oxide 5 in the field oxide isolation area. The thickness range of the field oxide 5 is: 4000 -8000 , while being oxidized, the N-drift region ND diffuses downward, and the junction depth ranges from 1μm to 2.5μm.

[0069] Step S600: Remove the hard mask, and while performing N-type impurity anti-penetration injection into the active area in the first well region for forming the source, drain and gate of the first MOS device, simultaneously perform N-type impurity anti-penetration injection into the active area in the second well region for forming the source and drain, so that an N-type buffer doping region is formed between the two N-drift regions of the source and between the two N-drift regions of the drain.

[0070] See also Figure 3-5 , the hard mask formed by SiN is removed by wet method, and the P-well region of the MOS device LVNMOS of the first voltage level is subjected to photolithography and N-ion anti-penetration (N-APT) implantation, and then the threshold voltage adjustment (Vt) implantation is performed; the impurity of the N-ion anti-penetration implantation is boron (B), and the implantation depth is 0.5μm-1.5μm to ensure the withstand voltage level of the HVNMOS device.

[0071] In this embodiment, N-ion anti-punch-through injection can prevent the punch-through phenomenon caused by the source and drain distance of the MOS device at the first voltage level being too small; threshold voltage adjustment injection can adjust the threshold voltage of the MOS device, and is injected on the silicon surface with low injection energy.

[0072] The P-well region of the MOS device LVPMOS of the first voltage level is subjected to photolithography and N-type impurity anti-penetration injection. At the same time, the active region of the source and the active region of the drain of the P-well region of the MOS device HVNMOS of the second voltage level are subjected to photolithography and N-type impurity anti-penetration injection, and then a threshold voltage adjustment injection is performed; the impurity of the N-type impurity anti-penetration injection is boron, the injection dose range is 1E12-1E13, the injection energy range is 300Kev-800Kev, and the injection depth range is 0.5μm-1.0μm, so as to ensure that the N-type impurity anti-penetration injection does not penetrate the field oxide.

[0073] Step S700: making a gate and injecting N+ ions into the P- ion region and then performing annealing activation, the doping concentration of the P- ions and the doping concentration of the N- ions are both lower than the doping concentration of the N+ ions, so that the annealed P- ion region wraps the N+ ion region.

[0074] See also Figure 3-6 , make the gate of the MOS device of the first voltage level and the gate 6 of the MOS device of the second voltage level, then make the N+ and P+ source and drain contacts of the MOS device of the first voltage level and the MOS device of the second voltage level, and perform normal annealing activation; in this process, the P- ion region in the MOS device HVNMOS of the second voltage level is also diffused, and its junction depth is greater than twice the N+ junction depth, so that the P- ion region completely wraps the N+ ion region, thereby replacing the region formed by additional lithography and high-energy implantation in the prior art.

[0075] In this embodiment, the doping concentration of P- ions and the ion doping concentration of the N- drift region are much smaller than the ion doping concentration of the N+ ion region. Usually, the doping concentration of the N+ ions is about 1E20 / cm 3 The doping concentration of N-ions and P-ions is 1E17 / cm 3 Magnitude.

[0076] Step S800: forming a source, a drain and a gate on the first MOS device and the second MOS device to obtain a manufactured MOS device.

[0077] See also Figure 3-7 , manufacturing an insulating dielectric layer, a contact hole, and metal electrodes corresponding to the source, drain, gate, and body regions of a MOS device at a first voltage level and a MOS device at a second voltage level, and obtaining a manufactured MOS device.

[0078] The MOS device manufacturing method based on the HVCMOS platform of this embodiment has the following characteristics:

[0079] (1) This method does not require the use of special high-energy ion implantation equipment, effectively reducing the manufacturing cost of the device.

[0080] (2) The injection energy of P-APT is low and insufficient to penetrate the field oxide, so it will not change the length of the N-drift region ND, nor will it reduce the drain-source breakdown voltage of the HVNMOS.

[0081] (3) It can weaken the peak electric field below N+ and avoid thermal breakdown in this area.

[0082] In one embodiment, a method is provided as follows Figure 4 The MOS device based on the HVCMOS platform shown includes:

[0083] A substrate 1 is provided on which MOS devices LVNMOS and LVPMOS of a first voltage level and a MOS device HVNMOS of a second voltage level are arranged.

[0084] The MOS device at the first voltage level includes a first well region arranged on the substrate 1, namely, the P well region of LVNMOS and the N well region of LVPMOS, and the MOS device at the second voltage level includes a second well region arranged on the substrate 1, namely, the P well region of HVNMOS; the first well region and the second well region are respectively provided with a source, a drain and a gate.

[0085] N-drift regions ND are respectively arranged on both sides of the source and drain of the second well region, and a mixed region of P- ions and N+ ions is formed between the two N-drift regions of the source and between the two N-drift regions of the drain.

[0086] The MOS device further comprises a field oxide 5, which is spaced above the N-drift region ND and between the source and drain of the MOS device at the first voltage level, and extends into all well regions by a preset distance and protrudes upward from all well regions.

[0087] Furthermore, the source, drain and gate of the MOS device are led out through metal electrodes and serve as electrodes of the HVCMOS device, which are connected to an external circuit.

[0088] Furthermore, the depths of the first well region and the second well region are greater than 3 μm to maintain a sufficient threshold voltage of the MOS device.

[0089] Furthermore, the depth of the P- ion and N+ ion mixed region ranges from 0.5 μm to 1.0 μm, which can improve the source-drain breakdown voltage of the MOS device, weaken the peak electric field under the N+, and prevent the MOS device from thermal breakdown.

[0090] Furthermore, the above-mentioned MOS device further includes an insulating dielectric layer 7, which is disposed on the upper surface of the entire HVCMOS device and has a preset thickness, so that the source, drain and gate of the MOS device are isolated from the outside.

[0091] In the MOS device based on the HVCMOS platform of this embodiment, a P- ion and N+ ion mixed region is set between the two N- drift regions of the source of the MOS device at the second voltage level and between the two N- drift regions of the drain, which effectively weakens the peak electric field under the N+ region and improves the voltage resistance level of the MOS device.

[0092] The embodiments described above are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included in the protection scope of the present invention.

Claims

1. A method for manufacturing a MOS device based on a HVCMOS platform, characterized in that: include: providing a substrate; Fabricating, on the substrate, a first well region of a first MOS device at a first voltage level and a second well region of a second MOS device at a second voltage level, wherein the second voltage level is higher than the first voltage level; Making hard masks on all well region sides to form active regions covered by masks and field oxygen isolation regions not covered by masks; Implanting impurities above the second well region so that an N-drift region is formed below the field oxygen isolation region in the second well region; Forming field oxides in all field oxide isolation regions, wherein the field oxides extend into all well regions by a preset distance and protrude from all well regions and extend upward; The hard mask is removed, and when N-type impurity anti-penetration injection is performed on the active area in the first well region for forming the source, drain and gate of the first MOS device, N-type impurity anti-penetration injection is performed on the active area in the second well region for forming the source and drain, so that an N-type buffer doping region is formed between the two N-drift regions of the source and between the two N-drift regions of the drain; A gate is fabricated and N+ ions are injected into the P- ion region and then annealed and activated. The doping concentration of the P- ions and the doping concentration of the N- ions are both lower than the doping concentration of the N+ ions, so that the annealed P- ion region wraps the N+ ion region from bottom to top; After forming the source, the drain, the gate and the metal electrodes corresponding to the body region on the first MOS device and the second MOS device, the manufactured MOS device is obtained.

2. The method for manufacturing a MOS device based on a HVCMOS platform according to claim 1, characterized in that: The first well region includes a P-well region and an N-well region. After removing the hard mask, N-ion penetration prevention implantation and threshold voltage adjustment implantation are performed on the N-well region.

3. The method for manufacturing a MOS device based on a HVCMOS platform according to claim 1, characterized in that: A hard mask is formed on all well region sides to form an active region covered by the mask and a field oxygen isolation region not covered by the mask, including: Growing a pad oxide layer on all well region sides of the substrate by thermal oxidation, and growing silicon nitride on the pad oxide layer by low pressure chemical vapor deposition to form a mask; The mask is photoetched with a preset pattern to form the hard mask, the area covered by the mask is the active area, and the area not covered by the mask is the field oxygen isolation area.

4. The method for manufacturing a MOS device based on a HVCMOS platform according to claim 3, characterized in that: Injecting impurities above the second well region so that an N-drift region is formed below the field oxygen isolation region in the second well region, comprising: Phosphorus impurities are injected into a set area above the second well region, so that the phosphorus impurities pass through the pad oxide layer in the second well region but not through the active area covered by the hard mask, and extend downward in the field oxygen isolation area not covered by the mask to form an N-drift region.

5. The method for manufacturing a MOS device based on a HVCMOS platform according to claim 4, characterized in that: The implantation dose of the phosphorus impurities ranges from 5E12 to 2E13, and the implantation energy is less than 100Kev.

6. The method for manufacturing a MOS device based on a HVCMOS platform according to claim 1, characterized in that: The injection energy range of the N-type impurity anti-through injection is 300Kev-800Kev, and the injection dose range is 1E12-1E13.

7. The method for manufacturing a MOS device based on a HVCMOS platform according to claim 1, characterized in that: The doping concentration of N+ ions is 1E20 / cm 3 Magnitude.

8. A MOS device based on a HVCMOS platform, characterized in that: include: a substrate, on which a MOS device of a first voltage level and a MOS device of a second voltage level are arranged, wherein the second voltage level is higher than the first voltage level; The MOS device at the first voltage level includes a first well region disposed on the substrate, and the MOS device at the second voltage level includes a second well region disposed on the substrate; a source, a drain and a gate are disposed in the first well region and the second well region respectively; N-drift regions are respectively arranged on both sides of the source and drain of the second well region, and a mixed region of P- ions and N+ ions is formed between the two N-drift regions of the source and between the two N-drift regions of the drain, and the P- ion region wraps the N+ ion region from bottom to top; A field oxide layer is disposed above the N-drift region at intervals, extends into all the well regions by a preset distance, and protrudes from all the well regions to extend upward.

9. The MOS device based on the HVCMOS platform according to claim 8, characterized in that: The depths of the first well region and the second well region are greater than 3 μm.

10. The MOS device based on the HVCMOS platform according to claim 8, characterized in that: The depth of the P- ion and N+ ion mixed zone ranges from 0.5 μm to 1.0 μm.

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