A buffer circuit for metering chip

Abstract

The present invention provides a buffer circuit applied to a metering chip. By performing electrostatic protection between the input and output ends of the buffer module, the buffer module generates a first signal based on an input signal; the input end of the first filter module is connected to the output end of the buffer module, the first filter module generates a second signal by filtering the first signal, and shortens the establishment time of the second signal; the input end of the second filter module is connected to the output end of the first filter module, the output end of the second filter module is connected to the subsequent load, and the second filter module outputs a driving signal by filtering the second signal. The problem that the voltage output by the buffer is offset and the electrostatic protection may fail due to the change of the driving signal of the subsequent load in the buffer with an off-chip large capacitor in the prior art is solved. The first filter module and the second filter module constitute a second-order filtering system, which enhances the anti-interference performance of the buffer circuit. The structure is simple and has wide applicability.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design and application, and in particular to a buffer circuit applied to a metering chip. Background Art

[0002] Traditional buffers use external resistors and capacitors to achieve filtering and charge pump functions. If the driving signal of the downstream load changes, the voltage output by the resistors and capacitors will change. However, if the external resistor of the buffer is removed, the electrostatic protection (ESD) of the buffer will fail, which will cause serious damage to the downstream load.

[0003] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because they are described in the background technology section of the present application. Summary of the invention

[0004] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a buffer circuit applied to a metering chip, which is used to solve the problem in the prior art that the voltage output by the buffer with a large external capacitor changes dramatically due to changes in the driving signal of the subsequent load and the electrostatic protection may fail.

[0005] To achieve the above-mentioned purpose and other related purposes, the present invention provides a buffer circuit applied to a metering chip, which is used to balance the driving signal of a subsequent load. The buffer circuit applied to the metering chip at least includes: a buffer module, a first filtering module and a second filtering module, wherein:

[0006] By performing electrostatic protection between the input end and the output end of the buffer module, the buffer module generates a first signal based on the input signal;

[0007] The input end of the first filtering module is connected to the output end of the buffer module, and the first filtering module generates a second signal by filtering the first signal and shortens the establishment time of the second signal;

[0008] The input end of the second filtering module is connected to the output end of the first filtering module, the output end of the second filtering module is connected to the subsequent load, and the second filtering module outputs the driving signal by filtering the second signal.

[0009] Optionally, the buffer module includes: a buffer unit, a first ESD unit and a second ESD unit, wherein: the first input end of the buffer unit is connected to the input signal; the first end of the first ESD unit is connected to the output end of the buffer unit; the second ESD unit is connected between the second end of the first ESD unit and the second input end of the buffer unit.

[0010] Optionally, the buffer unit comprises an operational amplifier, wherein an inverting terminal of the operational amplifier is connected to an input signal, and a non-inverting terminal of the operational amplifier is connected to the second ESD unit.

[0011] Optionally, the first ESD unit includes a first resistor; the second ESD unit includes a second resistor.

[0012] Optionally, the first filtering module includes: a third resistor, a first capacitor, a first port and a second port, wherein: the first end of the third resistor is connected to the output end of the buffer module; the first port is connected to the second end of the third resistor; the second port is connected to the first port; the first end of the first capacitor is connected to the connection point of the first port and the second port, and the second end of the first capacitor is connected to the reference ground.

[0013] Optionally, the resistance of the third resistor is between 10 ohms and 150 ohms.

[0014] Optionally, the second filtering module includes at least one filtering unit, wherein the number of the filtering units is equal to the number of subsequent-stage loads, and when the number of the filtering units is greater than 1, each of the filtering units is connected to a corresponding subsequent-stage load.

[0015] Optionally, the filtering unit includes a filtering resistor and a filtering capacitor, wherein the first end of the filtering resistor is connected to the output end of the first filtering module, and the second end of the filtering resistor is connected to a corresponding post-stage load; and the filtering capacitor is connected between the second end of the filtering resistor and a reference ground.

[0016] As described above, a buffer circuit applied to a metering chip of the present invention has the following beneficial effects:

[0017] 1) The buffer circuit applied to the metering chip of the present invention solves the problem in the prior art that the voltage output by the buffer may be offset and the electrostatic protection may fail due to the change of the driving signal of the subsequent load. The first filter module and the second filter module constitute a second-order filter system, which enhances the anti-interference ability of the buffer circuit.

[0018] 2) The buffer circuit applied to the metering chip of the present invention has a simple structure and wide applicability. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 FIG. 4 is a schematic diagram showing an exemplary buffer structure of the present invention.

[0020] Figure 2 A schematic diagram of the Thevenin equivalent analysis of an exemplary buffer of the present invention is shown.

[0021] Figure 3 It is a schematic structural diagram of a buffer circuit applied to a metering chip of the present invention.

[0022] Figure 4 It is a schematic diagram showing the buffer module of the present invention without electrostatic protection.

[0023] Figure 5 It is a schematic diagram showing the buffer module of the present invention for electrostatic protection.

[0024] Figure 6 It is a schematic diagram showing the amplitude-frequency curve of the buffer circuit applied to the metering chip of the present invention and the traditional buffer.

[0025] Description of Reference Numerals

[0026] 1 Buffer circuit for metering chip

[0027] 11 Buffer module

[0028] 111 Buffer unit

[0029] 112 First ESD Unit

[0030] 113 Second ESD unit

[0031] 12. First filter module

[0032] 13. Second filter module

[0033] 131 Filter Unit DETAILED DESCRIPTION

[0034] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0035] See also Figures 1 to 6It should be noted that the illustrations provided in this embodiment are only schematic illustrations of the basic concept of the present invention. The illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0036] Figure 1 A schematic diagram of a buffer architecture is shown, which includes: a buffer circuit, a filter circuit and a post-stage load, wherein the buffer circuit includes an operational amplifier Op1; the filter circuit includes: a resistor RL, a capacitor CL, a port VMO1 and a port VMI1, wherein the port VMO1 and the port VMI1 are externally connected to the pin VM1 (PAD) of the chip through a packaged metal bounding wire (bounding wire, the full name in English is binding wire, and the Chinese name is semiconductor bonding gold wire / gold wire. It is intended to bond the interface of the chip and the interface of the substrate with high-purity gold wire after treating the adhesive between the chip and the substrate to make it have better bonding performance. The composition is gold with a purity of 99.999%, and it is doped with elements such as silver, palladium, magnesium, iron, copper, and silicon; different elements are doped to adjust the hardness, rigidity, ductility, conductivity and other parameters of the gold wire); the post-stage load includes: Rload11, Rload12, Rload13,..., Rload1n, wherein n is a natural number greater than 1. Figure 1 The buffer shown has a simple structure and can provide a driving signal to a subsequent load only through an operational amplifier Op1, a resistor RL, and a capacitor CL.

[0037] Figure 2 The schematic diagram of performing Thevenin equivalent analysis on the buffer is shown, in which the operational amplifier Op1 is subjected to Thevenin equivalent analysis to obtain the current source Vout and the equivalent resistance Rout of the operational amplifier Op1; the capacitor CL provides a driving signal for the subsequent load, and the filter circuit composed of the resistor RL and the capacitor CL can isolate the influence of the signal fluctuation generated by the subsequent load on the output of the current source Vout, so the change of the subsequent load has little influence on the output of the current source Vout. It can be considered that the output of the current source Vout is a fixed value, and the value of the port VMI1 is:

[0038]

[0039] Among them, Rload=Rload11||Rload12||Rload13||···Rload1n, and “||” is the symbol for parallel connection.

[0040] like Figure 1 and Figure 2As shown, since the open-loop gain of the buffer is relatively high (the open-loop gain is the differential-mode voltage gain of the integrated operational amplifier in the absence of feedback resistance, and is the ratio of the output voltage of the integrated operational amplifier to the differential input voltage), the equivalent resistance Rout is of a relatively small magnitude, usually around ten ohms. In order to achieve a better filtering effect, the resistance RL is usually of the order of one hundred ohms. From the parallel law of the subsequent load, it can be seen that as the magnitude of the subsequent load decreases or the number of subsequent loads increases, the voltage of port VMI1 will inevitably decrease; similarly, as the magnitude of the subsequent load increases or the number of subsequent loads increases, the voltage of port VMI1 will inevitably increase, that is, the change of the subsequent load causes the voltage of port VMI1 to change, the instantaneous change of the subsequent load will reduce the voltage accuracy of port VMI1, and the timing switching of the subsequent load will introduce a relative error of port VMI1. In summary, the change of the subsequent load affects the accuracy of the subsequent circuit by affecting port VMI1.

[0041] Therefore, the present invention provides a buffer circuit applied to a metering chip, which is specifically implemented as follows:

[0042] like Figure 3 As shown, this embodiment provides a buffer circuit 1 applied to a metering chip, which is used to balance the driving signal of a subsequent load. The buffer circuit 1 applied to the metering chip includes: a buffer module 11, a first filter module 12 and a second filter module 13, wherein:

[0043] like Figure 3 As shown, by performing electrostatic protection between the input end and the output end of the buffer module 11 , the buffer module 11 generates the first signal Vout11 based on the input signal Vin2 .

[0044] Specifically, as an example, Figure 3As shown, the buffer module 11 includes: a buffer unit 111, a first ESD unit 112 and a second ESD unit 113, wherein: the first input end of the buffer unit 111 is connected to the input signal Vin2; the first end of the first ESD unit 112 is connected to the output end of the buffer unit 111; the second ESD unit 113 is connected between the second end of the first ESD unit 112 and the second input end of the buffer unit 111. More specifically, the buffer unit 111 includes an operational amplifier Op2, wherein the first input end of the operational amplifier Op2 is connected to the input signal Vin2, and the second input end of the operational amplifier Op2 is connected to the second ESD unit 113. In this example, the first input end of the operational amplifier Op2 is an inverting end, and the second input end of the operational amplifier Op2 is a non-inverting end; the first ESD unit 112 includes a first resistor R1; and the second ESD unit 113 includes a second resistor R2. It should be noted that the buffer unit 111, the first ESD unit 112 and the second ESD unit 113 constitute a buffer loop (i.e., a buffer loop). In the present embodiment, it specifically refers to a buffer loop composed of an operational amplifier Op2, a first resistor R1 and a second resistor R2. The buffer loop is used to balance the signal processing speed of the input end of the buffer module 11 with the signal processing speed of the output end. The introduction of the buffer loop is to reduce the sudden change of the signal between the input end and the output end in a short period of time.

[0045] More specifically, as an example, Figure 3 As shown, according to the relation (1), the signal relation value between the first port VMO2 and the second port VMI2 in the first filtering module 12 is obtained:

[0046]

[0047] Among them, the post-stage load includes: Rload21, Rload22, Rload23, . . . , Rload2n, where n is a natural number greater than 1; Rload2 = Rload21||Rload22||Rload23|| . . . Rload2n, and “||” is the symbol of parallel connection; the operational amplifier Op2 is subjected to the Thevenin equivalent analysis to obtain the equivalent resistance Rout2 of the operational amplifier Op2, where the process of the Thevenin equivalent analysis will not be elaborated here one by one.

[0048] Furthermore, if Figure 3As shown, reducing the resistance of the third resistor R3 in the first filtering module 12 can reduce the impact of the change of Rload2 on the second signal Vout12 output by the second port VMI2, and can also enable the first capacitor C1 in the first filtering module 12 to be quickly charged, thereby enabling the second signal Vout12 to be quickly established, so that the second signal Vout12 can provide a driving signal for the subsequent load more quickly.

[0049] Furthermore, when the first ESD unit 112 and the second ESD unit 113 are not provided in the buffer module 11, the structure of the buffer module 11 is as follows: Figure 4 As shown, the large electrostatic current is transmitted to the third resistor R3 through the chip pin VM2 (PAD), and then transmitted to the gate and drain of the PMOS tube M2 in the buffer unit 111 through the third resistor R3, causing the gate and drain of the PMOS tube M2 and the drain of the PMOS tube M4 in the buffer unit 111 to be broken down, resulting in the failure of the ESD protection effect of the buffer unit 111, wherein "ZAP" represents the large electrostatic current, and the "dashed arrow" represents the transmission direction of the large electrostatic current.

[0050] When the first ESD unit 112 and the second ESD unit 113 are provided in the buffer module 11, the structure of the buffer module 11 is as follows: Figure 5 As shown, the large electrostatic current is transmitted to the third resistor R3 through the pin VM2 (PAD) of the chip, and then transmitted to the gate and drain of the PMOS tube M2 in the buffer unit 111 through the third resistor R3. Due to the protection of the first ESD unit 112 and the second ESD unit 113, the gate and drain of the PMOS tube M2 and the drain of the PMOS tube M4 in the buffer unit 111 are protected, so that the buffer unit 111 has ESD protection capability.

[0051] It should be further explained that the buffer unit 111 includes but is not limited to the operational amplifier Op2, the first ESD unit 112 includes but is not limited to the first resistor R1, and the second ESD unit 113 includes but is not limited to the second resistor R2. The buffer module 11 can also be set through an ASIC chip (ASIC is the abbreviation of Application Specific Integrated Circuit. ASIC chip is an integrated circuit used for special applications. In the integrated circuit industry, it is considered to be an integrated circuit designed for a special purpose. ASIC chip technology is developing rapidly, and the forwarding performance between ASIC chips can usually reach 1Gbs or even higher, thus providing an excellent material basis for the switching matrix). The buffer module 11 can also be set through an IP core (IP core is Intellectual Property The abbreviation of IP core is a hardware description language program with specific circuit functions. The program is independent of the integrated circuit process and can be transplanted to different semiconductor processes to produce integrated circuit chips. The use of IP cores for electronic system design has the characteristics of convenient reference and easy modification of the functions of basic components. IP cores with complex functions and commercial value have intellectual property attributes. Although the market activities of IP cores are not yet standardized, there are still many integrated circuit design companies engaged in the design, development and marketing of IP cores. There are two types of IP cores. The hardware description language program that is independent of the process is called a soft core; the integrated circuit layout with a specific circuit function is called a hard core. Hard cores are generally not allowed to be changed. It is difficult to design integrated circuits using hard cores, but the success rate of tape-out will be greatly increased). As long as electrostatic protection can be performed between the input and output ends of the buffer module 11, so that the buffer module 11 generates the first signal Vout11 based on the input signal, any setting form of the buffer module 11 is applicable, and is not limited to this embodiment.

[0052] like Figure 3 As shown, the input end of the first filtering module 12 is connected to the output end of the buffer module 11 , and the first filtering module 12 generates the second signal Vout12 by filtering the first signal Vout11 , and shortens the establishment time of the second signal Vout12 .

[0053] Specifically, as an example, Figure 3As shown, the first filtering module 12 includes: a third resistor R3, a first capacitor C1, a first port VMO2 and a second port VMI2, wherein: a first end of the third resistor R3 is connected to the output end of the buffer module 11; the first port VMO2 is connected to the second end of the third resistor R3; the second port VMI2 is connected to the first port VMO2; a first end of the first capacitor C1 is connected to a connection point between the first port VMO2 and the second port VMI2, and a second end of the first capacitor C1 is connected to a reference ground GND. More specifically, the resistance value of the third resistor R3 is between 10 ohms and 150 ohms.

[0054] like Figure 3 As shown, the input end of the second filtering module 13 is connected to the output end of the first filtering module 12, and the output end of the second filtering module 13 is connected to the subsequent load. The second filtering module 13 outputs a driving signal through a filtering operation on the second signal Vout12, wherein the driving signal is used to balance the subsequent load, and the subsequent load includes: Rload21, Rload22, Rload23,..., Rload2n, wherein n is a natural number greater than 1; Rload2=Rload21||Rload22||Rload23||...Rload2n, and "||" is a symbol for parallel connection.

[0055] Specifically, as an example, Figure 3 As shown, the second filter module 13 includes at least one filter unit 131, wherein the number of the filter units 131 is equal to the number of the subsequent loads, and when the number of the filter units 131 is greater than 1, each filter unit 131 is connected to a corresponding subsequent load. More specifically, the filter unit 131 includes a filter resistor and a filter capacitor, wherein the first end of the filter resistor is connected to the output end of the first filter module, and the second end of the filter resistor is connected to a corresponding subsequent load; the filter capacitor is connected between the second end of the filter resistor and the reference ground GND, wherein the filter unit 131 connected to Rload21 includes a filter resistor RLM1 and a filter capacitor CLM1.

[0056] It should be noted that Figure 1 In the buffer architecture shown, the resistor RL is usually in the order of several hundred ohms, but in this embodiment, Figure 3 As shown, the resistance of the third resistor R3 is between 10 ohms and 150 ohms. Figure 1 Compared with the buffer, the charging speed of the first capacitor C1 is faster than that of the capacitor CL, so the establishment time of the second signal Vout12 is greatly shortened. In addition, the first filter module 12 and the second filter module 13 form a second-order filter system.

[0057] Figure 6The amplitude-frequency curves of the buffer circuit used in the metering chip and the traditional buffer are shown, where the transfer function of the amplitude-frequency curve of the traditional buffer is:

[0058]

[0059] Here, expression (3) is Figure 1 The transfer function of the amplitude-frequency curve of the buffer in the middle, the corresponding frequency fp1 expression is:

[0060]

[0061] In this embodiment, the transfer function of the amplitude-frequency curve corresponding to the first filtering module 12 and the second filtering module 13 is:

[0062]

[0063] Among them, the expressions of frequency fk1 and frequency fk2 corresponding to expression (5) are:

[0064]

[0065] If the signal of the second port VMI2 is to be guaranteed to reach a noise floor of -120 dB, the area enclosed by the amplitude-frequency curve and the frequency of the first filter module 12 and the second filter module 13 of this embodiment should be smaller than or equal to the area enclosed by the amplitude-frequency curve and the frequency of the traditional buffer. Figure 6 As shown, the area of ​​the shaded SA is less than or equal to the area of ​​the shaded SB (Note: After log analysis, the buffer circuit 1 applied to the metering chip will amplify the low-frequency signal, so Figure 6 There is a deviation between the visual area and the actual area). It should be noted that if Figure 3 As shown, the resistance value of the third resistor R3 is between 10 ohms and 150 ohms. As long as the parameters of the wave resistor RLM1 and the filter capacitor CLM1 are reasonably set in the filter unit 131 in the second filter module 13, the buffer circuit in this example can be made Figure 1 The buffer in the filter achieves better filtering effect.

[0066] This embodiment further provides a metering chip, which includes the buffer circuit applied to the metering chip described in this embodiment, and is used to measure the electric energy of the subsequent load and balance the driving signal of the subsequent load.

[0067] In summary, a buffer circuit applied to a metering chip of the present invention is used to balance the driving signal of the subsequent load. The buffer circuit applied to the metering chip at least includes: a buffer module, a first filter module and a second filter module, wherein: by performing electrostatic protection between the input end and the output end of the buffer module, the buffer module generates a first signal based on the input signal; the input end of the first filter module is connected to the output end of the buffer module, the first filter module generates a second signal by filtering the first signal, and shortens the establishment time of the second signal; the input end of the second filter module is connected to the output end of the first filter module, the output end of the second filter module is connected to the subsequent load, and the second filter module outputs the driving signal by filtering the second signal. The buffer circuit applied to the metering chip of the present invention solves the problem that the voltage output by the buffer with a large external capacitor in the prior art is offset due to the change of the driving signal of the subsequent load and the electrostatic protection may fail. The first filter module and the second filter module constitute a second-order filter system, which enhances the anti-interference performance of the buffer circuit. The buffer circuit applied to the metering chip of the present invention has a simple structure and is widely applicable. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0068] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A buffer circuit applied to a metering chip, used to balance the driving signal of a subsequent load, characterized in that: The buffer circuit applied to the metering chip at least includes: a buffer module, a first filter module and a second filter module, wherein: By performing electrostatic protection between the input end and the output end of the buffer module, the buffer module generates a first signal based on the input signal; the buffer module comprises: a buffer unit, a first ESD unit and a second ESD unit, wherein: the first input end of the buffer unit is connected to the input signal; the first end of the first ESD unit is connected to the output end of the buffer unit; the second ESD unit is connected between the second end of the first ESD unit and the second input end of the buffer unit; The input end of the first filtering module is connected to the output end of the buffer module, and the first filtering module generates a second signal by filtering the first signal, and shortens the establishment time of the second signal; the first filtering module includes: a third resistor, a first capacitor, a first port and a second port, wherein: the first end of the third resistor is connected to the output end of the buffer module; the first port is connected to the second end of the third resistor; the second port is connected to the first port; the first end of the first capacitor is connected to the connection point of the first port and the second port, and the second end of the first capacitor is connected to the reference ground; the resistance value of the third resistor is between 10 ohms and 150 ohms; The input end of the second filtering module is connected to the output end of the first filtering module, the output end of the second filtering module is connected to the subsequent load, and the second filtering module outputs the driving signal by filtering the second signal.

2. The buffer circuit for use in a metering chip according to claim 1, characterized in that: The buffer unit includes an operational amplifier, wherein a first input terminal of the operational amplifier is connected to an input signal, and a second input terminal of the operational amplifier is connected to the second ESD unit.

3. The buffer circuit for use in a metering chip according to claim 1, characterized in that: The first ESD unit includes a first resistor; the second ESD unit includes a second resistor.

4. The buffer circuit for use in a metering chip according to claim 1, characterized in that: The second filtering module includes at least one filtering unit, wherein the number of the filtering units is equal to the number of subsequent loads. When the number of the filtering units is greater than 1, each of the filtering units is connected to a corresponding subsequent load.

5. The buffer circuit for use in a metering chip according to claim 4, characterized in that: The filtering unit includes a filtering resistor and a filtering capacitor, wherein the first end of the filtering resistor is connected to the output end of the first filtering module, and the second end of the filtering resistor is connected to a corresponding post-stage load; the filtering capacitor is connected between the second end of the filtering resistor and a reference ground.

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