Array substrate, display panel and preparation method thereof

Abstract

The application discloses an array substrate, a display panel and a preparation method of the array substrate. The method comprises the following steps: sequentially forming a gate electrode and a gate insulating layer on a substrate; forming an active region on the gate insulating layer, wherein the active region is made of an oxide semiconductor material, and the active region is doped with an electron trapping element as a positive center; forming a source / drain electrode on the active region, and forming an insulating protective layer on the source / drain electrode. The application provides an array substrate, a display panel and a preparation method of the array substrate, which have better light stability and better performance.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to an array substrate, a display panel and a preparation method thereof. BACKGROUND

[0002] With the development of display panels, high aperture ratio, high refresh rate and other requirements are proposed for array substrates. In recent years, thin film transistors of oxide semiconductor materials have been rapidly developed in the field of array substrates due to their high mobility, good uniformity, small off-state current and other characteristics.

[0003] While pursuing the development of array substrate performance, its reliability problems also need to be improved. Among them, the light stability problem of thin film transistors of oxide semiconductor materials is related to display quality problems such as sand point defects, and improvement solutions are urgently needed. SUMMARY

[0004] In view of the above problems, the present application is proposed in order to provide an array substrate, a display panel and a preparation method thereof which overcome the above problems or at least partially solve the above problems.

[0005] In a first aspect, a preparation method of an array substrate is provided, comprising:

[0006] forming a gate electrode and a gate insulating layer on a substrate in sequence;

[0007] forming an active region on the gate insulating layer, the active region being made of an oxide semiconductor material, and the active region being doped with an electron trapping element as a positive center;

[0008] forming a source / drain electrode on the active region, and forming an insulating protective layer on the source / drain electrode.

[0009] Optionally, the electron trapping element includes any one or a combination of W, Ta and rare earth elements.

[0010] Optionally, the content of In element in the oxide semiconductor material is greater than the content of any other metal element.

[0011] Optionally, after forming the active region on the gate insulating layer, the method further comprises: forming a metal layer on the active region and performing an annealing process to reduce defects of the active region through the metal layer; and removing the metal layer.

[0012] Optionally, the metal layer is made of Al, Zn or Ta.

[0013] Optionally, the forming of the metal layer on the active region and the performing of the annealing process comprise: forming a metal layer with a thickness of 1000-3000 angstroms on the active region, and performing an annealing process at a temperature of 300-400℃.

[0014] Optionally, the forming the source-drain electrode on the active region comprises: forming a source-drain material layer on the active region; and patterning the source-drain material layer by using a dry etching process to form the source-drain electrode.

[0015] Optionally, the patterning the source-drain material layer by using a dry etching process comprises: patterning the source-drain material layer by using a dry etching process with an anisotropic etching device and an etching gas, wherein the etching gas contains only Cl2.

[0016] In a second aspect, an array substrate is provided, comprising:

[0017] a substrate, a thin film transistor layer and an insulating protective layer sequentially arranged on the substrate;

[0018] the thin film transistor layer comprises a gate, a gate insulating layer, an active region and a source-drain electrode;

[0019] the active region is made of an oxide semiconductor material, and the active region is doped with an electron trapping element as a positive center.

[0020] In a third aspect, a display panel is provided, comprising the array substrate of the second aspect and a pixel layer arranged on the array substrate.

[0021] The technical solutions provided in the embodiments of the present application have at least the following technical effects or advantages:

[0022] The array substrate and the display panel provided in the embodiments of the present application and the preparation method thereof use an oxide semiconductor material for the active region of the transistor, and the active region is doped with an electron trapping element as a positive center. In this way, even if the transistor in the pixel region generates photo-generated carriers (i.e. electrons) under the continuous irradiation of backlight, the photo-generated carriers in the active region can be captured by the electron trapping element, and the continuous and rapid photo-generated carrier recombination can be achieved. Thus, the negative bias temperature instability (NBTIS) of the transistor can continuously meet the requirements, and the display quality problems such as sand point defects caused by the characteristic shift of the transistor in the pixel region under the continuous irradiation of backlight can be avoided, thereby improving the light irradiation stability of the transistor and ensuring the reliability of the product.

[0023] The above description is only a summary of the technical solutions of the present application. In order to more clearly understand the technical means of the present application, the embodiments of the present application can be implemented according to the content of the specification, and in order to make the above and other purposes, characteristics and advantages of the present application more obvious and easy to understand, the specific embodiments of the present application are described below. BRIEF DESCRIPTION OF DRAWINGS

[0024] Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The accompanying drawings are included to provide a better understanding of the preferred embodiments, and are not intended to be a limitation on the application. Moreover, in the drawings, like reference numerals denote same or similar components. In the drawings:

[0025] Figure 1 Flow chart of the manufacturing method of the array substrate in the embodiment of the present application;

[0026] Figure 2 Process diagram of the manufacturing method of the array substrate in the embodiment of the present application Figure 1 ;

[0027] Figure 3 Process diagram of the manufacturing method of the array substrate in the embodiment of the present application Figure 2 ;

[0028] Figure 4 Process diagram of the manufacturing method of the array substrate in the embodiment of the present application Figure 3 ;

[0029] Figure 4 Process diagram of the manufacturing method of the array substrate in the embodiment of the present application Figure 6 ;

[0030] Figure 5 Process diagram of the manufacturing method of the array substrate in the embodiment of the present application Figure 7 ;

[0031] Figure 8 Comparison chart of the transistor parameters of the different processes for etching the source and drain in the embodiment of the present application;

[0032] Figure 9 Comparison chart of the active area of the transistor of the dry etching for preparing the source and drain in the embodiment of the present application;

[0033] Figure 6 Process diagram of the manufacturing method of the array substrate in the embodiment of the present application Figure 10 ;

[0034] Figure 7 Process diagram of the manufacturing method of the array substrate in the embodiment of the present application Figure 11 ;

[0035] Figure 8 Process diagram of the manufacturing method of the array substrate in the embodiment of the present application Figure 12 ;

[0036] Figure 9 Process diagram of the manufacturing method of the array substrate in the embodiment of the present application Figure 13 ;

[0037] Figure 14 Fig. 1 is a flow chart of a method for manufacturing an array substrate according to an embodiment of the present application;

[0038] Figure 1 Fig. 2 is a structural diagram of a display panel according to an embodiment of the present application. DETAILED DESCRIPTION

[0039] Exemplary embodiments of the present disclosure will be described in greater detail below with reference to the accompanying drawings.

[0040] Various structural diagrams according to embodiments of the present disclosure are shown in the accompanying drawings. These diagrams are not drawn to scale, in which certain details are exaggerated for the purpose of clarity, and certain details can be omitted. The shapes of various regions, layers, and the relative sizes and positional relationships among them shown in the diagrams are merely exemplary, and can be varied in actual implementation due to manufacturing tolerances or technical limitations, and regions / layers having different shapes, sizes, and relative positions can be additionally designed by those skilled in the art according to actual needs.

[0041] In the context of the present disclosure, when a layer / element is said to be located "on" another layer / element, the layer / element can be directly on the other layer / element, or there can be an intervening layer / element therebetween. In addition, if a layer / element is located "on" another layer / element in one orientation, it can be located "under" the other layer / element when the orientation is reversed. In the context of the present disclosure, similar or identical components can be indicated by the same or similar reference numerals.

[0042] In order to better understand the above technical solutions, the above technical solutions will be described in detail below in conjunction with specific embodiments. It should be understood that the embodiments of the present disclosure and the specific features in the embodiments are detailed descriptions of the technical solutions of the present application, rather than limitations of the technical solutions of the present application. In the case of no conflict, the technical features in the embodiments of the present application and the embodiments can be combined with each other.

[0043] The present application provides a method for manufacturing an array substrate, please refer to Figure 1 , Figures 2-10 Fig. 1 is a flow chart of a method for manufacturing an array substrate according to an embodiment of the present application;

[0044] Step S101, forming a gate electrode and a gate insulating layer on a substrate in sequence;

[0045] Step S102, forming an active region on the gate insulating layer, the active region adopts an oxide semiconductor material, and an electron trapping element as a positive center is doped in the active region;

[0046] Step S103: Form source and drain electrodes on the active region and form an insulating protective layer on the source and drain electrodes.

[0047] It should be noted that the array substrate provided in this application can be applied to liquid crystal display (LCD), organic electroluminescence display (OLED), light-emitting diode display (LED), etc., without limitation, and will not be listed one by one.

[0048] The following is combined with Figures 2-3 The implementation steps of the array substrate fabrication method provided in this application are described in detail:

[0049] A substrate 1 is provided, which may be a glass substrate or a semiconductor substrate, etc., without limitation.

[0050] Perform step S101, such as Figure 2 As shown, a gate 2 and a gate insulating layer 3 are sequentially formed on a substrate 1.

[0051] like Figure 3 As shown, the gate 2 can be fabricated by first forming a gate material layer, and then using a gate mask to pattern the gate material layer to form the gate 2. The material of the gate 2 can be metal or polysilicon. In an optional embodiment, the material of the gate 2 can be Cu to reduce the gate line resistance. In an optional embodiment, the gate 2 can also be a multi-layer structure, using composite metal layers to improve the adhesion between the metal and the substrate 1, avoiding metal diffusion and oxidation of the metal surface. For example, the gate 2 can be a three-layer structure, such as MTD / Cu / MTD (the top and bottom layers are MTD, and the middle layer is Cu) or MoNb / Cu / MoNb (the top and bottom layers are MoNb, and the middle layer is Cu).

[0052] like Figure 4 As shown, the gate insulating layer 3 can be fabricated by first forming a gate insulating material layer, and then using a mask to pattern the gate insulating material layer to form the gate insulating layer 3. The material of the gate insulating layer 3 can be an insulating material such as SiO2 or SiN. In optional embodiments, the gate insulating layer 3 can be a multi-layer structure, such as a SiO / SiON / SiN (upper layer is SiN, middle layer is SiON, and lower layer is SiO) triple-layer structure or a SiO / SiN (with thickened SiN) double-layer structure.

[0053] Perform step S102, such as Figure 4 As shown, an active region 4 is formed on the gate insulating layer 3.

[0054] like Figures 5-6 As shown, the active region 4 can be fabricated by first forming an active region material layer, and then patterning the active region material layer using an active region mask to form the active region 4. The active region 4 uses an oxide semiconductor material (e.g., indium gallium zinc oxide IGZO, indium tin zinc oxide ITZO, indium gallium tin oxide IGTO, etc.), which is also doped with an electron-trapping element as a positive charge center. In an optional embodiment, the doping atomic ratio of the electron-trapping element in the active region 4 is within 20%, for example, a doping atomic ratio of 10%. The electron-trapping element can be doped into the target material before depositing the active region material layer, or it can be doped into the active region 4 through a doping process after depositing the active region material layer; there are no limitations on this.

[0055] In optional embodiments, the electron-trapping element includes any one or more combinations of the following: W, Ta, and rare earth elements. The rare earth elements can be any one or more of lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu), yttrium (Y), and scandium (Sc). Specifically, the transistor device located in the pixel region generates photogenerated carriers (i.e., electrons) under continuous backlight illumination. The increase in photogenerated carriers leads to the reliability problem NBTIS. Therefore, the electron-trapping element doped in the active region 4, acting as a positively charged center, can trap the photogenerated carriers in the active region 4, achieving continuous and rapid photogenerated carrier recombination. This ensures that the NBTIS of the transistor can continuously meet the requirements (at least the NBTIS offset can be less than 1V within two hours), avoiding display quality problems such as sand spots caused by the characteristic offset of the transistor in the pixel area under continuous backlight illumination, thereby improving the illumination stability of the transistor and ensuring the reliability of the product.

[0056] In an optional implementation, the indium (In) content in the oxide semiconductor material of the active region 4 can be set to be greater than the content of any other metal element (for example, if the oxide semiconductor material is indium gallium zinc oxide (IGZO), then the In content is greater than the gallium content and also greater than the zinc content). Since In can provide an electron transport path, In-rich oxide semiconductor materials have higher carrier mobility than traditional oxide semiconductor materials. Therefore, using In-rich oxide semiconductor materials to fabricate the active region 4 can effectively improve the mobility of transistor devices, thereby ensuring reliability and improving product performance.

[0057] In an optional embodiment, after forming the active region 4 on the gate insulating layer 3 in step S102, a metal layer can be formed on the active region 4, and then an annealing process can be performed (the metal layer thickness can be 1000-3000 angstroms, and the annealing temperature can be 300-400°C to better promote the ordering of the active region 4). After reducing the defects of the active region 4 by using the metal layer as an inducing layer through the annealing process, the metal layer is removed (the metal layer can be removed by a dry etching process to avoid damage to the active region 4). The metal layer can be a metal material with strong electronegativity such as Al, Zn, or Ta, so as to more strongly abstract oxygen in the active region 4 and cause ordering to occur inside the active region 4. The specific sequencing process involves attracting defects at the bottom and interior of active region 4 to a position of 100–150 angstroms on the surface. This increases the oxygen vacancy concentration and defect states, transforming the original metal on the surface into a mixed phase of metal and metal oxide with higher defect state density. Meanwhile, the atomic arrangement at the bottom and interior of active region 4 becomes more regular, reducing the defect state concentration. Then, the high-defect-state layer on the surface of the sequenced active region 4 is removed by removing the metal layer. Since active region 4 serves as the device channel region, reducing the internal defect state concentration effectively improves the mobility of the active region, thereby increasing the device refresh rate, reducing power consumption, and further enhancing product performance.

[0058] Execute step S103, such as Figure 5 As shown, source and drain electrodes 5 are formed on the active region 4, and an insulating protective layer 6 is formed on the source and drain electrodes 5.

[0059] like Figure 7 As shown, the source / drain electrode 5 can be fabricated by first forming a source / drain material layer, and then using a source / drain mask to pattern the source / drain material layer to form the source / drain electrode 5. The material of the source / drain electrode 5 can be a metal. In optional embodiments, the material of the source / drain electrode 5 can be Mo or Al to reduce the source / drain line resistance. In optional embodiments, the source / drain electrode 5 can also be a multi-layer structure, using composite metal layers to avoid metal diffusion and oxidation of the metal surface. For example, the source / drain electrode 5 can be a three-layer structure, such as Ti / Al / Ti (the top and bottom layers are Ti, and the middle layer is Al).

[0060] It should be noted that for the existing back channel etching type (BCE) structure transistor, the dry etching process for preparing the source and drain 5 will cause damage to the active region 4, and the damage defects of the active region 4 will cause the transistor device to have large current or serious negative bias after light and other reliability problems. However, the wet etching process will have low precision, and the channel length L of the transistor cannot be less than 2.5 μm, which cannot meet the requirements of high resolution and aperture ratio of display products. If the etching stop layer (ESL) structure transistor is used, although the dry etching process can avoid damage to the active region 4, compared with the BCE structure process, the etching mask of the blocking layer is increased, the cost is higher, and in order to ensure the overlap of the active region 4 and the source and drain 5, the size of the active region 4 will also be limited, and the size of the transistor cannot be further reduced.

[0061] However, the preparation method of the array substrate provided by the embodiment of the present application can use a dry etching process to pattern the source and drain material layer to form the source and drain 5. Since the active region 4 is doped with an electron trapping element as a positive center, it can capture the discrete defects and electrons (such as Cl - and the like) generated in the dry etching process, thereby reducing the damage of the dry etching process to the active region 4. Therefore, the dry etching process can be used to prepare the source and drain 5, which can still maintain good light stability and ensure reliability on the one hand, and can also improve the etching precision, which is suitable for preparing smaller size (for example, channel length L less than 2.5 μm) BCE structure transistors, thereby realizing the preparation of short channel transistors on the premise of saving cost and improving product resolution on the premise of ensuring device stability.

[0062] Please refer to Figure 7 , Figure 7 for the comparison of transistor parameters for different process etching to form source and drain. Among them, the column of "IGZO (111) wet etching" is the parameter data of the wet etching single-layer active region ordinary IGZO transistor source and drain, the column of "IGZO (111) dry etching" is the parameter data of the dry etching single-layer active region ordinary IGZO transistor source and drain, the column of "IGZO (111) + IGZO (136) laminated dry etching" is the parameter data of the dry etching laminated active region ordinary IGZO transistor source and drain, and the column of "IGZO (X) dry etching" is the parameter data of the dry etching single-layer active region IGZO transistor source and drain provided by the present application which is doped with an electron trapping element. "Vth / 3σ" is the threshold voltage of the transistor, that is, the error data, "SS / Mob" is the characteristic data of the switching characteristic curve, "EMP" is the switching characteristic curve, and "Stress (2h)" is the offset amount of the switching characteristic curve after 2h of external force such as temperature and pressure (including negative bias temperature instability NBTIS and positive bias high temperature PBTS parameters).

[0063] From Figure 8It can be seen that, compared with the wet etching process, the NBTIS negative bias caused by the dry etching process reaches -15.6, which is obviously more serious. This is because the etching gas BCl3 and Cl2 etches the source and drain 5 while also causing damage to the active region 4, resulting in more discrete defects and electrons (such as Cl-) in the active region 4. While using a stacked active region transistor, the NBTIS is optimized to -9.18, but the effect is not obvious and is still higher than the 4.92 of the wet etching process. This is because the etching rate of the etching liquid for different active region layers is different, causing the stacked interface to be more easily etched by the etching gas during dry etching, resulting in the invasion of discrete defects and electrons from the stacked interface, causing NBTIS negative bias. For the single-layer active region transistor provided by the present application, which is doped with an electron trapping element, even if the source and drain are prepared using a dry etching process, the NBTIS can be controlled to -0.27, the PBTS is 2.82, and the remaining parameters also meet the requirements. That is, for the transistor provided by the present application, which is doped with an electron trapping element in the active region and has a source and drain prepared using a dry etching process, the characteristic data of the switching characteristic curve is within 25 cm 2 Vs, and after 2h of temperature and pressure and other external forces, the Vth shift represented by NBTIS is within 1V, and the PBTS shift is also within 3V, and the reliability is significantly improved.

[0064] In an optional embodiment, during the preparation of the source and drain 5 using a dry etching process, an anisotropic etching device can be used to reduce the time consumed for patterning the source and drain 5. The etching gas can also be adjusted to remove BCl3 from the etching gas, or to set the chlorine-containing gas in the etching gas to only Cl2. Since Cl2 has strong chemical reactivity and weak bombardment ability, it can further reduce the damage of the etching gas to the active region 5 while ensuring the efficiency of dry etching. Optionally, a mixed gas of Cl2 and F2 can be selected as the dry etching gas. On the one hand, Cl2 reduces the damage of the etching gas to the active region 5, and on the other hand, the F atoms in F2 replace the Cl - atoms entering the active region 5, thereby maximizing the reduction of defect content in the active region 5 after dry etching. And the H atoms in the H2 used in the subsequent process of preparing an insulating protective layer will also replace the Cl - atoms entering the active region 5, further reducing the damage of dry etching to the active region 5, thereby ensuring the characteristics of the device while improving its resolution.

[0065] Please refer to Figure 8 , Figure 8The active area of the transistor is prepared by using the existing dry etching process and the dry etching process after adjusting the etching gas. Wherein, (a) is the scanning electron microscope (SEM) image of the active area after dry etching using the existing etching gas, and (b) is the scanning electron microscope (SEM) image of the active area after dry etching using the adjusted etching gas. From Figure 6 It can be seen that the defect layer thickness of the active area 5 before adjusting the etching gas is about 250 angstroms, and the defect layer thickness of the active area 5 after adjusting the etching gas is about 25 angstroms. The defect layer thickness is obviously reduced after adjusting the etching gas. As can be known from the above, removing BCl3 from the etching gas or setting the chlorine-containing gas in the etching gas to only Cl2 obviously reduces the physical and chemical damage caused by the dry etching process of the source and drain region 5 to the active area 4, optimizes the device characteristics, and enables the preparation of smaller size short channel devices.

[0066] As shown in Figure 9 , after the source and drain electrodes 5 are prepared, a first insulating protective layer 6, i.e., a PVX layer, is formed on the source and drain electrodes 5. The preparation process of the first insulating protective layer 6 can be a physical or chemical deposition process, or a sputtering process, which is not limited herein. The first insulating protective layer 6 can be made of insulating materials such as silicon nitride, silicon oxide, hafnium oxide, or silicon oxynitride, for example, SiNx or SiO2, which is not limited herein. Since the first insulating protective layer 6 has insulating properties and is not an organic material, it will not contaminate the thin film transistor layer and is not easily contaminated by organic materials, and can play a role in isolation and protection. In an optional embodiment, the first insulating protective layer 6 can also be provided in a stacked layer, for example, can be a SiO / SiON or SiO / SiN stacked structure, and NH3 can be added when preparing SiN to replace the Cl - in the active area 5 before, further reducing the damage of dry etching to the active area 5.

[0067] The surface of the thin film transistor layer in the array substrate can be provided with the first insulating protective layer 6 directly contacting and covering the remaining areas except the areas provided with the through holes, so as to play a role in comprehensive and effective protection and isolation.

[0068] In an optional embodiment, as shown in Figure 9 , a planar layer 7 can also be formed on the first insulating protective layer 6. The planar layer 7 can be an organic resin or an acrylic passivation layer, etc., which plays a role in planar surface and reduces parasitic capacitance, increases the distance between the pixel electrode and the thin film transistor layer, ensures the stability of the product picture, effectively blocks the influence of external moisture on the device performance in the array substrate, ensures the device characteristics, and ensures the reliability.

[0069] Depending on the type of display panel the array substrate is used in, different structural layers can be formed on the array substrate. For example, when the array substrate is used in OLED, in Figures 10-12 A first electrode layer, an organic light-emitting material layer, and a second electrode layer can be sequentially disposed on the planarization layer 7 shown. When the array substrate is used in an LCD, an electrode layer, a liquid crystal layer, and a color cell substrate layer can also be sequentially disposed on the planarization layer 7. The following details the subsequent fabrication process using the array substrate in an LCD as an example:

[0070] like Figure 13 As shown, a first electrode layer 8, a second insulating protective layer 9, and a second electrode layer 10 can be sequentially formed on the planarization layer 7. The first electrode layer 8 has an opening at the via connecting the second electrode layer 10 to the source / drain electrode 5, and the remaining space is covered as a common electrode to form an electric field with the second electrode layer 10. The second electrode layer 10 leads out the signals from the source / drain electrode 5 for signal input, and the remaining space is arranged in a spaced pattern as pixel electrodes to form an electric field with the first electrode layer 8 to control the liquid crystal deflection. The second insulating protective layer 9 can be made of insulating materials such as silicon nitride, silicon oxide, hafnium oxide, or silicon oxide nitride, for example, SiNx or SiO2, etc., without limitation. Optionally, the second insulating protective layer 9 is made of SiN material, whose density allows the devices on the array substrate to be more resistant to the influence of external moisture or oxygen environments, improving device stability. When fabricating the via connecting the second electrode layer 10 to the source / drain electrode 5, the second insulating protective layer 9, the planarization layer 7, and the first insulating protective layer 6 can be simultaneously opened using a dry etching process.

[0071] like Figure 6 The diagram illustrates a specific example of a product fabricated using the array substrate fabrication method provided in this application. In this diagram, Mask No. represents the layer number, Layer is the layer name, DI is the patterned size at a certain location after exposure, FI is the etched size at that location, Bias is the etching error, OL is the alignment error, Process is the process parameter, Material is the material of the layer, Thickness is the thickness of the layer, and 8mask indicates that there are 8 main layers (Gate, Active region, Gate insulating layer GI, Source / drain SD, First insulating protective layers PVX1-1 and PVX1-2, Planarization layer Resin, First electrode layer ITO1, Second insulating protective layer PVX, and Second electrode layer ITO2). It is evident that the size, error, and parameters of the product fabricated using the array substrate fabrication method provided in this application all meet the process requirements.

[0072] Based on the same inventive concept, embodiments of the present invention also provide an array substrate, such as... Figure 14 As shown, it includes:

[0073] Substrate 1, and a thin-film transistor layer and an insulating protective layer sequentially disposed on substrate 1;

[0074] The thin-film transistor layer includes a gate 2, a gate insulating layer 3, an active region 4, and source / drain electrodes 5;

[0075] The active region 4 is made of oxide semiconductor material and is doped with an electron-trapping element that serves as a positive charge center.

[0076] Since the array substrate described in the embodiments of this invention is a substrate prepared by the array substrate preparation method described in the embodiments of this invention, and its specific implementation has been explained in the process of describing the manufacturing method, those skilled in the art can understand the specific structure and variations of the array substrate based on the array substrate preparation method described in the embodiments of this invention, and therefore will not be repeated here. All substrates prepared by the array substrate preparation method of the embodiments of this invention fall within the scope of protection of this invention.

[0077] Based on the same inventive concept, embodiments of the present invention also provide a display panel, such as... ​ As shown, it includes: an array substrate 1401 provided in the embodiment of the present invention, and a pixel layer 1402 located on the array substrate 1401.

[0078] It should be noted that the display panel provided in this application may be a liquid crystal display panel, an organic light-emitting semiconductor display panel, a light-emitting diode display panel, etc., and there are no restrictions here, nor will they be listed one by one.

[0079] The technical solutions provided in the embodiments of the present invention have at least the following technical effects or advantages:

[0080] The array substrate, display panel, and fabrication method provided in this invention employ oxide semiconductor material in the active region of the transistors and incorporate electron-trapping elements that act as positive charge centers within the active region. This allows for continuous and rapid photogenerated carrier recombination, even when the transistors in the pixel area generate photogenerated carriers (electrons) under continuous backlight illumination, as these carriers can be captured by the electron-trapping elements. This ensures that the transistors' NBTIS (Network Target Indicator Sequence) consistently meets requirements, preventing display quality issues such as pixel defects caused by characteristic shifts in the pixel area transistors under continuous backlight illumination. This improves the transistors' illumination stability and guarantees product reliability.

[0081] Furthermore, the active region's oxide semiconductor material is made of In-rich material. Since In can provide an electron transport path, In-rich oxide semiconductor materials have higher carrier mobility than traditional oxide semiconductor materials, thus effectively improving the mobility of transistor devices, thereby ensuring reliability and improving product performance.

[0082] Further, a metal layer is formed on the active region 4, and then an annealing process is performed to reduce defects of the active region 4 by using the metal layer as an inducing layer, and then the metal layer is removed, so that the internal structure of the active region 4 is ordered, the mobility of the active region is effectively improved, the refresh rate of the device is improved, the power consumption is reduced, and the product performance is further improved.

[0083] Further, by optimizing the dry etching gas, Cl2 with strong chemical reaction ability and weak bombardment ability is used as the main etching gas, so that the physical and chemical damage of the dry etching process of the source and drain regions 5 to the active region 4 is obviously reduced, the device characteristics are optimized, and the preparation of a smaller size short channel device is realized, and the product transmittance is improved.

[0084] In the description provided herein, a large number of specific details are described. However, it can be understood that the embodiments of the present application can be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure the understanding of the present description.

[0085] Similarly, it is to be understood that the features of the present application that are of a conventional nature can be implemented to form a single embodiment, figure, or description of the application. However, this disclosure should not be interpreted as reflecting a desire to claim more than is explicitly reflected in the claims that follow. Rather, the claims reflect the application claimed in its full scope, as reflected in the claims that follow, in which each claim is in itself intended to be a separate embodiment of the application.

[0086] It should be noted that the above-mentioned embodiments illustrate rather than limit the application, and that one skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The application can be implemented by means of both hardware and software, and any combination thereof. In a unit claim, several elements can be presented with a comma between them. These are considered to be a list of means. The word "first", "second", "third", etc. do not denote any order. These words are to be interpreted as names.

Claims

1. A method for fabricating an array substrate, characterized in that, include: A gate and a gate insulating layer are sequentially formed on a substrate; An active region is formed on the gate insulating layer. The active region is made of oxide semiconductor material. The active region is doped with an electron-trapping element that serves as a positive charge center. The doping ratio of the electron-trapping element in the active region is less than 20%. The active region is the device channel region. A metal layer is formed on the active region and an annealing process is performed. During the annealing process, defects at the bottom and inside of the active region are attracted to the surface, which increases the oxygen vacancy concentration and defect states on the surface to form a defect state layer, and reduces the defect state concentration at the bottom and inside of the active region. The defect state layer on the surface of the active region is removed by removing the metal layer; Source and drain electrodes are formed on the active region, and an insulating protective layer is formed on the source and drain electrodes.

2. The method for fabricating an array substrate as described in claim 1, characterized in that, The electron trapping element includes any one or more of the following combinations: W, Ta, and rare earth elements.

3. The method for fabricating an array substrate as described in claim 1, characterized in that, The content of In in the oxide semiconductor material is greater than the content of any other metal element.

4. The method for fabricating an array substrate as described in claim 1, characterized in that, The metal layer is made of Al, Zn or Ta.

5. The method for fabricating an array substrate as described in claim 1, characterized in that, The step of forming a metal layer on the active region and performing an annealing process includes: A metal layer with a thickness of 1000~3000 angstroms is formed on the active region, and an annealing process is performed at a temperature of 300~400°C.

6. The method for fabricating an array substrate as described in claim 1, characterized in that, The formation of source and drain electrodes on the active region includes: A source / drain material layer is formed on the active region; The source and drain material layers are patterned using a dry etching process to form the source and drain electrodes.

7. The method for fabricating an array substrate as described in claim 6, characterized in that, The process of patterning the source / drain material layer using a dry etching process includes: Using an anisotropic etching apparatus and a dry etching process, the source / drain material layer is patterned with an etching gas, wherein the etching gas containing chlorine is only Cl2.

8. An array substrate, characterized in that, include: A substrate, and a thin-film transistor layer and an insulating protective layer sequentially disposed on the substrate; The thin-film transistor layer includes a gate, a gate insulating layer, an active region, and source / drain electrodes; The active region is made of oxide semiconductor material, and the active region is doped with an electron-trapping element that serves as a positive charge center. The doping ratio of the electron-trapping element in the active region is less than 20%. The active region is the device channel region, and the interior and bottom of the active region are ordered.

9. A display panel, characterized in that, It includes the array substrate as described in claim 8, and a pixel layer located on the array substrate.

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