A programmable high-stability laser pulse control system based on FPGA

Abstract

The present invention belongs to the field of laser system control technology, and relates to a programmable high-stability laser pulse control system based on FPGA. The system includes a laser light source, a pulse shape control circuit, and a control unit; the pulse shape control circuit is composed of a power supply, a comparator, an FPGA chip, and an addition output unit; the laser pulse generated by the laser light source is converted into an electrical signal by a photodetector and then input to the inverting input terminal of the comparator, and the pulse signal is compared with the discrimination level of the in-phase input terminal of the comparator to obtain a signal output to the FPGA chip for processing, and the signal output after FPGA processing is four pairs of differential outputs; the four pairs of differential outputs are subjected to T-type attenuation of different multiples, and the attenuated signals are differentially summed by the addition output unit to obtain an output with a common mode voltage. The present invention adopts a programmable FPGA chip in conjunction with a peripheral circuit, which can not only realize high-quality and high-stability modulated pulse laser output, but also significantly improve the device integration.

Description

Technical Field

[0001] The invention belongs to the technical field of laser system control, and in particular relates to a programmable high-stability laser pulse control system based on FPGA. Background Art

[0002] Pulse laser is a short-duration, high-energy laser pulse. Its unique characteristics make it play an important role in many application fields. In the field of material processing, pulse laser has unique advantages in micro-machining and precision machining of materials, and provides high-precision and high-efficiency processing solutions for the manufacture of advanced precision instruments and equipment. In the field of scientific research, pulse laser is widely used in high-energy physics research, ultrafast dynamics research, spectral analysis and molecular manipulation. In addition, pulse laser is also widely used in biomedicine, military weapons and other fields, and has greatly promoted the progress and development of related fields.

[0003] In the application of pulsed lasers, good time domain characteristics and stability of laser pulses are important indicators for measuring laser performance. Taking material processing as an example, the pulse shape and pulse sequence stability of the laser greatly affect the processing quality and efficiency of the material. Especially for high-precision ultrashort pulse laser processing, the quality of the pulsed laser is particularly important.

[0004] For pulse laser amplifier systems, there are many factors that affect the pulse quality, mainly including the output characteristics of the oscillator, the gain characteristics of the amplifier, and the performance of the pulse control system. In practical applications, the seed light pulses output by the oscillator are usually better, while the performance of the amplifier and the pulse control system is the key to affecting the quality of the final output laser pulse. Among them, for laser amplifiers, when laser pulses are amplified by laser gain media, the time delay between the front and rear edges of the pulses and the energy-related differences in pulse gain characteristics will cause asymmetry or even distortion in the shape of the amplified pulses. To address this phenomenon, the currently commonly used technical solution is to use a pulse control system to pre-modulate the pulse shape in order to achieve pre-compensation of the amplified pulse distortion. The principle is to compensate for the non-uniform gain of the pulse in the laser gain medium by modulating the amplitude of the front and rear edges of the pulse. In specific applications, this is achieved by combining an arbitrary signal generator with an acousto-optic modulator.

[0005] However, this pulse control mechanism has a significant shortcoming. Specifically, the driving signal of the acousto-optic modulator and the gate signal of the signal generator are independent of each other. After mixing, the two are used to drive the acousto-optic modulator to realize the modulation of the laser pulse. The key problem is that there is no fixed phase relationship between the laser pulse signal to be modulated, the driving signal of the acousto-optic modulator, and the gate signal of the signal generator. Although the signals are synchronized in time, there is always a certain phase jitter, which leads to the instability of the modulated pulse and the low pulse modulation accuracy. For the pulse selector based on the same principle, the modulated pulse sequence shows uneven amplitude. This will greatly affect the application of pulse lasers in actual industrial processing and other fields. Summary of the invention

[0006] In view of the shortcomings of the prior art, the present invention provides a programmable high-stability laser pulse control system based on FPGA. The biggest feature of this system is that the driving frequency signal of the acousto-optic modulator and the gate signal of the arbitrary waveform generator are integrated, that is, the two are generated by the same circuit, thereby eliminating the phase jitter between the two and achieving a stable pulse modulation driving signal output. The system can achieve both higher-precision laser pulse shape modulation and highly stable and high-quality modulated laser pulse sequence output.

[0007] The technical solution adopted by the present invention to solve its technical problems is to provide a programmable high-stability laser pulse control system based on FPGA, including a laser light source, a pulse shape control circuit, and a control unit; the pulse shape control circuit is composed of a power supply, a comparator, an FPGA chip and an addition output unit; the laser pulse generated by the laser light source is converted into an electrical signal by a photoelectric detector and then input into the inverting input end of the comparator, the pulse signal is compared with the identification level of the same-phase input end of the comparator to obtain a signal output to the FPGA chip for processing, and the signal output after the FPGA chip processing is four pairs of differential outputs; the four pairs of differential outputs are subjected to T-type attenuation of different multiples, and the attenuated signals are differentially summed by the addition output unit to obtain an output with a common-mode voltage; the control unit is connected to the pulse shape control circuit, the FPGA chip, and the comparator, and respectively controls the output of the pulse shape control circuit, the frequency division number, the pulse width, and the width of the rising edge and the falling edge of the output signal; controls the FPGA chip to process the signal and output the processed signal; and controls the level of the comparator identification.

[0008] Preferably, the FPGA chip processes the input signal including: the GTP built into the FPGA chip converts the input signal into a 40-bit signal, first finds the position where the rising edge of the 40-bit signal appears and records it, and reproduces the signal according to the set pulse width and the position of the rising edge. When the signal is reproduced, four signals are generated, and when the rising edge is detected, waveform data is generated according to the pre-stored lookup table.

[0009] Preferably, the pre-stored lookup table includes rising edge data and falling edge data; the generation of waveform data is divided into rising edge data generation and falling edge data generation. The FPGA chip determines the corresponding lookup table according to the rising edge width and the falling edge width, generates rising edge data and falling edge data; the generated rising edge data and falling edge data are aligned and ANDed to obtain complete waveform data.

[0010] Preferably, the process of generating rising edge data includes three states: state 0 is to detect whether the rising edge signal exists, and if it exists, the rising edge data is generated according to the rising edge lookup table; state 1 is the state of continuing to generate rising edge data; state 3 is to generate pulse data according to the set pulse width after the rising edge data generation is completed. If the rising edge width to be generated is less than 40 bits, and the pulse width is also less than 40 bits, then only state 0 is entered; if the rising edge width is less than 40 bits and the pulse width is greater than 40 bits, then state 0 is entered first, and then state 3 is entered; if the rising edge width is greater than 40 bits and less than 80 bits, and the pulse width is greater than 40 bits, then state 0 is entered first, and then state 1 is entered; whether to enter state 3 is determined based on whether the pulse width is greater than 80 bits. If the rising edge width is greater than 80 bits, then state 0 is entered first, then state 1 is cycled, and state 3 is entered.

[0011] During the generation of rising edge data, an enable signal is set to start generating falling edge data: in the current state, when the pulse width minus the falling edge width is less than 40 bits and greater than 0, falling edge data starts to be generated at the corresponding position, and the enable signal is high.

[0012] The process of generating falling edge data is divided into two states: State 0 determines whether there is an enable signal for starting the generation of falling edge. If so, it starts to generate falling edge data according to the falling edge lookup table. State 1 continues to generate falling edge data. If the falling edge width is less than 40 bits, it only enters state 0; if the falling edge width is greater than 40 bits, it first enters state 0 and then enters state 1.

[0013] Preferably, the pre-stored lookup table is a sinusoidal signal of a fixed frequency: when a rising edge occurs, a sinusoidal signal of a fixed frequency is generated according to the lookup table until the required pulse width is reached, and the waveform data generation ends.

[0014] Preferably, the generated waveform data is subjected to a delay operation, and the delayed data is first divided into two parts: a quotient and a remainder divisible by 40. The quotient divisible by 40 is an integer multiple of 40 that needs to be delayed, and Black Memory is used for delay; the remainder is processed by data shifting, and the processed data is converted into a serial signal output through the TX of GTP.

[0015] Preferably, the FPGA chip is connected to a DAC chip, and the FPGA chip converts the received identification level control signal into an input signal of the DAC chip. The input signal is converted into an analog level output by the DAC chip as the identification level of the comparator.

[0016] Preferably, the output signal of the addition output unit is amplified and output by a high-speed operational amplifier; the output signal amplitude is controlled by changing the adjustable power supply voltage of the inverting input terminal of the high-speed operational amplifier and the resistance between the inverting input terminal and the output terminal of the high-speed operational amplifier.

[0017] The programmable high-stability laser pulse control system based on FPGA provided by the present invention adopts programmable FPGA chip in conjunction with peripheral circuits, which reduces production cost and improves integration. Compared with the signal generator for frequency division and pulse modulation, the implementation method of the present invention is simple, the requirements for optical pulses are also lower, and the waveform accuracy generated is higher. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 Schematic diagram of the structure principle of a programmable high-stability laser pulse control system based on FPGA in an embodiment of the present invention;

[0019] Figure 2 is a flow chart of a pulse shape control circuit in Embodiment 1 of the present invention;

[0020] Figure 3 This is the process of generating rising edge data in Embodiment 1 of the present invention;

[0021] Figure 4 This is the process of generating falling edge data in Embodiment 1 of the present invention;

[0022] Figure 5 is a flow chart of a pulse shape control circuit in Embodiment 2 of the present invention;

[0023] Figure 6 Schematic diagram of the effect of laser pulse after adjustment by the programmable high-stability laser pulse control system based on FPGA of the present invention; (a) is the system of Example 1 after adjustment, generating a waveform with arbitrary rising edge and falling edge time; (b) is the system of Example 2 after adjustment, generating a sine wave with a constant frequency, which drives the acousto-optic modulator after amplification. DETAILED DESCRIPTION

[0024] In order to facilitate the understanding of the present invention, the present invention is described in more detail below in conjunction with the accompanying drawings and specific embodiments. However, the present invention can be implemented in many different forms and is not limited to the embodiments described in this specification. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure of the present invention more thorough and comprehensive.

[0025] Embodiment 1 A programmable high-stability laser pulse control system based on FPGA, such as Figure 1 As shown, it includes a laser light source, a pulse shape control circuit, and a control unit. The laser light source adopts an NPE mode-locked laser, which outputs a laser frequency of 64MHz and a pulse width of 2ps. The pulse shape control circuit consists of a power supply, a high-speed comparator (ADCMP572), an FPGA chip, and a fully differential operational amplifier (LMH5401). The laser pulse generated by the NPE mode-locked laser is converted into an electrical signal by a photodetector and input to the inverting input terminal of the high-speed comparator. The output signal obtained by comparing the pulse signal with the discrimination level of the in-phase input terminal is sent to the FPGA chip for processing.

[0026] In this embodiment, a G-bit transceiver (GTP) built into the FPGA chip is used, such as the GTP transceiver of the Xilinx 7 series FPGA chip, which has a maximum rate of 6.25 Gb / s, and has four pairs of RX differential inputs and four pairs of TX differential outputs. The transmission rate is selected to be 6.25 Gb / s, and the RX of the GTP receives the signal and performs serial-to-parallel conversion, converting the signal into a 40-bit signal output, with a signal accuracy of 160ps and a clock signal of 156.25MHz. This clock signal is used for program operation.

[0027] The signal received by GTP is a group of 40 bits, and then the 40-bit signal is processed. The specific processing flow is as follows: Figure 2 As shown, first find the rising edge and sum the number of times the rising edge occurs. If the sum is greater than or equal to the frequency division number, the rising edge position is output and the total number of rising edges is reset to zero. Otherwise, continue to find the rising edge and sum. When the rising edge position is output, waveform data is generated. The waveform data generation process is divided into rising edge data generation and falling edge data generation.

[0028] The rising edge data generation uses a state machine, which is divided into three states. Figure 3As shown, state 0 detects whether the rising edge signal exists. If it exists, it starts to generate rising edge data according to the rising edge lookup table; state 1 is the state of continuing to generate rising edge data; state 3 is the state of generating pulse data according to the set pulse width after the rising edge data generation is completed. If the rising edge width to be generated is less than 40 bits and the pulse width is also less than 40 bits, only state 0 is entered; if the rising edge width is less than 40 bits and the pulse width is greater than 40 bits, state 0 is entered first, and then state 3 is entered; if the rising edge width is greater than 40 bits and less than 80 bits, and the pulse width is greater than 40 bits, state 0 is entered first, and then state 1 is entered, and whether to enter state 3 is determined based on whether the pulse width is greater than 80 bits; if the rising edge width is greater than 80 bits, state 0 is entered first, and then state 1 is cycled to enter state 3.

[0029] Because the pulse width includes the rising edge width and the falling edge width, an enable signal for the falling edge data to start generating is set during the generation of the rising edge data: in the current state, when the pulse width minus the falling edge width is less than 40 bits and greater than 0, the falling edge data starts to be generated at the corresponding position, and the enable signal is high. After this process, the rising edge data, pulse data, and the enable signal for the falling edge to start generating are obtained.

[0030] Falling edge data generation also uses a state machine and is divided into two states. Figure 4 As shown, state 0 determines whether there is an enable signal generated by the falling edge. If so, it starts to generate falling edge data according to the falling edge lookup table; state 1 continues to generate falling edge data. If the falling edge width is less than 40 bits, it only enters state 0; if the falling edge width is greater than 40 bits, it first enters state 0 and then enters state 1.

[0031] The generated rising edge data and falling edge data are aligned and ANDed to obtain complete waveform data. Finally, the generated waveform data is delayed. First, the delayed data is divided into two parts, the quotient and remainder parts that are divisible by 40. The quotient that is divisible by 40 is an integer multiple of 40 that needs to be delayed. Block Memory is used for delay, and the remainder part is processed by data shifting. The processed data is finally converted into a serial signal output through the TX of GTP.

[0032] After the four-way serial signal is output, it undergoes T-type attenuation, with the attenuation multiples being eight times, four times, two times, and one time respectively. The fully differential operational amplifier (LMH5401) weights and sums the four-way signal to obtain the desired signal shape. The summed signal is amplified by the high-speed operational amplifier (THS3201) according to the requirements and finally output. The inverting input of the high-speed operational amplifier is connected to the power supply voltage and cooperates with the resistor voltage divider to control the amplitude of the output signal. A resistor is connected between the inverting input and the output to cooperate with the resistor of the non-inverting input to control the amplitude of the output signal. The resistor is connected to the ground at the non-inverting input to control the amplitude of the output signal of the fully differential operational amplifier when necessary.

[0033] The whole system works under the control of the control unit. The control unit is connected to the pulse shape control circuit. The control unit controls the output of the pulse shape control circuit, and controls the frequency division number, pulse width, rising edge and falling edge width of the output signal. The FPGA chip determines the address of the lookup table according to the rising edge width and falling edge width. When the FPGA chip receives various control signals, it processes the input signal according to the control signal. When the FPGA chip receives the output start signal, it controls the output of the processed signal. The control unit also controls the high and low level of the high-speed comparator identification level. The FPGA chip is connected to the DAC chip. The FPGA chip converts the received identification level control signal into the input signal of the DAC chip, and the DAC chip converts it into an analog level output as the identification level of the high-speed comparator. According to the change of the control signal, the input laser pulse signal can be realized with any number of frequency divisions, any pulse width, and any rising edge and falling edge width.

[0034] Example 2 The programmable high-stability laser pulse control system based on FPGA provided in this example is substantially the same as that in the example, except that this example is used to generate the driving signal of the AOM. When the FPGA chip processes the input signal, the lookup table is a sinusoidal signal with a fixed frequency. The processing flow is as follows: Figure 5 As shown in the figure, when the rising edge is detected, a fixed frequency sine signal starts to be generated until the required pulse width is reached and the generation ends. The generated waveform signal is connected to an external power amplifier and amplified to the power required by the acousto-optic modulator to drive the acousto-optic modulator. In this way, when each rising edge arrives, the generated sine signal has a stable phase and is synchronized with the modulation signal, which drives the diffraction efficiency of the AOM to be higher and the diffraction signal to be more stable.

[0035] The waveform adjusted by the programmable high-stability laser pulse control system based on FPGA provided by the present invention is as follows: Figure 6 As shown. Among them, Figure 6(a) is a waveform with arbitrary rising and falling edge times after the system of Example 1 is adjusted; (b) is a sine wave with a constant frequency after the system of Example 2 is adjusted, which drives the acousto-optic modulator after amplification. The system provided by the present invention uses a programmable FPGA chip in conjunction with a peripheral circuit, and can achieve arbitrary frequency division, arbitrary pulse width, arbitrary rising and falling edge width, and pulse delay for the input laser pulse signal according to the change of the control signal.

Claims

1. A modulation pulse shape control system based on FPGA, characterized in that: It includes a laser light source, a pulse shape control circuit, and a control unit; the pulse shape control circuit is composed of a power supply, a comparator, an FPGA chip, and an addition output unit; the laser pulse generated by the laser light source is converted into an electrical signal by a photodetector and then input into the inverting input end of the comparator, the pulse signal is compared with the discrimination level of the in-phase input end of the comparator to obtain a signal output to the FPGA chip for processing, and the signal output after the FPGA chip processes is four pairs of differential outputs; The four pairs of differential outputs are subjected to T-type attenuation of different multiples, and the attenuated signals are differentially summed through the addition output unit to obtain an output with a common-mode voltage; the control unit is connected to the pulse shape control circuit, the FPGA chip, and the comparator to respectively control the output of the pulse shape control circuit, the frequency division number, the pulse width, and the width of the rising and falling edges of the output signal; control the FPGA chip to process the signal and output the processed signal; and control the comparator to identify the level; The FPGA chip processes the input signal, including: the GTP built into the FPGA chip converts the input signal into a 40-bit signal, first finds the position of the rising edge of the 40-bit signal and records it, and reproduces the signal according to the set pulse width and the position of the rising edge: first finds the rising edge and sums the number of times the rising edge appears, if the sum is greater than or equal to the frequency division number, then outputs the rising edge position and resets the total number of rising edges to zero, otherwise continues to find the rising edge and sums; when reproducing the signal, four signals are generated, and when the rising edge is detected, waveform data is generated according to the pre-stored lookup table; The pre-stored lookup table includes rising edge data and falling edge data; the generation of waveform data is divided into rising edge data generation and falling edge data generation; the FPGA chip determines the corresponding lookup table according to the rising edge width and the falling edge width, and generates rising edge data and falling edge data; the generated rising edge data and falling edge data are aligned and ANDed to obtain complete waveform data.

2. The FPGA-based modulation pulse shape control system according to claim 1, characterized in that: The process of generating rising edge data includes three states: state 0 is to detect whether the rising edge signal exists, and if it exists, it starts to generate rising edge data according to the rising edge lookup table; state 1 is the state of continuing to generate rising edge data; state 3 is to generate pulse data according to the set pulse width after the rising edge data generation is completed; if the rising edge width to be generated is less than 40 bits, and the pulse width is also less than 40 bits, then only enter state 0; if the rising edge width is less than 40 bits and the pulse width is greater than 40 bits, then enter state 0 first, and then enter state 3; if the rising edge width is greater than 40 bits and less than 80 bits, and the pulse width is greater than 40 bits, then enter state 0 first, and then enter state 1; determine whether to enter state 3 based on whether the pulse width is greater than 80 bits; if the rising edge width is greater than 80 bits, then enter state 0 first, then cycle in state 1, and enter state 3; During the generation of rising edge data, an enable signal is set to start generating falling edge data: in the current state, when the pulse width minus the falling edge width is less than 40 bits and greater than 0, falling edge data starts to be generated at the corresponding position, and the enable signal is high.

3. The FPGA-based modulation pulse shape control system according to claim 2, characterized in that: The generation process of falling edge data is divided into two states: State 0 determines whether there is an enable signal for starting the generation of falling edge. If so, it starts to generate falling edge data according to the falling edge lookup table; State 1 continues to generate falling edge data; if the falling edge width is less than 40 bits, it only enters state 0; if the falling edge width is greater than 40 bits, it first enters state 0 and then enters state 1.

4. The FPGA-based modulation pulse shape control system according to claim 2, characterized in that: The pre-stored lookup table is a fixed-frequency sine signal; when a rising edge appears, a fixed-frequency sine signal is generated according to the lookup table until the required pulse width is reached, and the waveform data generation is completed.

5. The FPGA-based modulation pulse shape control system according to claim 2 or 4, characterized in that: The generated waveform data is delayed. First, the delayed data is divided into two parts: the quotient divisible by 40 and the remainder. The quotient divisible by 40 is an integer multiple of 40 that needs to be delayed. Block Memory is used for delay. The remainder is processed by data shifting. The processed data is then converted into a serial signal output via the GTP TX.

6. The FPGA-based modulation pulse shape control system according to claim 1, characterized in that: The FPGA chip is connected to the DAC chip. The FPGA chip converts the received identification level control signal into an input signal of the DAC chip. The input signal is converted into an analog level output by the DAC chip as the identification level of the comparator.

7. The FPGA-based modulation pulse shape control system according to claim 1, characterized in that: The output signal of the addition output unit is amplified and output by a high-speed operational amplifier; the output signal amplitude is controlled by changing the adjustable power supply voltage of the inverting input terminal of the high-speed operational amplifier and the resistance between the inverting input terminal and the output terminal of the high-speed operational amplifier.

8. The FPGA-based modulation pulse shape control system according to any one of claims 1 to 7, characterized in that: The laser light source adopts NPE mode-locked laser, which has an output laser frequency of 64MHz and a pulse width of 2ps.

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