Fast-locking broadband sub-sampling phase-locked loop based on TDC digital module
By using the TDC digital module in the subsampled phase-locked loop to detect frequency differences and control the bias current, the problem of uneven switching between the frequency lock loop and the phase-locked loop is solved, and a phase-locked loop with low phase noise and fast lock is realized , reduces power consumption.
Patent Information
- Application Number
- CN202311592203.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2023-11-27
- Publication Date
- 2024-12-31
- Estimated Expiration
- 2043-11-27
AI Technical Summary
In the locking process, traditional subsampled phase-locking loops have problems such as inconsistent switching between frequency locking loops and phase-locking loops, which leads to the inability to take into account the performance of low phase noise and fast locking.
Using a fast locked wideband subsampled phase-locking loop based on TDC digital module, removes the frequency locking loop, detects the difference between the output signal frequency and the target frequency through the TDC digital module, and directly controls the frequency band selection and phase-locking loop of the oscillator. Bias current switches extend the frequency capture range and accelerate the locking process.
A phase-locking loop with low phase noise and fast locking is realized, avoiding the problem of locking point misalignment introduced by the locking frequency loop and phase-locking loop switching, and reducing power consumption.
Smart Images
Figure CN117674831B_ABST
Abstract
Description
Technical Field
[0001] The invention relates to the field of digital-analog hybrid integrated circuits, and in particular to a fast-locking broadband sub-sampling phase-locked loop based on a TDC (Time-to-Digital Converter) digital module. Background Art
[0002] Phase-locked loop is one of the basic modules in integrated circuits and is widely used in receivers and transmitters for wireless transmission, frequency synthesizers in wired communications, clock data recovery circuits, etc. Figure 1 As shown in the figure, the circuit consists of five modules: phase detector, charge pump, loop filter, oscillator and frequency divider. The phase-locked loop detects the frequency and phase difference between the reference clock and the feedback clock (frequency divider output) through the phase detector, generates a pulse signal, and thus controls the output current of the charge pump. The output current charges and discharges the capacitor of the loop filter, converts the current into a control voltage, and controls the oscillation frequency of the oscillator. The frequency divider then divides the output high-frequency signal of the oscillator and feeds it back to the phase detector to form a negative feedback network. The loop eventually reaches a stable state through repeated adjustments. Figure 2 The phase-locked loop characteristic diagram of this type of charge pump phase-locked loop shows that the phase-locked loop curve presents a monotonic linear characteristic within each input signal cycle, which indicates that the phase-locked loop has a phase-locked range of [-2π, 2π]. Figure 1 The charge pump phase-locked loop represented by the above figure has amplified noise of the divider, phase detector, and charge pump within the loop bandwidth. 2 times (N: division ratio), which will seriously deteriorate the jitter performance of the phase-locked loop.
[0003] In recent years, sub-sampling phase-locked loop technology has achieved good results in achieving low in-band phase noise. The schematic diagram is shown in Figure 3 As shown, it does not require a frequency divider, essentially eliminating the phase detector and charge pump noise being amplified by N 2 problem. Figure 4 The phase-lock characteristic diagram of the sub-sampling phase-locked loop shows that near the locking point, the phase-lock gain of the sub-sampling phase detector is much greater than that of the traditional charge pump phase-locked loop, which effectively reduces the in-band phase noise. However, due to the periodic characteristics of the sine wave, the phase-lock range of this type of phase-locked loop is only [-π,π]. If only the phase-locked loop works, it is easy to mistakenly lock to any integer multiple of the reference clock, which will cause the phase-locked loop to fail to work properly, which means that it can only guarantee phase lock, but not frequency lock. Therefore, the sub-sampling phase-locked loop usually requires an additional frequency-locked loop (working in a similar way to the traditional charge pump phase-locked loop) to control the output signal frequency to ensure correct frequency and phase lock.
[0004] The traditional sub-sampling phase-locked loop has two loops, the frequency-locked loop and the sub-sampling loop. The frequency-locked loop realizes frequency locking, and the sub-sampling loop realizes phase locking. In order to reduce power consumption, the circuit will turn off the frequency-locked loop after locking. This is achieved through a PFD with a dead zone, but the phase detector PFD and the divider in the frequency-locked loop are not completely turned off, which will consume a certain amount of power, especially the divider in the high-frequency band. In addition, after the initial frequency lock, there is a problem of misalignment of the locking point during the switching process from the frequency-locked loop to the sub-sampling phase-locked loop, which also increases the potential locking time. This makes the current sub-sampling phase-locked loop structure unable to take into account both low phase noise and fast locking performance. Summary of the invention
[0005] In view of the shortcomings of the prior art, the present invention proposes a fast-locking wide-band sub-sampling phase-locked loop based on a TDC digital module. The phase-locked loop removes the frequency-locked loop in the traditional sub-sampling phase-locked loop, detects the difference between the output signal frequency and the target frequency through the TDC digital module, directly controls the frequency band selection of the oscillator and the bias current switch of the phase-locked loop charge pump, and retains the high-gain characteristic of the sub-sampling phase-locked loop during the phase-locking process, thereby expanding the frequency capture range of the sub-sampling phase-locked loop and avoiding the problem of misalignment in switching between the frequency-locked loop and the phase-locked loop, thereby accelerating the locking of the phase-locked loop. At the same time, the TDC digital module can be turned off to reduce its power consumption.
[0006] The specific technical solutions are as follows:
[0007] A fast-locking wideband sub-sampling phase-locked loop based on a TDC digital module, comprising: a sub-sampling phase detector, a comparison selection unit, a charge pump, a loop filter, an oscillator, a differential to four-phase unit, and a TDC digital module;
[0008] The first input terminal of the sub-sampling phase detector inputs a reference signal, and the second input terminal is connected to the output terminal of the differential-to-four-phase unit to receive a uniform four-phase oscillation signal; the sub-sampling phase detector obtains a phase error according to the reference signal and the four-phase oscillation signal and outputs a four-phase phase-detection voltage result;
[0009] The comparison and selection unit comprises a comparator and a multiplexer, wherein the input end of the comparator is connected to the output end of the sub-sampling phase detector, and is used to compare the magnitudes of the two pairs of differential phase-detection voltage results and output the comparison result; the first input end and the second input end of the multiplexer are respectively input with a fixed two-bit value by a register, and the third input end is input with one pair of differential phase-detection voltage results;
[0010] The first input terminal of the charge pump is connected to the output terminal of the multiplexer, and is used to convert the input voltage signal into a current output; the current of the charge pump includes its own current and an additional bias current, and the bias current is controlled to be turned on or off by the TDC digital module;
[0011] The input end of the loop filter is connected to the output end of the charge pump, and the output control voltage controls the voltage controlled oscillator;
[0012] The first input terminal of the voltage-controlled oscillator is connected to the output terminal of the loop filter, and is used to generate and output a differential oscillation signal;
[0013] The input end of the differential-to-four-phase unit is connected to the output end of the voltage-controlled oscillator, and is used to convert the differential oscillation signal into a four-phase oscillation signal output;
[0014] The first input terminal of the TDC digital module inputs a reference signal, and the second input terminal is connected to the output terminal of the voltage-controlled oscillator to obtain a frequency difference between the oscillation signal and the reference signal; the first output terminal is connected to the second input terminal of the voltage-controlled oscillator, and is used to output a digital signal according to the frequency difference to control the frequency band selection of the voltage-controlled oscillator;
[0015] The third input terminal of the TDC digital module is connected to the output terminal of the comparator, and is used to receive the comparison result of the comparator; the second output terminal is connected to the fourth input terminal of the multiplexer, and outputs a digital signal to control the input signal selection of the charge pump according to the comparison result and the frequency difference; the third output terminal is connected to the second input terminal of the charge pump, and outputs a digital signal to control the turning on or off of the charge pump bias current according to the comparison result and the frequency difference.
[0016] Furthermore, the sub-sampling phase detector samples the voltage at the first input terminal using the edge of the four-phase oscillation signal at the second input terminal, or samples the voltage at the second input terminal using the edge of the reference signal at the first input terminal.
[0017] Furthermore, the bias current is turned on in different levels according to the frequency difference between the oscillation signal and the reference signal to adjust the total output current.
[0018] Furthermore, the charge pump adopts a single-ended branch structure, or a double-ended branch structure with a current steering structure.
[0019] Further, the loop filter adopts a single-channel passive filter, the input end of the single-channel passive filter is connected to the output end of the charge pump, and the output end is connected to the first input end of the voltage-controlled oscillator;
[0020] The loop filter can also adopt a dual-path filter, which includes an integral path and a proportional path. The input end of the integral path is connected to the output end of the charge pump, and the output end is connected to the first input end of the voltage-controlled oscillator; the input end of the proportional path is connected to the output end of the sub-sampling phase detector, and the output end is connected to the first input end of the voltage-controlled oscillator; the voltage-controlled oscillator supports dual-path control, and the oscillator gains corresponding to the two paths are different.
[0021] Furthermore, the control signal of the voltage-controlled oscillator is divided into coarse modulation and fine modulation. The coarse modulation is a band selection signal output by a TDC digital module. The band selection signal is a multi-bit digital signal with a large frequency coverage range. The fine modulation comes from the output voltage of the loop filter, which accurately controls the oscillation frequency, and the corresponding frequency coverage range is small. The range of the fine modulation covers at least one coarse modulation frequency band.
[0022] Furthermore, the differential-to-four-phase unit can be replaced. In one case, the voltage-controlled oscillator directly outputs a four-phase oscillation signal to the sub-sampling phase detector; in another case, the output of the voltage-controlled oscillator is divided by a frequency divider to generate a four-phase oscillation signal and transmit it to the sub-sampling phase detector, or the phase shifting unit receives the differential output of the voltage-controlled oscillator, generates a four-phase signal of the same frequency and transmits it to the sub-sampling phase detector.
[0023] Furthermore, the working process of the phase-locked loop is as follows: the TDC digital module receives a reference signal and an oscillation signal, and after roughly estimating the frequency of the oscillation signal and the reference signal, outputs a digital signal to a multiplexer to control the input signal selection of a sub-sampling charge pump, and outputs a digital signal to a voltage-controlled oscillator to control the frequency band selection of the voltage-controlled oscillator; when the frequency ratio of the oscillation signal and the reference signal is inconsistent with the set frequency division ratio, the TDC digital module outputs a digital signal to the sub-sampling charge pump to turn on the bias current; in the phase-locked loop, the sub-sampling phase detector receives a four-phase oscillation signal and a reference signal, samples the four-phase oscillation signal at the rising edge of the reference signal, and the sampling result is passed through a charge pump to obtain a current, and finally the output voltage is passed through a loop filter to control the frequency of the voltage-controlled oscillator.
[0024] Furthermore, the TDC digital module includes a TDC core module and a state machine module. The TDC core module is used to obtain the frequency difference between the oscillation signal and the reference signal, and its structure is a counter structure circuit or a time-to-digital converter circuit; the state machine module receives the comparator output and the frequency difference, and the output signal controls the turning on and off of the additional bias current in the charge pump in the phase-locked loop, as well as the frequency band selection of the voltage-controlled oscillator, and its structure is a digital circuit.
[0025] The beneficial effects of the present invention are:
[0026] The present invention expands the locking range of the sub-sampling phase-locked loop through a TDC digital module and a comparison selection unit, avoids the problem of misalignment of locking points introduced in the switching of the frequency-locked loop and the phase-locked loop, accelerates the locking process, and combines the low phase noise advantage of the low-jitter sub-sampling loop to ultimately achieve a phase-locked loop with low phase noise and fast locking. BRIEF DESCRIPTION OF THE DRAWINGS
[0027] Figure 1 It is a schematic diagram of the architecture of a traditional charge pump phase-locked loop.
[0028] Figure 2 This is the phase-locked loop characteristic diagram of a traditional charge pump.
[0029] Figure 3 This is a schematic diagram of the architecture of a traditional sub-sampling phase-locked loop.
[0030] Figure 4 This is the phase-locked loop characteristic diagram of the traditional sub-sampling phase-locked loop.
[0031] Figure 5 It is a schematic diagram of the architecture of a fast-locked sub-sampling phase-locked loop based on a TDC digital module of the present invention.
[0032] Figure 6 It is a possible embodiment of the fast locked sub-sampling phase-locked loop based on the TDC digital module of the present invention.
[0033] Figure 7 This is another possible embodiment of the fast locked sub-sampling phase-locked loop based on the TDC digital module of the present invention.
[0034] Figure 8 It is a locking timing diagram of a fast-locking sub-sampling phase-locked loop based on a TDC digital module of the present invention.
[0035] Fig. 9 It is a regional division diagram and a charge pump input signal diagram of a fast locked sub-sampling phase-locked loop based on a TDC digital module in the phase-locked stage of the present invention, wherein (a) is a regional division diagram based on a comparison selection unit in the phase-locked stage; (b) is a charge pump input signal diagram in the phase-locked stage.
[0036] Fig.10 It is a schematic diagram of the architecture of the charge pump of the fast-locked sub-sampling phase-locked loop based on the TDC digital module of the present invention and a frequency discrimination and phase discrimination characteristic diagram, wherein (a) is a schematic diagram of the architecture of the charge pump, and (b) is a frequency discrimination and phase discrimination characteristic diagram. DETAILED DESCRIPTION
[0037] The present invention will be described in detail below according to the accompanying drawings and preferred embodiments, and the purpose and effect of the present invention will become more clear. The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.
[0038] Before further describing the embodiments of the present invention in detail, the nouns and terms involved in the embodiments of the present invention are described. The nouns and terms involved in the embodiments of the present invention are subject to the following explanations.
[0039] (1) Voltage-controlled Oscillator (VCO) is a controlled device in a phase-locked loop and is used to provide an oscillation signal with adjustable frequency.
[0040] (2) Reference Signal, hereinafter referred to as REF. In the field of communications, a reference signal usually refers to a signal used to provide a reference phase or frequency, which has stability, accuracy and repeatability. In a phase-locked loop, the reference signal is used to control the phase and frequency of the local oscillator signal, thereby achieving frequency tracking and synchronization.
[0041] (3) Time-to-Digital Converter (TDC) is used to measure the time interval between two signal pulses and convert this interval into digital form. TDC is mainly used to determine the time interval between the start pulse and the stop pulse. When the rising edge or falling edge of the signal pulse exceeds the set threshold, TDC starts measuring and outputs the result.
[0042] like Figure 5 As shown, a fast-locking wide-band sub-sampling phase-locked loop based on a TDC digital module includes: a sub-sampling phase detector, a comparison selection unit, a sub-sampling charge pump, a loop filter, an oscillator, a differential to four-phase unit, and a TDC digital module.
[0043] The sub-sampling phase detector has a reference signal at its first input terminal, and the frequency of the reference signal is F REF The second input terminal is connected to the output terminal of the differential to four-phase unit to receive a uniform four-phase (90° / 180° / 270° / 0°) oscillation signal, which is a sine wave with a frequency of F VCO_4PHASE (90° / 180° / 270° / 0°). The sub-sampling phase detector can use the edge of the four-phase oscillation signal at the second input end to sample the voltage at the first input end, and can also use the edge of the reference signal at the first input end to sample the voltage at the second input end; in this embodiment, the sub-sampling phase detector performs sub-sampling processing on the four-phase oscillation signal according to the reference signal, obtains the phase error and outputs the phase detection voltage result V sam0 、V sam90 、V sam270 、V sam180 .
[0044] The comparison and selection unit includes a comparator and a multiplexer. The input end of the comparator is connected to the output end of the sub-sampling phase detector, which is used to compare the magnitudes of the two pairs of differential phase detection voltage results and output the comparison result, that is, compare V sam0 and V sam180 The size of V sam90 and V sam270The first input terminal and the second input terminal of the multiplexer are respectively input with fixed two-bit values by the register, and the third input terminal is input with one pair of differential phase-discrimination voltage results.
[0045] The sub-sampling charge pump has a first input terminal connected to the output terminal of the multiplexer and is used to convert the input voltage signal into a current output. The current of the sub-sampling charge pump includes its own current I CP and additional bias current ΔI CP , bias current ΔI CP The TDC digital module controls the on or off state, and the bias current ΔI CP It can also be adjusted in different levels according to the frequency difference between the oscillation signal and the reference signal. The sub-sampling charge pump can adopt a single-ended branch structure or a double-ended branch structure with a current steering structure.
[0046] The loop filter has an input connected to the output of the sub-sampling charge pump, and an output control voltage is output to control the voltage-controlled oscillator. The loop filter can be a single-channel passive filter, such as Figure 6 As shown, the input end of the single-path passive filter is connected to the output end of the charge pump, and the output end is connected to the first input end of the voltage-controlled oscillator. The loop filter can also use a dual-path filter (proportional path / integral path), such as Figure 7 As shown, the input end of the integral path of the dual-path filter is connected to the output end of the sub-sampling charge pump, and the output end is connected to the first input end of the voltage-controlled oscillator; the input end of the proportional path is connected to the output end of the sub-sampling phase detector, and the output end is connected to the first input end of the voltage-controlled oscillator, and the output of the sub-sampling phase detector is directly input to the voltage-controlled oscillator for control; the voltage-controlled oscillator supports dual-path control, and the oscillator gains corresponding to the dual paths are different; the advantage of the dual-path control in this embodiment is that the correlation between the resistance and loop bandwidth of the original filter is reduced, and the capacitor area can be greatly reduced.
[0047] The voltage-controlled oscillator has a first input terminal connected to the output terminal of the loop filter, and is used to generate and output a differential sinusoidal oscillation signal, the frequency of the oscillation signal being F VCO The second input terminal is connected to the first output terminal of the TDC digital module. The control signal of the voltage-controlled oscillator is divided into coarse modulation and fine modulation. The coarse modulation is the frequency band selection signal output by the TDC digital module, which is generally a multi-bit digital signal with a large frequency coverage range. The fine modulation comes from the output voltage of the loop filter, which accurately controls the oscillation frequency. The corresponding frequency coverage range is small, and the fine modulation range generally covers at least one coarse modulation frequency band.
[0048] The differential-to-four-phase unit, whose input end is connected to the output end of the voltage-controlled oscillator, is used to convert the differential sinusoidal wave oscillation signal into a four-phase oscillation signal and output it to the sub-sampling phase detector. The differential-to-four-phase unit can be replaced. In one case, the voltage-controlled oscillator directly outputs the four-phase oscillation signal to the sub-sampling phase detector; in another case, the output of the voltage-controlled oscillator is divided by a frequency divider to generate a four-phase oscillation signal and transmit it to the sub-sampling phase detector, or the phase shift unit receives the differential output of the voltage-controlled oscillator, generates a four-phase signal of the same frequency and transmits it to the sub-sampling phase detector.
[0049] The TDC digital module has a first input terminal that inputs a reference signal, and a second input terminal that is connected to the output terminal of a voltage-controlled oscillator, for obtaining a frequency difference between a sinusoidal oscillation signal and a reference signal; a first output terminal that is connected to the second input terminal of the voltage-controlled oscillator, for outputting a digital signal (i.e., a frequency band selection signal) according to the frequency difference to control the frequency band selection of the voltage-controlled oscillator.
[0050] The third input terminal of the TDC digital module is connected to the output terminal of the comparator to receive the comparison result of the comparator; the second output terminal is connected to the fourth input terminal of the multiplexer, and outputs a digital signal to control the input signal selection of the sub-sampling charge pump according to the comparison result and the frequency difference. The third output terminal of the TDC digital module is connected to the second input terminal of the sub-sampling charge pump, and outputs a digital signal to control the opening or closing of the bias current of the sub-sampling charge pump according to the comparison result and the frequency difference.
[0051] The TDC digital module includes a TDC core module and a state machine module. The TDC core module is used to obtain the frequency difference between the oscillation signal and the reference signal. Its structure is a counter structure circuit or a time-to-digital converter circuit. The state machine module receives the comparator output and the frequency difference. The output signal controls the opening and closing of related units such as the sub-sampling charge pump and the voltage-controlled oscillator in the phase-locked loop. Its structure is a digital circuit.
[0052] by Figure 6 Taking a possible implementation example of a fast-locked sub-sampling phase-locked loop based on a TDC digital module, the working process of the phase-locked loop is as follows:
[0053] The TDC digital module receives the reference signal and the oscillation signal, and after roughly estimating the oscillation signal frequency and the reference signal frequency, outputs a digital signal to the multiplexer to control the input signal selection of the sub-sampling charge pump; outputs a digital signal to the voltage-controlled oscillator to control the frequency band selection of the voltage-controlled oscillator; when the frequency ratio of the oscillation signal and the reference signal is inconsistent with the set frequency division ratio, the output digital signal selects one of the first two signals of the multiplexer to input the charge pump, and at the same time turns on the additional sub-sampling charge pump current to inject or extract charge into the loop, that is, turns on the bias current, thereby accelerating the change of the control voltage, preventing false lock, and achieving the function of accelerated locking. In the phase-locked loop, the sub-sampling phase detector receives the four-phase oscillation signal and the reference signal, samples the four-phase oscillation signal at the rising edge of the reference signal, and the sampling result passes through the sub-sampling charge pump to obtain the current, and finally passes through the loop filter to output the voltage to control the frequency of the voltage-controlled oscillator. The following is a detailed introduction to the working principles of the frequency locking stage and the phase locking stage:
[0054] like Figure 8 As shown, assuming the frequency division ratio N = 100, in the frequency locking stage, the TDC digital module is Figure 8 The oscillation signal edge within the reference signal cycle (x=1) is counted (both rising and falling edges are counted), and the absolute value of the difference obtained by subtracting the count result from N*x is judged. When the absolute value is greater than x, it is considered that the frequency is not locked and is in the frequency locking stage; when the absolute value is less than or equal to x, it is considered that the frequency is locked and enters the phase locking stage; when the absolute value remains unchanged for a long time and is very small, it is considered that the loop is locked and the circuit itself is turned off to save power. The TDC digital module will determine the appropriate frequency band control signal through a table lookup, and output it to the VCO so that the oscillation frequency switches to the correct frequency band; output an enable signal and a selection signal to determine whether to turn on the additional bias current in the sub-sampling charge pump in the frequency locking phase-locked loop, and pull the sub-sampling charge pump input to a high level or a low level (the specific voltage depends on the count difference result). Through the above judgment, the TDC digital module reduces the phase difference between the two inputs in the phase locking stage to [-1.5π,1.5π].
[0055] In the phase-locked phase, the VCO frequency band control signal has been confirmed, and the TDC digital module will also turn off the additional bias current of the sub-sampling charge pump in the frequency-locked phase-locked loop. Due to the characteristics of the sine wave, in the last phase-locked phase cycle, the sampled voltage V sam There are two possible phase differences. In order to speed up the locking, the present invention introduces a comparison selection unit. The comparison selection unit receives the result V of the sub-sampling phase detector. sam0 / V sam90 / V sam180 / V sam270 , the final phase-locked period is divided into three regions, such as Fig. 9In region II, V sam90 <V sam270 and This is the desired high gain phase locking region, such as Fig. 9 As shown in (b), in this region, the sampling voltage result V sam0 and V sam180 It will be directly input to the sub-sampling charge pump for phase locking of the loop, and the loop is considered phase locked after it is stable.
[0056] In region I, V sam90 >V sam270 and After the above judgment, the state machine in the TDC digital module outputs a signal to the multiplexer, selecting the sub-sampling charge pump input as 2'b01, that is, the two inputs V sam0 is low level, V sam180 is high, at which point the subsampling charge pump draws current from the loop filter, reducing the control voltage, causing the voltage-controlled oscillator output signal frequency to change slightly, forcing the phase lock to enter region II.
[0057] In region III, V sam90 >V sam270 and After the above judgment, the state machine in the TDC digital module outputs a signal to the multiplexer, selecting the sub-sampling charge pump input as 2'b10, that is, the two inputs V sam0 is high level, V sam180 is low level, at this time the sub-sampling charge pump injects current into the loop filter, increasing the control voltage, causing the output signal frequency of the voltage-controlled oscillator to change slightly, forcing the phase lock to enter region II, speeding up the locking and avoiding false locking.
[0058] After being processed by the comparison selection unit and the TDC digital module, the voltage is input to the sub-sampling charge pump and then to the voltage-controlled oscillator to control the oscillation frequency through the loop filter. The fast-locking wide-band sub-sampling phase-locked loop based on the TDC digital module provided in the embodiment of the present invention combines the good noise characteristics of the traditional sub-sampling phase-locked loop, and adopts the TDC digital module to automatically shut down the entire frequency-locked loop when the sub-sampling phase-locked loop is locked.
[0059] like Fig.10 (a) is a possible embodiment of the sub-sampling charge pump of the present invention. The sub-sampling charge pump has three inputs, two of which are a pair of differential voltage inputs V sam0 and V sam180 The other input is the enable signal EN, which is used to turn on or off the additional bias current circuit. The sub-sampling charge pump output current I OUTThe size of the differential input voltage V sam0 、V sam180 and the sub-sampling charge pump gain G m Decide, where I OUT =G m *(V sam0 -V sam180 ). The sub-sampling charge pump output current source is in addition to the default current I CP =g m* (V sam0 -V sam180 ), and also introduces an additional bias current ΔI CP =Δg m* (V sam0 -V sam180 ), so the total gain of the sub-sampling charge pump is G m =g m +Δg m Where, the gain of the additional bias circuit is Δg m It can be adjusted in different levels according to the frequency difference, thereby changing the output current ΔI of the sub-sampling charge pump. CP The enable signal EN of the bias current circuit is controlled by the TDC digital module. When the frequency ratio of the oscillation signal and the input signal differs greatly from the frequency division ratio, the enable signal EN turns on the bias current, allowing the sub-sampling charge pump to inject or extract more charge into the loop, and at the same time, the input signal V sam0 and V sam180 Pull it up or down to accelerate the change of control voltage into the phase-locked area; when the oscillation signal is close to the input signal frequency and enters the phase-locked area, the enable signal EN is turned off, and the TDC digital module determines the actual sampling area by receiving the output of the comparator, and then inputs the sub-sampling charge pump to V sam0 and V sam180 The loop is forced to enter the final phase-locked region II by pulling it up or down. At this time, the phase difference is reduced to [-0.5π, 0.5π]. The final locking can be achieved only by the subsampling loop. The phase-locked gain curve is shown in Fig.10 as shown in (b).
[0060] The present invention optimizes the traditional sub-sampling phase-locked loop structure, replaces the frequency-locked loop with a TDC digital module, adds a comparison and selection unit, and expands the frequency capture range of the sub-sampling phase detector while ensuring the performance of the sub-sampling phase-locked loop, thereby accelerating the locking process.
[0061] Those skilled in the art can understand that the above are only preferred examples of the invention and are not intended to limit the invention. Although the invention is described in detail with reference to the above examples, those skilled in the art can still modify the technical solutions recorded in the above examples or replace some of the technical features therein with equivalents. Any modification, equivalent replacement, etc. made within the spirit and principle of the invention shall be included in the protection scope of the invention.
Claims
1. A fast-locking broadband sub-sampling phase-locked loop based on a TDC digital module, characterized in that: include: Sub-sampling phase detector, comparison selection unit, charge pump, loop filter, oscillator, differential to four-phase unit, TDC digital module; The first input terminal of the sub-sampling phase detector inputs a reference signal, and the second input terminal is connected to the output terminal of the differential-to-four-phase unit to receive a uniform four-phase oscillation signal; The sub-sampling phase detector obtains a phase error according to a reference signal and a four-phase oscillation signal and outputs a four-phase phase detection voltage result; The comparison and selection unit comprises a comparator and a multiplexer, wherein the input end of the comparator is connected to the output end of the sub-sampling phase detector, and is used to compare the magnitudes of the two pairs of differential phase-detection voltage results and output the comparison result; the first input end and the second input end of the multiplexer are respectively input with a fixed two-bit value by a register, and the third input end is input with one pair of differential phase-detection voltage results; The first input terminal of the charge pump is connected to the output terminal of the multiplexer, and is used to convert the input voltage signal into a current output; the current of the charge pump includes its own current and an additional bias current, and the bias current is controlled to be turned on or off by the TDC digital module; The input end of the loop filter is connected to the output end of the charge pump, and the output control voltage controls the voltage controlled oscillator; The first input terminal of the voltage-controlled oscillator is connected to the output terminal of the loop filter, and is used to generate and output a differential oscillation signal; The input end of the differential-to-four-phase unit is connected to the output end of the voltage-controlled oscillator, and is used to convert the differential oscillation signal into a four-phase oscillation signal output; The first input terminal of the TDC digital module inputs a reference signal, and the second input terminal is connected to the output terminal of the voltage-controlled oscillator to obtain a frequency difference between the oscillation signal and the reference signal; the first output terminal is connected to the second input terminal of the voltage-controlled oscillator, and is used to output a digital signal according to the frequency difference to control the frequency band selection of the voltage-controlled oscillator; The third input terminal of the TDC digital module is connected to the output terminal of the comparator, and is used to receive the comparison result of the comparator; The second output terminal is connected to the fourth input terminal of the multiplexer, and outputs a digital signal to control the input signal selection of the charge pump according to the comparison result and the frequency difference; the third output terminal is connected to the second input terminal of the charge pump, and outputs a digital signal to control the opening or closing of the charge pump bias current according to the comparison result and the frequency difference.
2. The fast locking broadband sub-sampling phase-locked loop based on TDC digital module according to claim 1, characterized in that: The sub-sampling phase detector samples the voltage at the first input terminal using the edge of the four-phase oscillation signal at the second input terminal, or samples the voltage at the second input terminal using the edge of the reference signal at the first input terminal.
3. The fast locking broadband sub-sampling phase-locked loop based on TDC digital module according to claim 1, characterized in that: The bias current is turned on in different levels according to the frequency difference between the oscillation signal and the reference signal to adjust the total output current.
4. The fast locking broadband sub-sampling phase-locked loop based on TDC digital module according to claim 1, characterized in that: The charge pump adopts a single-end branch structure, or a double-end branch structure with a current steering structure.
5. The fast locking broadband sub-sampling phase-locked loop based on TDC digital module according to claim 1, characterized in that: The loop filter adopts a single-channel passive filter, the input end of the single-channel passive filter is connected to the output end of the charge pump, and the output end is connected to the first input end of the voltage-controlled oscillator; The loop filter can also adopt a dual-path filter, which includes an integral path and a proportional path, wherein the input end of the integral path is connected to the output end of the charge pump, and the output end is connected to the first input end of the voltage-controlled oscillator; the input end of the proportional path is connected to the output end of the sub-sampling phase detector, and the output end is connected to the first input end of the voltage-controlled oscillator; The voltage-controlled oscillator supports dual-channel control, and the oscillator gains corresponding to the dual-channels are different.
6. The fast locking broadband sub-sampling phase-locked loop based on TDC digital module according to claim 1, characterized in that: The control signal of the voltage-controlled oscillator is divided into coarse modulation and fine modulation. The coarse modulation is a band selection signal output by the TDC digital module. The band selection signal is a multi-bit digital signal with a large frequency coverage range. The fine modulation comes from the output voltage of the loop filter, which accurately controls the oscillation frequency and has a small corresponding frequency coverage range. The range of the fine modulation covers at least one coarse modulation frequency band.
7. The fast locking broadband sub-sampling phase-locked loop based on TDC digital module according to claim 1, characterized in that: The differential-to-four-phase unit can be replaced. In one case, the voltage-controlled oscillator directly outputs a four-phase oscillation signal to the sub-sampling phase detector; in another case, the output of the voltage-controlled oscillator is divided by a frequency divider to generate a four-phase oscillation signal and transmit it to the sub-sampling phase detector, or the phase shifting unit receives the differential output of the voltage-controlled oscillator, generates a four-phase signal of the same frequency and transmits it to the sub-sampling phase detector.
8. The fast-locking wideband sub-sampling phase-locked loop based on a TDC digital module according to claim 1, characterized in that: The working process of the phase-locked loop is as follows: the TDC digital module receives a reference signal and an oscillation signal, roughly estimates the frequency of the oscillation signal and the reference signal, and then outputs a digital signal to a multiplexer to control the input signal selection of a sub-sampling charge pump, and outputs a digital signal to a voltage-controlled oscillator to control the frequency band selection of the voltage-controlled oscillator; when the frequency ratio of the oscillation signal and the reference signal is inconsistent with the set frequency division ratio, the TDC digital module outputs a digital signal to the sub-sampling charge pump to turn on the bias current; in the phase-locked loop, the sub-sampling phase detector receives a four-phase oscillation signal and a reference signal, samples the four-phase oscillation signal at the rising edge of the reference signal, and the sampling result is passed through a charge pump to obtain a current, and finally the output voltage is passed through a loop filter to control the frequency of the voltage-controlled oscillator.
9. The fast locking broadband sub-sampling phase-locked loop based on TDC digital module according to claim 1, characterized in that: The TDC digital module includes a TDC core module and a state machine module. The TDC core module is used to obtain the frequency difference between the oscillation signal and the reference signal, and its structure is a counter structure circuit or a time-to-digital converter circuit; the state machine module receives the comparator output and the frequency difference, and the output signal controls the opening and closing of the additional bias current in the charge pump in the phase-locked loop, and the frequency band selection of the voltage-controlled oscillator, and its structure is a digital circuit.