LPDDR chip packaging structure and electronic devices

Abstract

The present application proposes a LPDDR chip packaging structure and electronic device, which relates to the field of chip technology. The LPDDR chip packaging structure includes a PCB board and at least one LPDDR wafer. A plurality of electrical balls are electrically connected between the LPDDR wafer and the PCB board. The plurality of electrical balls are connected to the pins of the LPDDR wafer through wiring, wherein at least one strip area is provided on the front of the PCB board, and the strip area is connected to the same edge of the PCB board, wherein the electrical balls are prohibited from being arranged in the strip area, and the electrical balls are arranged in an array in the non-strip area. In this way, the wiring can be extended from a single side of the PCB board, so that it can better cooperate with the SOC control chip and reduce the difficulty of wiring. In addition, by reducing the ball spacing between the electrical balls, the size of a single LPDDR chip can be reduced, so that it is easy to use in small electronic devices.

Description

Technical Field

[0001] The present application relates to the field of chip technology, and in particular to an LPDDR chip packaging structure and an electronic device. Background Art

[0002] LPDDR (Low Power Double Data Rate SDRAM) chip is a communication standard developed by the JEDEC Solid State Technology Association of the United States for low-power memory. It is known for its low power consumption and small size and is specifically used in mobile electronic devices.

[0003] At present, mainstream suppliers generally use 315 balls to package LPDDR chips individually, but the package size of this packaging method is 15mmx12.4mm, which occupies a large area. Therefore, it is mostly used in large electronic devices such as laptops. However, it is not well adapted to small electronic devices such as smartphones and wearable devices. Summary of the invention

[0004] In view of the above technical problems, the present application provides a LPDDR chip packaging structure and an electronic device, so that the LPDDR chip packaging structure can be applied to small electronic devices.

[0005] The present application provides an LPDDR chip packaging structure, including a circuit board and at least one LPDDR wafer; at least one LPDDR wafer is arranged on the back of the circuit board, and an array of electrical balls is arranged on the front of the circuit board for connecting to an external circuit, and the electrical balls are connected to the pins of the LPDDR wafer through wiring; at least one strip area is arranged on the front of the circuit board, and the electrical balls are prohibited from being arranged in the strip area, and the strip area is connected to the same edge of the circuit board.

[0006] Optionally, the LPDDR chip packaging structure includes at least one of the following: the spacing between any adjacent electrical balls in the non-strip region is equal; the width of the strip region is greater than the spacing between any adjacent electrical balls in the non-strip region.

[0007] Optionally, the strip area includes at least one of the following: a main strip area, which is connected to the edge of the circuit board; and at least one sub-strip area, which is arranged within the orthographic projection area of ​​at least one LPDDR wafer on the circuit board, and the extension direction of the sub-strip area is different from that of the main strip area.

[0008] Optionally, the main strip area includes at least one of the following: the main strip area is arranged within the orthographic projection area of ​​the LPDDR wafer on the circuit board; the main strip area at least partially covers the symmetry line of the orthographic projection area.

[0009] Optionally, at least one of the following items is included: the wiring is arranged on the front side of the circuit board; an insulating layer covering the wiring is arranged on the circuit board, an opening is arranged on the insulating layer, and the electrical contact ball extends out of the opening.

[0010] Optionally, the LPDDR chip packaging structure includes a first LPDDR wafer and a second LPDDR wafer that are symmetrically arranged; the electrical contacts and wiring on the circuit board are also arranged symmetrically about the symmetry lines of the two wafers.

[0011] Optionally, at least one of the following items is included: at least one grounding ball for grounding is provided on the circuit board along the symmetry line of the two wafers; at least one strip area is provided on the circuit board to cover the symmetry line of the two wafers.

[0012] Optionally, the width of the strip-shaped region covering the symmetry lines of the two wafers is smaller than the width of other strip-shaped regions.

[0013] The present application also provides an electronic device, comprising the LPDDR chip packaging structure disclosed in the above embodiments.

[0014] Optionally, in the electronic device, the edge on the circuit board connected to the strip area is the target edge; at least one control chip is also arranged on a single side of the LPDDR chip packaging structure, and the control chip is connected to the electrical ball of the LPDDR chip packaging structure through a wiring crossing the target edge.

[0015] In the LPDDR chip packaging structure provided by the present application, a plurality of electrical connection balls are electrically connected between the LPDDR wafer and the PCB board, and the plurality of electrical connection balls are connected to the pins of the LPDDR wafer through wiring, wherein at least one strip area is provided on the front of the PCB board, and the strip area is connected to the same edge of the PCB board, wherein the electrical connection balls are prohibited from being arranged in the strip area, and the electrical connection balls are arranged in an array in the non-strip area. In this way, the wiring can be extended from a single side of the PCB board, so that it can better cooperate with the SOC control chip and reduce the difficulty of wiring. In addition, by reducing the ball spacing between the electrical connection balls, the size of a single LPDDR chip can be reduced, so that it is convenient for application in small electronic devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present application, and are used together with the specification to explain the principles of the present application. In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the description of the embodiments are briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative labor.

[0017] Figure 1A schematic diagram of the LPDDR chip packaging structure provided in an embodiment of the present application;

[0018] Figure 2 A top view of the LPDDR chip packaging structure provided in an embodiment of the present application is shown;

[0019] Figure 3 A schematic diagram of the pin layout of the LPDDR chip packaging structure provided in an embodiment of the present application;

[0020] Figure 4 A schematic diagram of the pin layout of another LPDDR chip packaging structure provided in an embodiment of the present application;

[0021] Figure 5 A schematic diagram of the pin arrangement of a LPDDR chip is shown;

[0022] Figure 6 A schematic diagram showing the connection between the LPDDR chip packaging structure and the control chip provided in an embodiment of the present application is shown;

[0023] Figure 7 A schematic diagram of the system structure of an electronic device provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0024] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0025] It should be noted that, in this article, the terms "include", "comprises" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "includes a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element. In addition, components, features, and elements with the same name in different embodiments of the present application may have the same meaning or different meanings, and their specific meanings need to be determined by their explanation in the specific embodiment or further combined with the context of the specific embodiment.

[0026] LPDDR (Low Power Double Data Rate SDRAM) chip is a type of volatile memory product, characterized by low power consumption and small size, and is mainly used in mobile electronic devices.

[0027] At present, mainstream suppliers generally package LPDDR chips and UFS (Universal Flash Storage) chips in a two-in-one package and then sell them as a whole.

[0028] However, in actual applications, users may only need LPDDR chips instead of UFS chips, but due to the above two-in-one packaging method, users cannot obtain separately packaged LPDDR chips. This not only increases the user's usage cost, but also wastes the resources of UFS chips.

[0029] In addition, the two-in-one packaging structure is relatively large in size and is limited in volume, height and capacity. It can only be used in large electronic devices and cannot be configured in small electronic devices.

[0030] At the same time, users found that if any of the LPDDR chip and the UFS chip is damaged, it must be replaced as a whole, which further increases the cost. When the model of the UFS chip that the user expects to use is inconsistent with the model of the UFS chip in the two-in-one package structure, new problems will arise. For example, the user expects to use the UFS3.1 chip, but the model of the UFS chip in the two-in-one package structure is UFS2.0. Obviously, this fixed combination is not flexible and cannot meet the needs of users.

[0031] In order to solve this problem, the relevant technology has proposed a solution of packaging LPDDR chips separately, that is, a single LPDDR packaged chip + an independent UFS chip. In this way, the model of the UFS chip can be flexibly selected, and it can be used when needed and not used when not needed, which effectively reduces costs.

[0032] Among them, the relevant technology uses 315 balls specified by JEDEC (Solid State Technology Association is the leading standard organization in the microelectronics industry) for single LPDDR chip packaging, where 315 balls can be understood as 315 solder balls or copper balls electrically connected between the LPDDR chip and the substrate. Among them, the 315-ball package size is 15mmx12.4mm, which occupies too much board area, so it is mostly used in large electronic devices such as laptops. However, it cannot be well adapted to small electronic devices such as smartphones and wearable devices.

[0033] Taking smartphones as an example, the design of smartphone motherboards is becoming more and more complex, so the area available for LPDDR chips is constantly compressed. Therefore, the above-mentioned single LPDDR chip packaging structure becomes very unfriendly due to its large size.

[0034] In order to solve the above technical problems, the present application provides an LPDDR chip packaging structure, in which at least one strip area is provided on the front of the PCB board, and the strip area is connected to the same edge of the PCB board, wherein the arrangement of electrical connection balls is prohibited in the strip area, and the electrical connection balls are arranged in an array in the non-strip area, and the multiple electrical connection balls are connected to the pins of the LPDDR wafer through wiring, wherein the ball spacing of the multiple electrical connection balls is 0.5mm×0.6mm, and the wiring extends from the same edge of the PCB to connect to the external circuit, which can better cooperate with the external circuit such as the external control chip, etc., and reduces the difficulty of wiring. And by reducing the ball spacing between the electrical connection balls, the size of a single LPDDR chip can be reduced, so that it is easy to use in small electronic devices.

[0035] The LPDDR chip packaging structure provided in the embodiment of the present application can be applied to large electronic devices or small electronic devices. Among them, the electronic device can be, for example, a terminal device, which can also be called a terminal, a user equipment (UE), a mobile station (MS), a mobile terminal (MT), etc. The electronic device can be a mobile phone, a smart TV, a wearable device, a tablet computer (Pad), a computer with wireless transceiver function, a virtual reality (VR) device, an augmented reality (AR) device, a wireless terminal in industrial control, a wireless terminal in self-driving, a wireless terminal in remote medical surgery, a wireless terminal in smart grid, a wireless terminal in transportation safety, a wireless terminal in smart city, a wireless terminal in smart home, etc. The embodiment of the present application does not limit the specific technology and specific device form adopted by the electronic device.

[0036] The LPDDR chip packaging structure provided in the embodiment of the present application is described below with reference to the accompanying drawings.

[0037] For example, Figure 1A schematic diagram of an LPDDR chip packaging structure provided in an embodiment of the present application, wherein the LPDDR chip packaging structure includes a circuit board 101 and at least one LPDDR wafer 102. The circuit board can be a mainboard of an electronic device, and plays a role in carrying electronic components such as a target memory chip, a processor chip, and a power management chip, and realizing the electrical connection between the target memory chip, the processor chip, and the power management chip. The circuit board can include but is not limited to a printed circuit board (PCB), a flexible printed circuit board (FPC), and a hard-soft circuit board. The following description takes the circuit board as a PCB board as an example.

[0038] In the embodiment of the present application, the thickness of the PCB board can be any size between 1 mm and 3 mm.

[0039] In the embodiment of the present application, the LPDDR chip may be a LPDDR5 chip, and correspondingly, the LPDDR wafer is a LPDDR5 wafer.

[0040] Among them, one LPDDR chip packaging structure may include 1 LPDDR wafer, or 2 LPDDR wafers, or 4 LPDDR wafers. When the number of LPDDR wafers in the present application exceeds 1, they are all arranged in a symmetrical manner.

[0041] In the embodiment of the present application, the front array of the PCB board is arranged with electrical balls 103, which are important components for connecting the internal circuit of the chip with the external circuit. The electrical balls usually refer to solder balls or bumps, such as tin balls or copper balls.

[0042] In the embodiment of the present application, the electrical ball is connected to the pin of the LPDDR wafer through wiring. The LPDDR wafer is provided with multiple pins, each of which has its specific function, such as power supply, grounding, data transmission, control signal, etc. It should be noted that the pin is not directly exposed on the surface of the LPDDR wafer, but is connected to the electrical ball through the internal metal layer. Among them, during the chip packaging process, the pin will be connected to the electrical ball through the internal metal wiring layer. This connection can ensure that the signal on the pin can be correctly transmitted to the electrical ball, and then connected to the external circuit through the package pin (the part of the pin outside the package body).

[0043] The wiring is arranged on the front side of the PCB board, an insulating layer covering the wiring is arranged on the PCB board, an opening is arranged on the insulating layer, and the electrical ball extends out of the opening to be electrically connected with the wiring.

[0044] In the embodiment of the present application, at least one strip area is provided on the front side of the PCB board, the strip area is prohibited from arranging the electrical balls, and the strip area is connected to the same edge of the PCB board.

[0045] For example, Figure 2 and Figure 3 As shown, Figure 2 A top view of the LPDDR chip packaging structure provided in an embodiment of the present application is shown, wherein the LPDDR wafer 201 extends from a single side of a PCB board 202 to be connected to an external circuit. Figure 3 A schematic diagram of the pin layout of the LPDDR chip packaging structure provided in the embodiment of the present application. Figure 3 It can be seen that there are multiple strip areas on the front of the PCB board, among which: Figure 3 Two bar areas are shown as an example. Figure 3 As shown in the middle shaded area, there is no electrical contact ball arranged in the strip area, while the rest of the area outside the strip area is arranged with electrical contact balls in an array.

[0046] At the same time, in the embodiment of the present application, the multiple strip areas are all connected to the same edge of the PCB board. For example, the edge on the PCB board connected to the strip area is the target edge. It can be understood that in the embodiment of the present application, the target edge can be the upper edge of the PCB board, or the target edge can be the lower edge of the PCB board, or the target edge can be the left edge of the PCB board, or the target edge can be the right edge of the PCB board. Figure 3 It can be seen that the multiple strip-shaped areas are all connected to the left edge of the PCB board.

[0047] The wiring in the PCB board extends outward through the strip area, wherein the multiple strip areas are connected to the same edge of the PCB board, that is, the wiring corresponding to the multiple strip areas extends from a single side of the PCB board to connect with the external circuit, such as Figure 2 As shown in FIG. 1 , the LPDDR wafer extends from the left edge of the PCB board through wiring. This can simplify the wiring between the LPDDR chip packaging structure and the external circuit and reduce the wiring difficulty.

[0048] In the embodiment of the present application, the rest of the area outside the strip area is defined as a non-strip area, wherein the electrical ball array is arranged in the non-strip area, and the ball pitch of any adjacent electrical balls is equal. Optionally, in the embodiment of the present application, the ball pitch of any adjacent electrical balls is 0.5mm×0.6mm. By reducing the ball pitch, the size of the LPDDR wafer can be reduced, and then the size of the LPDDR chip packaging structure can be reduced. In the embodiment of the present application, the size of the LPDDR chip packaging structure can be reduced to 8.2mm×12.4mm, so that it is easy to be used in small electronic devices.

[0049] Optionally, in the embodiment of the present application, the width of the strip-shaped area is greater than the ball spacing between any adjacent electrical balls in the non-strip-shaped area.

[0050] In the embodiment of the present application, there are multiple strip areas, wherein each strip area may include a main strip area and a secondary strip area, the main strip area is connected to the edge of the PCB board, the secondary strip area is connected to the main strip area, and the secondary strip area may be connected to the edge of the PCB board or may not be connected to the edge of the PCB board. Optionally, there is one main strip area and multiple secondary strip areas. Optionally, when the secondary strip area is connected to the edge of the PCB board, both the main strip area and the secondary strip area are connected to the same target edge of the PCB board.

[0051] When the LPDDR chip includes one LPDDR wafer, the main stripe area and the sub-stripe area are both arranged within the orthographic projection area of ​​the LPDDR wafer on the PCB board, such as Figure 3 As shown, Figure 3 The main strip area is connected to the edge of the PCB board, and the sub-strip area is connected to the main strip area.

[0052] Optionally, the strip area may include a first strip area and a second strip area, wherein the first strip area includes a main strip area, and the second strip area includes a main strip area and a sub-strip area.

[0053] When the LPDDR chip includes more than two LPDDR wafers, the first strip area is arranged between two adjacent LPDDR wafers, and the second strip area is arranged within the orthographic projection area of ​​the LPDDR wafer on the PCB board.

[0054] Optionally, a LPDDR wafer may include a plurality of second strip-shaped areas within an orthographic projection area on the PCB board.

[0055] Optionally, the first strip area at least partially covers a symmetry line of an orthographic projection area of ​​two adjacent LPDDR wafers on the PCB board.

[0056] Based on the above embodiments, the embodiments of the present application also provide another LPDDR chip packaging structure, which includes a first LPDDR wafer and a second LPDDR wafer that are symmetrically arranged, and the electrical balls and wirings arranged in an array on the PCB board are symmetrically arranged corresponding to the two LPDDR wafers.

[0057] Exemplarily, the first LPDDR wafer constitutes the A channel of the LPDDR chip, and the second LPDDR wafer constitutes the B channel of the LPDDR chip. Alternatively, the first LPDDR wafer constitutes the B channel of the LPDDR chip, and the second LPDDR wafer constitutes the A channel of the LPDDR chip.

[0058] Optionally, in the embodiment of the present application, a plurality of strip regions are provided on the PCB board, wherein at least one strip region covers the symmetry line of the first LPDDR wafer and the second LPDDR wafer, or partially covers the symmetry line of the first LPDDR wafer and the second LPDDR wafer. The strip region is the first strip region mentioned above.

[0059] Optionally, at least one grounding ball is disposed on the PCB along the symmetry line between the first LPDDR wafer and the second LPDDR wafer. Optionally, three grounding balls are disposed on the PCB along the symmetry line between the two wafers.

[0060] Optionally, the width of the strip region covering the symmetry line of the first LPDDR wafer and the second LPDDR wafer is smaller than the width of other strip regions.

[0061] For example, Figure 4 A schematic diagram of the pin layout of another LPDDR chip packaging structure provided in an embodiment of the present application is shown in FIG. Figure 4 As shown, the pins in the LPDDR chip package structure are arranged in an array, wherein each row of pins is marked as row A, row B, row C, row D, row E, row F, row G, row H, row J, row K, row L, row M, row N, row P, row R, row T, row U, row V, row W, row Y, row AA, row AB and row AC from top to bottom, and each column of pins is marked as column 1, column 2, column 3, column 4, column 5, column 6, column 7, column 8, column 9, column 10, column 11, column 12 and column 13 from left to right. In addition, the LPDDR chip package structure includes 245 pins.

[0062] In the embodiment of the present application, compared with the LPDDR chip of the prior art including 315 pins, the number of pins is reduced, and the ball spacing between the electrical balls is shortened, that is, the spacing between the pins is shortened, so that the package size of a single LPDDR chip can be further reduced.

[0063] Figure 4 The LPDDR chip packaging structure shown includes a first LPDDR wafer and a second LPDDR wafer, and the first LPDDR wafer and the second LPDDR wafer are shown in dotted boxes in the figure.

[0064] The front of the PCB board is provided with three strip areas, namely, one first strip area and two second strip areas, the first strip area partially covers the symmetry line of the first LPDDR wafer and the second LPDDR wafer, wherein the uncovered area is provided with three grounding balls. Optionally, the first strip area corresponds to the Mth row and the 1st to the 10th columns on the PCB board.

[0065] The two second strip areas are respectively defined as target strip area 1 and target strip area 2, wherein target strip area 1 includes a main strip area and a sub-strip area, and is arranged in the orthographic projection area of ​​the first LPDDR wafer on the PCB board; target strip area 2 includes a main strip area and a sub-strip area, and is arranged in the orthographic projection area of ​​the second LPDDR wafer on the PCB board.

[0066] Optionally, refer to Figure 5 , Figure 5 A pin arrangement schematic diagram of an LPDDR chip is shown, wherein the main strip area of ​​the target strip area 1 corresponds to the Fth row, 1st column to the 8th column and the Gth row, 1st column to the 8th column on the PCB board, and the sub-strip area of ​​the target strip area 1 corresponds to the Dth row, 8th column, the Eth row, 8th column and the 13th column, the Hth row, 1st column to the 2nd column and the Kth row, 1st column on the PCB board.

[0067] refer to Figure 5 It can be seen that the main strip area of ​​the target strip area 2 corresponds to the Uth row, 1st column to the 8th column and the Vth row, 1st column to the 8th column on the PCB board; the sub-strip area of ​​the target strip area 2 corresponds to the Pth row, 1st column, the Tth row, 1st column to the 2nd column, the Wth row, 8th column and the 13th column, and the Yth row, 8th column on the PCB board.

[0068] Exemplary, reference Figure 5 The pins of the LPDDR chip in the embodiment of the present application are described.

[0069] like Figure 5 As shown, the pins in the first column and row C of the LPDDR chip are the eleventh data input and output terminal of the A channel of the LPDDR chip, the pins in the first column and row E of the LPDDR chip are the fourteenth data input and output terminal of the A channel of the LPDDR chip, the pins in the first column and row W of the LPDDR chip are the sixth data input and output terminal of the B channel of the LPDDR chip, and the pins in the first column and row AA of the LPDDR chip are the third data input and output terminal of the B channel of the LPDDR chip.

[0070] The pins in the second column, row B of the LPDDR chip are the ninth data input and output terminal of the A channel of the LPDDR chip, the pins in the second column, row D of the LPDDR chip are the thirteenth data input and output terminal of the A channel of the LPDDR chip, the pins in the second column, row J of the LPDDR chip are the first data input and output terminal of the A channel of the LPDDR chip, the pins in the second column, row R of the LPDDR chip are the ninth data input and output terminal of the B channel of the LPDDR chip, the pins in the second column, row Y of the LPDDR chip are the fifth data input and output terminal of the B channel of the LPDDR chip, and the pins in the second column, row AB of the LPDDR chip are the first data input and output terminal of the B channel; the pins in the second column, row C and the pins in the K row of the LPDDR chip are the input / output power supply terminals of the A channel of the LPDDR chip, and the pins in the second column, row P and the pins in the AA row of the LPDDR chip are the input / output power supply terminals of the B channel of the LPDDR chip.

[0071] The pins in the third column, row C of the LPDDR chip are the tenth data input and output terminal of channel A of the LPDDR chip, the pins in the third column, row E of the LPDDR chip are the fifteenth data input and output terminal of channel A of the LPDDR chip, the pins in the third column, row H of the LPDDR chip are the seventh data input and output terminal of channel A of the LPDDR chip, the pins in the third column, row T of the LPDDR chip are the fifteenth data input and output terminal of channel B of the LPDDR chip, the pins in the third column, row W of the LPDDR chip are the seventh data input and output terminal of channel B of the LPDDR chip, the pins in the third column, row AA of the LPDDR chip are the second data input and output terminal of channel B of the LPDDR chip, the pins in the third column, row A and the pins in the K row of the LPDDR chip are the input / output power supply terminals of channel A of the LPDDR chip, and the pins in the third column, row P and the pins in the AC row of the LPDDR chip are the input / output power supply terminals of channel B of the LPDDR chip.

[0072] The pins in the fourth column and row B of the LPDDR chip are the sixteenth data input and output terminal of the A channel of the LPDDR chip, the pins in the fourth column and row J of the LPDDR chip are the first input data mask terminal of the A channel of the LPDDR chip, the pins in the fourth column and row L of the LPDDR chip are the second data input and output terminal of the A channel of the LPDDR chip, the pins in the fourth column and row N of the LPDDR chip are the tenth data input and output terminal of the B channel of the LPDDR chip, the pins in the fourth column and row R of the LPDDR chip are the second input data mask terminal of the B channel of the LPDDR chip, and the pins in the fourth column and row AB of the LPDDR chip are the eighth data input and output terminal of the B channel of the LPDDR chip; the pins in the fourth column and row A of the LPDDR chip, the pins in the C row, the pins in the D row and the pins in the E row are the input / output power supply terminals of the A channel of the LPDDR chip, and the pins in the fourth column and row W of the LPDDR chip, the pins in the Y row, the pins in the AA row and the pins in the AC row are the input / output power supply terminals of the B channel of the LPDDR chip.

[0073] The pins in the fifth column, row C of the LPDDR chip are the second input data mask terminal of the A channel of the LPDDR chip, the pins in the fifth column, row E of the LPDDR chip are the second data input and output terminal of the A channel of the LPDDR chip, the pins in the fifth column, row H of the LPDDR chip are the sixth data input and output terminal of the A channel of the LPDDR chip, the pins in the fifth column, row K of the LPDDR chip are the fifth data input and output terminal of the A channel of the LPDDR chip, the pins in the fifth column, row P of the LPDDR chip are the thirteenth data input and output terminal of the B channel of the LPDDR chip, and the pins in the fifth column, row L of the LPDDR chip are the sixth data input and output terminal of the A channel of the LPDDR chip. The pins in the fifth column and the T row of the PDDR chip are the fourteenth data input and output terminal of the B channel of the LPDDR chip, and the pins in the fifth column and the W row of the LPDDR chip are the fourth data input and output terminal of the B channel of the LPDDR chip; the pins in the fifth column and the AA row of the LPDDR chip are the first input data mask terminal of the B channel of the LPDDR chip, the pins in the fifth column and the A row of the LPDDR chip are the input / output power supply terminal of the A channel of the LPDDR chip, and the pins in the fifth column and the AC row of the LPDDR chip are the input / output power supply terminal of the B channel of the LPDDR chip.

[0074] The pins in the sixth column and row B of the LPDDR chip are the second differential read synchronization signal terminal of the A channel of the LPDDR chip, the pins in the sixth column and row D of the LPDDR chip are the second readout clock terminal of the A channel of the LPDDR chip, the pins in the sixth column and row L of the LPDDR chip are the third data input and output terminal of the A channel of the LPDDR chip, and the pins in the sixth column and row N of the LPDDR chip are the eleventh data input and output terminal of the B channel of the LPDDR chip; the pins in the sixth column and row Y of the LPDDR chip are the first readout clock terminal of the B channel of the LPDDR chip, the pins in the sixth column and row AB of the LPDDR chip are the first differential read synchronization signal terminal of the B channel of the LPDDR chip, the pins in the sixth column and row C of the LPDDR chip and the pins in the J row are the input / output power supply terminals of the A channel of the LPDDR chip, and the pins in the sixth column and row R of the LPDDR chip and the pins in the AA row are the input / output power supply terminals of the B channel of the LPDDR chip.

[0075] The pin of the seventh column and row B of the LPDDR chip is the second differential read synchronization signal terminal of the A channel of the LPDDR chip, the pin of the seventh column and row D of the LPDDR chip is the second write clock terminal of the A channel of the LPDDR chip, the pin of the seventh column and row H of the LPDDR chip is the eighth data input and output terminal of the A channel of the LPDDR chip, the pin of the seventh column and row K of the LPDDR chip is the fourth data input and output terminal of the A channel of the LPDDR chip, the pin of the seventh column and row P of the LPDDR chip is the twelfth data input and output terminal of the B channel of the LPDDR chip, and the LPDDR chip The pins in the seventh column, row T of the LPDDR chip are the sixteenth data input and output terminal of the B channel of the LPDDR chip; the pins in the seventh column, row Y of the LPDDR chip are the first write clock terminal of the B channel of the LPDDR chip, the pins in the seventh column, row AB of the LPDDR chip are the first differential read synchronization signal terminal of the B channel of the LPDDR chip, the pins in the seventh column, row E of the LPDDR chip and the pins in the J row are the input / output power supply terminals of the A channel of the LPDDR chip, and the pins in the seventh column, row R of the LPDDR chip and the pins in the W row are the input / output power supply terminals of the B channel of the LPDDR chip.

[0076] The pins in the eighth column and row J of the LPDDR chip are the first readout clock terminal of the A channel of the LPDDR chip, and the pins in the eighth column and row R of the LPDDR chip are the second readout clock terminal of the B channel of the LPDDR chip; the pins in the eighth column and row A and the pins in the L row of the LPDDR chip are the input / output power supply terminals of the A channel of the LPDDR chip, and the pins in the eighth column and row N and the pins in the AC row of the LPDDR chip are the input / output power supply terminals of the B channel of the LPDDR chip.

[0077] The pin of the ninth column, row B of the LPDDR chip is the third address terminal of the A channel of the LPDDR chip, the pin of the ninth column, row D of the LPDDR chip is the first address terminal of the A channel of the LPDDR chip, the pin of the ninth column, row G of the LPDDR chip is the second chip select terminal of the A channel of the LPDDR chip, the pin of the ninth column, row J of the LPDDR chip is the first write clock terminal of the A channel of the LPDDR chip, the pin of the ninth column, row K of the LPDDR chip is the first differential read synchronization signal terminal of the A channel of the LPDDR chip, the pin of the ninth column, row P of the LPDDR chip is the second differential read synchronization signal terminal of the B channel of the LPDDR chip, the pin of the ninth column, row R of the LPDDR chip The pin of the ninth column, row U of the LPDDR chip is the second write clock terminal of the B channel of the LPDDR chip; the pin of the ninth column, row Y of the LPDDR chip is the first address terminal of the B channel of the LPDDR chip, the pin of the ninth column, row AB of the LPDDR chip is the fourth address terminal of the B channel of the LPDDR chip, the pin of the ninth column, row C of the LPDDR chip, the pin of the E row and the pin of the H row are the input / output power supply terminals of the A channel of the LPDDR chip, the pin of the ninth column, row T of the LPDDR chip, the pin of the W row and the pin of the AA row are the input / output power supply terminals of the B channel of the LPDDR chip.

[0078] The pin of the tenth column, row B of the LPDDR chip is the second address terminal of the A channel of the LPDDR chip, the pin of the tenth column, row D of the LPDDR chip is the sixth address terminal of the A channel of the LPDDR chip, the pin of the tenth column, row F of the LPDDR chip is the reserved terminal of the LPDDR chip, the pin of the tenth column, row G of the LPDDR chip is the first chip select terminal of the A channel of the LPDDR chip, the pin of the tenth column, row K of the LPDDR chip is the first differential read synchronization signal terminal of the A channel of the LPDDR chip, the pin of the tenth column, row P of the LPDDR chip is the second differential read synchronization signal terminal of the B channel of the LPDDR chip, and the LPDDR chip The pins in the tenth column, row U of the LPDDR chip are the first chip select terminals of the B channel of the LPDDR chip, and the pins in the tenth column, row V of the LPDDR chip are the reserved terminals of the LPDDR chip; the pins in the tenth column, row Y of the LPDDR chip are the third address terminals of the B channel of the LPDDR chip, and the pins in the tenth column, row AB of the LPDDR chip are the second address terminals of the B channel of the LPDDR chip, the pins in the tenth column, row A of the LPDDR chip and the pins in the H row are the input / output power terminals of the A channel of the LPDDR chip, and the pins in the tenth column, row T of the LPDDR chip and the pins in the AC row are the input / output power terminals of the B channel of the LPDDR chip.

[0079] The pins in the eleventh column and row C of the LPDDR chip are the seventh address terminal of channel A of the LPDDR chip, the pins in the eleventh column and row E of the LPDDR chip are the fourth address terminal of channel A of the LPDDR chip, the pins in the eleventh column and row W of the LPDDR chip are the seventh address terminal of channel B of the LPDDR chip, and the pins in the eleventh column and row AA of the LPDDR chip are the sixth address terminal of channel B of the LPDDR chip; the pins in the eleventh column and row B of the LPDDR chip, the pins in the D row, the pins in the J row, the pins in the K row, and the pins in the L row are the input / output power terminals of channel A of the LPDDR chip, and the pins in the eleventh column and row N of the LPDDR chip, the pins in the P row, the pins in the R row, the pins in the Y row, and the pins in the AB row are the input / output power terminals of channel B of the LPDDR chip.

[0080] The pins in the twelfth column, row C of the LPDDR chip are the fifth address terminal of channel A of the LPDDR chip, the pins in the twelfth column, row F of the LPDDR chip are the differential clock signal terminal of channel A of the LPDDR chip, the pins in the twelfth column, row G of the LPDDR chip are the differential clock signal terminal of channel A of the LPDDR chip, the pins in the twelfth column, row U of the LPDDR chip are the differential clock signal terminal of channel B of the LPDDR chip, the pins in the twelfth column, row V of the LPDDR chip are the differential clock signal terminal of channel B of the LPDDR chip, the pins in the twelfth column, row AA of the LPDDR chip are the fifth address terminal of channel B of the LPDDR chip, the pins in the twelfth column, row J and the pins in the L row of the LPDDR chip are the input / output power supply terminals of channel A of the LPDDR chip, and the pins in the twelfth column, row N and the pins in the R row of the LPDDR chip are the input / output power supply terminals of channel B of the LPDDR chip.

[0081] The pins in the thirteenth column and row J of the LPDDR chip are the drive strength calibration signal terminals of the A channel of the LPDDR chip, the pins in the thirteenth column and row R of the LPDDR chip are the reset signal terminals of the LPDDR chip, the pins in the thirteenth column and row C of the LPDDR chip, the pins in the D row, the pins in the K row and the pins in the L row are the input / output power terminals of the A channel of the LPDDR chip, the pins in the thirteenth column and row N of the LPDDR chip, the pins in the P row, the pins in the Y row and the pins in the AA row are the input / output power terminals of the B channel of the LPDDR chip.

[0082] In addition, the pins of the first column, row A, the pins of the first column, row B, the pins of the first column, row AB, the pins of the first column, row AC, the pins of the second column, row A, the pins of the second column, row AC, the pins of the twelfth column, row A, the pins of the twelfth column, row AC, the pins of the thirteenth column, row A, the pins of the thirteenth column, row B, the pins of the thirteenth column, row AB, and the pins of the thirteenth column, row AC are all floating ends of the LPDDR chip. DNU (Do Not Use) means do not connect to power, GND, and any other signals. These pins must be left floating.

[0083] Secondly, the pins of the first column of the LPDDR chip are the pins of the D row, the pins of the J row, the pins of the L row, the pins of the N row, the pins of the R row, and the pins of the Y row; the pins of the second column are the pins of the E row, the pins of the L row, the pins of the N row, and the pins of the W row; the pins of the B row, the pins of the D row, the pins of the J row, the pins of the L row, the pins of the N row, the pins of the R row, the pins of the Y row, and the pins of the AB row; the pins of the H row, the pins of the K row, the pins of the P row, and the pins of the T row are in the fifth column. The pins of row B, the pins of row D, the pins of row J, the pins of row L, the pins of row N, the pins of row R, the pins of row Y, the pins of row AB; the pins of row A in the sixth column, the pins of row E, the pins of row H, the pins of row K, the pins of row P, the pins of row T, the pins of row W, and the pins of row AC; the pins of row A in the seventh column, the pins of row C, the pins of row L, the pins of row N, the pins of row AA, and the pins of row AC; the pins of row B in the eighth column, the pins of row C, and the pins of The pins of row H, the pins of row K, the pins of row P, the pins of row T, the pins of row AA, the pins of row AB; the pins of row A in the ninth column, the pins of row F, the pins of row L, the pins of row N, the pins of row V, the pins of row AC; the pins of row C in the tenth column, the pins of row E, the pins of row J, the pins of row L, the pins of row N, the pins of row R, the pins of row W, and the pins of row AA; the pins of row A in the eleventh column, the pins of row F, the pins of row G, the pins of row H, and the pins of row The pins of row M, row T, row U, row V, and row AC; the pins of row B in the twelfth column, row D, row E, row H, row K, row M, row P, row T, row W, row Y, and row AB; the pins of row F in the thirteenth column, row G, row H, row M, row T, row U, and row V are the ground terminals of the LPDDR chip.

[0084] Based on the above embodiment, the embodiment of the present application further provides an electronic device, wherein the processor in the electronic device can be the LPDDR chip packaging structure disclosed above in the present application. The LPDDR chip packaging structure is also provided with at least one control chip on one side, such as Figure 6 As shown, Figure 6 The schematic diagram of the connection between the LPDDR chip package structure and the control chip provided in the embodiment of the present application is shown, wherein the control chip is connected to the electrical connection ball of the LPDDR chip package structure by routing across the target edge. The target edge is the edge on the PCB that is connected to the strip area, such as Figure 6 The left edge is shown in FIG.

[0085] Optionally, the control chip may be a SOC control chip, and the SOC control chip may be a 32-bit chip. The SOC control chip is disposed on the PCB board and is electrically connected to the LPDDR chip.

[0086] Optionally, the SOC control chip includes a first A channel and a first B channel, the first A channel is electrically connected to the A channel of the LPDDR chip, and the first B channel is electrically connected to the B channel of the LPDDR chip.

[0087] Please refer to Figure 7 , Figure 7 A schematic diagram of the system structure of an electronic device provided in an embodiment of the present application is shown. The electronic device may include a processor, a memory and a communication interface connected via a system bus, wherein the processor is, for example, an LPDDR chip packaging structure provided in an embodiment of the present application. The processor is the control center of the electronic device, and uses various interfaces and lines to connect various parts of the entire mobile terminal. By running or executing software programs and / or modules stored in the memory, and calling data stored in the memory, it executes various functions of the electronic device and processes data, thereby monitoring the electronic device as a whole. The processor may include one or more processing units; preferably, the processor may integrate an application processor and a modem processor, and optionally, the application processor mainly processes an operating system, a user interface, and application programs, etc., and the modem processor mainly processes wireless communications. It is understandable that the above-mentioned modem processor may not be integrated into the processor.

[0088] The memory can be used to store software programs and various data. The memory can mainly include a program storage area and a data storage area. Optionally, the program storage area can store an operating system, an application required for at least one function (such as a sound playback function, an image playback function, etc.), etc.; the data storage area can store data created according to the use of the mobile phone (such as audio data, a phone book, etc.), etc. In addition, the memory can include a high-speed random access memory, and can also include a non-volatile memory, such as at least one disk storage device, a flash memory device, or other volatile solid-state storage devices.

[0089] It should be noted that Figure 7 The structure of the electronic device shown does not constitute a limitation of the electronic device, and the electronic device may include more or fewer components than shown in the figure, or combine certain components, or arrange the components differently.

[0090] The above examples are only reference examples. In order to avoid redundancy, they are not listed one by one here. In actual development or application, they can be flexibly combined according to actual needs, but any combination belongs to the technical solution of this application and is covered within the scope of protection of this application.

[0091] The above are only preferred embodiments of the present application, and are not intended to limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A LPDDR chip packaging structure, characterized in that: Including PCB board and more than two LPDDR wafers; The two or more LPDDR wafers are arranged on the back of the PCB board, and the front of the PCB board is arrayed with electrical balls for connecting to an external circuit, and the electrical balls are connected to the pins of the LPDDR wafers through wiring; The front side of the PCB board is provided with a plurality of strip-shaped areas, the strip-shaped areas are prohibited from arranging the electrical balls, and the strip-shaped areas are connected to the same edge of the PCB board; three grounding electrical balls are provided on the PCB board along the symmetry line of two adjacent LPDDR wafers; Among them, the multiple strip areas include a first strip area and a second strip area, wherein the first strip area includes a main strip area, the second strip area includes a main strip area and a sub-strip area, the first strip area covers or partially covers the symmetry line of the orthographic projection area of ​​two adjacent LPDDR wafers on the PCB board, and the second strip area is arranged within the orthographic projection area of ​​each LPDDR wafer on the PCB board.

2. The LPDDR chip packaging structure according to claim 1, characterized in that: Include at least one of the following: The spacing between any adjacent electrical balls in the non-strip area is equal; The width of the strip-shaped area is greater than the distance between any adjacent electrical balls in the non-strip-shaped area.

3. The LPDDR chip packaging structure according to claim 2, characterized in that: The strip area includes at least one of the following: A main strip area, the main strip area is connected to the edge of the PCB board; At least one secondary strip region, wherein the secondary strip region is disposed within an orthographic projection region of the at least one LPDDR wafer on the PCB board, and the secondary strip region and the primary strip region have different extension directions.

4. The LPDDR chip packaging structure according to claim 3, characterized in that: The main strip area includes at least one of the following: The main strip area is arranged within the orthographic projection area of ​​the LPDDR wafer on the PCB board; The main strip area at least partially covers the symmetry line of the orthographic projection area.

5. The LPDDR chip packaging structure according to claim 1, characterized in that: Include at least one of the following: The wiring is arranged on the front side of the PCB board; The PCB board is provided with an insulating layer covering the wiring, the insulating layer is provided with an opening, and the electrical ball extends out of the opening.

6. The LPDDR chip packaging structure according to any one of claims 1 to 5, characterized in that: The LPDDR chip packaging structure includes a first LPDDR wafer and a second LPDDR wafer that are symmetrically arranged; the electrical balls and the wiring on the PCB board are also arranged symmetrically about the symmetry lines of the two wafers.

7. The LPDDR chip packaging structure according to claim 6, characterized in that: Include at least one of the following: At least one grounding ball for grounding is arranged on the PCB board along the symmetry line of the two wafers; At least one strip area is arranged on the PCB board to cover the symmetry line of the two wafers.

8. The LPDDR chip packaging structure according to claim 7, characterized in that: The width of the strip region covering the symmetry line of the two wafers is smaller than the width of other strip regions.

9. An electronic device, characterized in that: It comprises the LPDDR chip packaging structure as claimed in any one of claims 1 to 8.

10. The electronic device according to claim 9, characterized in that: The edge on the PCB board connected to the strip area is a target edge; At least one control chip is also disposed on one side of the LPDDR chip package structure. The control chip is connected to the electrical ball of the LPDDR chip package structure via a wiring across the target edge.

Images