Register disturbance device, chip verification method and system, equipment and storage medium

Abstract

The present application provides a UVM-based register perturbation device, a chip verification method, a chip verification system, a chip verification equipment and a computer-readable storage medium. Based on the random testing concept of UVM methodology, a register chip verification environment including a UVM register model and at least one perturbation generating device is constructed, which can initiate random perturbation access operations to the chip under test, and can be combined with a large number of regression tests to initiate various types and combinations of perturbations to increase the coverage of random perturbations, thereby greatly increasing the exposure probability of system defects, to verify the robustness of the chip under test, and to improve the detection rate of register access perturbation defects for the chip under test.

Description

Technical Field

[0001] The present application relates to the field of chip verification technology, and in particular to a UVM-based register perturbation device, a chip verification method, a chip verification system, a chip verification device, and a computer-readable storage medium. Background Art

[0002] System on Chip (SOC) is an integrated circuit chip that can effectively reduce the development cost of electronic / information system products, shorten the development cycle, and improve product competitiveness. It is the most important product development method that the industry will adopt in the future.

[0003] In the process of chip development, verification plays a vital role and is also a key step to ensure chip quality. The commonly used verification method is to use the Universal Verification Methodology (UVM) to verify the chip under test. Registers are one of the most important parts of SOC chips, and the registers in SOC chips are large in number and constantly changing. Therefore, register verification is an important part of the verification process.

[0004] The most common register access interfaces of SOC chips can be divided into two categories. The first is the register access initiated by the CPU inside the SOC through the corresponding interface. The second is the external physical interface (referred to as peripheral interface) provided by the SOC to users to access internal registers, such as the common MDIO, I2C, SPI and other standard interfaces.

[0005] Since internal registers are often only allowed to be accessed by a single interface at the same time, a bus arbiter module is usually used in SOC design to arbitrate between access operations initiated by different interfaces to ensure the single interface characteristics of register access. When verifying the SOC chip system, verification personnel usually focus on testing the conflicts between the above two types of interfaces within the chip, that is, verifying the function of the bus arbiter module. However, due to the diversity of the timing of access conflicts between different interfaces, it is easy to make omissions in the actual verification process, resulting in unexpected problems in actual use.

[0006] In addition, due to the particularity of SOC chips, the CPU plays a vital role. During the operation of the chip, the CPU will continuously access internal registers to obtain and control the functional behavior of the chip. Even when the interface bus arbiter is relatively fully verified, it is possible that the CPU will hang due to defects in the program itself and sudden register access by the user during operation. For example, when the CPU program runs to a certain moment, it needs to read the value of a certain internal register to perform the next operation, and there are strict timeliness requirements. At this time, the user is occupying the bus to access the internal register through the peripheral interface, causing the CPU to not respond immediately and hang. This is extremely difficult to be discovered in time during the conventional verification process, but it is fatal in actual use.

[0007] In SOC chips, in addition to the CPU being affected by the user's random access to registers, complex functional modules will also be disturbed. For example, if a functional module is interacting with a register, such as writing status or reading configuration, and the user happens to access other registers of the module through an external interface at this time, due to the design defects of the register itself, the behavior initiated by the module on the register will change unexpectedly, causing the module to malfunction. Summary of the invention

[0008] In view of the above-mentioned defects or shortcomings of the prior art, the present application provides a UVM-based register perturbation device, a chip verification method, a chip verification system, a chip verification equipment and a computer-readable storage medium, which are used to solve the problems of conflicts, omissions, affecting the normal operation of the CPU or causing errors in functional modules in register access operations in the prior art.

[0009] In a first aspect, the present application provides a register perturbation device based on UVM, which is suitable for verifying a chip under test, wherein the chip under test has at least one register, and the register perturbation device comprises: a register pool, storing register information associated with one or more registers that can be safely accessed in the chip under test; a perturbation generator, connected to the register pool, for selecting a target register that meets a register filtering rule from the register pool, and calling a connected UVM register model based on a calculated perturbation interval time and a selected operation mode to initiate a perturbative access operation to the target register in the selected chip under test; wherein the UVM register model is connected to the chip under test, and the operation mode comprises a write operation, a read operation, a read and write operation, and a write and read operation.

[0010] In an implementation of the first aspect, the disturbance generator includes: a disturbance interval calculation unit, which is used to calculate the disturbance time interval between the occurrence of this disturbance and the occurrence of the previous disturbance according to the configured maximum disturbance time interval and minimum disturbance time interval; a register selection unit, which is used to randomly select a register that meets the register filtering rule from the register pool as a target register; a disturbance operation generation unit, which is connected to the disturbance interval calculation unit, the register selection unit, and the UVM register model, and is used to randomly select an operation mode from multiple configured operation modes after receiving the disturbance time interval output by the disturbance interval calculation unit, and call the UVM register model to initiate a perturbative access operation to the target register selected by the register selection unit in the connected chip to be tested.

[0011] In an implementation of the first aspect, the disturbance generator also includes: a safe exit control unit, connected to the disturbance operation generating unit, for generating an access exit instruction and sending the access exit instruction to the disturbance operation generating unit so that the disturbance operation generating unit waits for the current access operation to end and then exits safely according to the access exit instruction.

[0012] In an implementation of the first aspect, the disturbance generator further includes: a dynamic control unit connected to the disturbance operation generating unit, configured to generate a control instruction and send the control instruction to the disturbance operation generating unit so that the disturbance operation generating unit responds to the control instruction to perform a control operation.

[0013] In an implementation manner of the first aspect, the dynamic control unit further includes a device for configuring register filtering rules.

[0014] In a second aspect, the present application provides a chip verification method based on UVM, which is suitable for verifying a chip to be tested, wherein the chip to be tested has at least one register, and the chip verification method comprises the following steps: creating a UVM register model to create at least one disturbance generating device as described in any one of claims 1 to 5, wherein the UVM register model is connected to the chip to be tested, and the creation of at least one disturbance generating device comprises: creating a register pool, wherein the memory pool stores register information associated with one or more registers that can be safely accessed in the chip to be tested; creating a disturbance generator, wherein the disturbance generator is connected to the register pool and the UVM register model; based on a base class use case of simulation verification, starting the disturbance generator, selecting a target register that meets the register filtering rule from the register pool, and calling the UVM register model based on the calculated disturbance interval time and the selected operation mode to initiate a perturbative access operation to the target register in the selected chip to be tested; wherein the operation mode includes a write operation, a read operation, a read and write operation, and a write and read operation.

[0015] In an implementation of the second aspect, the chip verification method further includes a base class use case based on simulation verification, wherein the disturbance generator generates an access exit instruction and waits for a current access operation to end before safely exiting according to the access exit instruction.

[0016] In an implementation manner of the second aspect, the chip verification method further includes a special use case based on simulation verification, where the disturbance generator generates a control instruction and performs a control operation according to the control instruction.

[0017] The present application provides a UVM-based chip verification system in a third aspect, which is suitable for verifying a chip to be tested, wherein the chip to be tested has at least one register, and the chip verification system includes: a UVM register model, wherein the UVM register model is connected to the chip to be tested; at least one disturbance generating device as described above, wherein the disturbance generating device includes a register pool and a disturbance generator, wherein the register pool stores register information associated with one or more registers that can be safely accessed in the chip to be tested, and the disturbance generator is connected to the register pool and the UVM register model, and is used to select a target register that meets the register filtering rule from the register pool, and call the UVM register model based on the calculated disturbance interval time and the selected operation mode to initiate a perturbative access operation to the target register in the selected chip to be tested; wherein the UVM register model is connected to the chip to be tested, and the operation mode includes a write operation, a read operation, a read and write operation, and a write and read operation.

[0018] In a fourth aspect, the present application provides a UVM-based chip verification device, comprising: a memory for storing at least one computer program; a processor connected to the memory, for executing the at least one computer program to implement the UVM-based chip verification method as described above.

[0019] In a fifth aspect, the present application provides a computer-readable storage medium storing at least one computer program, wherein when the computer program is executed by a processor, the UVM-based chip verification method as described above is implemented.

[0020] As described above, the register perturbation device based on UVM, chip verification method, chip verification system, chip verification equipment and computer-readable storage medium disclosed in the present application have the following beneficial effects: the technical solution is based on the random testing concept of UVM methodology, and constructs a register chip verification environment including a UVM register model and at least one perturbation generating device, which is simple and easy to deploy, has low cost of use, and has significant effect. The technical solution can initiate random perturbation access operations to the chip to be tested, and can be combined with a large number of regression tests to initiate various types and various combinations of perturbations, increase the coverage of random perturbations, thereby greatly increasing the exposure probability of system defects to verify the robustness of the chip to be tested. In addition, the technical solution can make full use of random characteristics to carry out enhanced testing, so as to collide with edge cases and loopholes that are not easily detected by conventional methods, thereby improving the detection rate of register access perturbation defects for the chip to be tested. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 Shown is an application schematic diagram of a register perturbation device based on UVM in one embodiment of the present application.

[0022] Figure 2 Shown is the register access architecture of the SOC chip.

[0023] Figure 3 Display as Figure 1 A schematic diagram of the structure of a disturbance generator in one embodiment.

[0024] Figure 4 Shown is a schematic diagram of a register access operation performed by a UVM-based register perturbation device of the present application in one embodiment.

[0025] Figure 5 Shown is a schematic diagram of the application of the chip verification system provided by the present application in another embodiment.

[0026] Figure 6 Shown is a schematic flow chart of a chip verification method in one embodiment of the present application.

[0027] Figure 7 Shown is a schematic diagram of the structure of a UVM-based chip verification device in one embodiment of the present application. DETAILED DESCRIPTION

[0028] The following describes the embodiments of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. The present application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0029] It should be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present application, and thus the drawings only show components related to the present application rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed at will, and the component layout may also be more complicated.

[0030] In the following description, a large number of details are discussed to provide a more thorough explanation of the embodiments of the present application. However, it is obvious to those skilled in the art that the embodiments of the present application can be implemented without these specific details. In other embodiments, well-known structures and devices are shown in the form of block diagrams rather than in detail to avoid making the embodiments of the present application difficult to understand.

[0031] The terms "first", "second", etc. in the specification and claims of the embodiments of the present disclosure and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchanged where appropriate, so that the embodiments of the embodiments of the present disclosure described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions.

[0032] Unless otherwise specified, the term "plurality" means two or more than two. In the disclosed embodiments, the character " / " indicates that the objects before and after are in an "or" relationship. For example, A / B means: A or B. The term "and / or" is a description of the association relationship between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or, A and B.

[0033] In the process of chip development, verification plays a vital role, and register is an important component in SOC chip, therefore, the verification of register is an important part in the verification process. However, in the existing verification technology, there are problems such as omissions due to different interface access conflicts, sudden accesses causing CPU to hang up or some functional modules to be disturbed and errors. In view of this, the present application provides a register disturbance device based on UVM, a chip verification method, a chip verification system, a chip verification device and a computer-readable storage medium, which can initiate random perturbation access operations to the chip to be tested, and can be combined with a large number of regression tests, various types, various combinations of disturbances are initiated to verify the robustness of the chip to be tested, and the edge cases and loopholes that are not easily perceived by conventional methods can be detected by enhanced testing, and the detection rate of register access disturbance defects for the chip to be tested is improved.

[0034] See also Figure 1 , Figure 1 The following is a schematic diagram showing an application of the UVM-based register perturbation device in one embodiment of the present application. Figure 1 As shown, in the embodiment, the UVM-based register perturbation device 1 is connected to a UVM register model 2, and the two can form a chip verification system based on UVM. The UVM register model 2 is connected to a chip to be tested 3, and the chip to be tested 3 can be, for example, a chip to be tested. In the following, the chip to be tested is described by taking a SoC (System On Chip) chip as an example.

[0035] With the development of integrated circuit technology, an integrated system has evolved, which is composed of multiple integrated circuits with specific functions combined on a single chip and can process various information. This type of integrated system is called System On Chip (SOC). SOC chips have greatly reduced system costs, shortened design cycles, and reduced design risks, but they have also brought great challenges to SOC verification. Among them, registers are one of the most important parts of SOC chips, and the registers in SOC chips are large in number and constantly changing. Therefore, register verification is an important part of the verification process.

[0036] See also Figure 2 , showing the register access architecture of the SOC chip. Figure 2As shown, the SOC chip may include a central processing unit CPU31, a register group 33 including multiple registers, a functional module / data path 34, etc., wherein the corresponding registers can be accessed through the register interface. The most common register access interfaces of the SOC chip can be divided into two categories, one is the internal interface provided by the SOC to the CPU to directly access the register, and the other is the external physical interface (referred to as the peripheral interface) provided by the SOC to the external device to access the register, such as the common MDIO, I2C, SPI and other standard interfaces, such as Figure 1 Peripheral interface A and peripheral interface B in the device. Since a register is usually only allowed to be accessed by a single interface at the same time, a bus arbiter 32 is usually used in SOC chip design to arbitrate between access operations initiated by different interfaces to ensure the single interface characteristic of register access.

[0037] Described UVM register model is built and configured based on UVM methodology, and UVM is the abbreviation of UniversalVerification Method (universal verification methodology), and it is a kind of verification methodology newly developed in chip verification industry.In the verification of SOC chip, UVM plays a vital role with the identity of mainstream verification methodology, and instructs verification personnel to create a verification platform with strong reusability and interpretability under a scientific framework.For the register access operation in SOC, UVM provides a set of register abstraction layer method, helps verification personnel to set up, maintain, control and test the register in the module under test with the general paradigm of standard.

[0038] like Figure 1 As shown, the UVM register model 2 is connected to the chip under test 3. Figure 2 Taking the SOC chip in as an example, the UVM register model 2 can be connected to the external physical interface of the SOC chip to be tested (i.e., peripheral interface A and peripheral interface B), so as to realize register access operations such as read, write, read+write, write+read, etc.

[0039] The UVM-based register perturbation device 1 may include a register pool 10 and a perturbation generator 11 .

[0040] The register pool 10 stores register information associated with one or more registers that can be safely accessed in the chip to be tested. As mentioned above, the SOC chip to be tested includes multiple registers. When verifying the SOC chip, the verification personnel can select some registers that can be safely accessed from the information of all registers in the SOC chip, that is, access to these selected registers will not affect the relevant functional modules. Such registers are, for example, reserved registers that are not usually used, test registers, readable status registers, and debug function registers.

[0041] A register pool can be constructed by summarizing the information of some of the selected registers. In some embodiments, the information of some of the selected registers is stored in the form of a list, an array, or a queue, so as to construct a register pool. It can be seen that one or more registers associated with the register information stored in the constructed register pool correspond to the registers in the SOC chip to be tested. Of course, according to the changes in the type of SOC chip to be tested, the type of registers in the SOC chip, the verification content, etc., the registers in the SOC chip can be selected differently, so that the information of the registers stored in the register pool is updated.

[0042] The disturbance generator 11 is connected with the register pool 10 and the UVM register model 2, and the disturbance generator 11 is constructed based on the UVM methodology, and can interact with the UVM register model 2, and complies with the grammar and concept of UVM. Specifically, the disturbance generator 11 is used to select the target register that meets the register filtering rule from the register pool 10, and the UVM register model 2 connected is called based on the disturbance interval time calculated and the operating mode selected, so as to initiate a perturbative access operation to the target register in the selected chip to be tested 3 (for example, SOC chip). In certain embodiments, the operating mode includes a write operation, a read operation, a read and write operation, and a write and read operation.

[0043] See also Figure 3 , displayed as Figure 1 A schematic diagram of the structure of a disturbance generator in one embodiment.

[0044] like Figure 3 As shown, the disturbance generator 11 may include a disturbance interval calculation unit 111 , a register selection unit 112 , and a disturbance operation generation unit 113 .

[0045] The disturbance interval calculation unit 111 is used to calculate the disturbance time interval between the current disturbance and the previous disturbance according to the configured maximum disturbance time interval and minimum disturbance time interval. In some embodiments, the maximum disturbance time interval and the minimum disturbance time interval may have different configurations according to the type of SOC chip to be tested, the type of registers in the SOC chip, the verification content, etc. In practical applications, a random time is calculated based on the maximum disturbance time interval and the minimum disturbance time interval, and the obtained random time is used as the disturbance time interval between the current disturbance and the previous disturbance. In some embodiments, the minimum disturbance time interval may be 0, and the disturbance interval time may also be 0.

[0046] The register selection unit 112 is used to randomly select a register that meets the register filtering rule from the register pool 10 as the target register. As mentioned above, the register pool stores register information associated with one or more registers that can be safely accessed in the SOC chip to be tested. Therefore, the register selection unit 112 randomly selects a register that meets the register filtering rule from the register pool 10, that is, selects a register from the register information stored in the register pool 10 (the register information can be in the form of a list, array or queue, etc.) as the target register.

[0047] The disturbance operation generating unit 113 is connected to the disturbance interval calculation unit 111, the register selection unit 112, and the UVM register model 2, and is used to randomly select an operation mode from the configured multiple operation modes after receiving the disturbance time interval output by the disturbance interval calculation unit 111, and call the UVM register model 2 to initiate a disturbing access operation to the target register selected by the register selection unit 112 in the connected chip to be tested. In some embodiments, the disturbance operation generating unit 113 first waits for the disturbance interval time output by the disturbance interval calculation unit 111, and after the disturbance interval time ends, randomly selects an operation mode from four operation modes including write operation, read operation, read and write operation, and write and read operation, and then calls the UVM register model 2 to initiate a disturbing access operation to the target register selected by the register selection unit 112 in the SOC chip to be tested. Among them, the access operation corresponds to the randomly selected operation mode, for example: if the randomly selected operation is a read operation, the read operation is performed on the target register; if the randomly selected operation is a write operation, the write operation is performed on the target register; if the randomly selected operations are read and write operations, the read and write operations are performed on the target register; if the randomly selected operations are write and read operations, the write and read operations are performed on the target register.

[0048] The disturbance interval calculation unit 111, the register selection unit 112, and the disturbance operation generation unit 113 are related to the main process of the disturbance generator 11. After the disturbance generator 11 is started, these three units will work in sequence in a cycle, that is, after the disturbance interval calculation unit 111, the register selection unit 112, and the disturbance operation generation unit 113 complete an access operation within the corresponding disturbance time interval, they will continue to complete the next access operation within the next disturbance time interval.

[0049] The disturbance generator 11 may further include a safety exit control unit 114, which is connected to the disturbance operation generating unit 113 and is used to generate an access exit instruction and send the access exit instruction to the disturbance operation generating unit 113 so that the disturbance operation generating unit 113 waits for the current access operation to end and then safely exits according to the access exit instruction. As mentioned above, after the disturbance generator 11 is started, the disturbance interval calculation unit 111, the register selection unit 112, and the disturbance operation generating unit 113 will work in sequence and cyclically, but when the disturbance operation generating unit 113 receives the access exit instruction generated by the safety exit control unit, it waits for the current access operation to end and then safely exits.

[0050] The disturbance generator 11 further includes a dynamic control unit 115 connected to the disturbance operation generating unit 113 .

[0051] The dynamic control unit 115 can be used to generate a control instruction and send the control instruction to the disturbance operation generating unit 113 so that the disturbance operation generating unit 113 responds to the control instruction to perform a control operation. In some embodiments, the control instruction can be, for example, access suspension, access reply, etc., to achieve autonomous control, and to deal with special scenarios such as the reset and resetting of the target register being accessed. For example, when the CPU program runs to a certain moment, it needs to read the value of a certain register to perform the next operation, and there are strict timeliness requirements. At this time, the register is occupied through the peripheral interface. In this case, the dynamic control unit 115 can generate an access suspension instruction and send the access suspension instruction to the disturbance operation generating unit so that the disturbance operation generating unit 113 responds to the access suspension instruction to suspend the ongoing access operation until the CPU program completes the reading of the target register, and then the dynamic control unit 115 generates an access recovery instruction so that the disturbance operation generating unit 113 responds to the access recovery instruction to resume the access operation.

[0052] The dynamic control unit 115 can also be used to configure register filtering rules. In some embodiments, the register filtering rules can be preference filtering rules, that is, registers that meet the preference filtering rules are selected. In some embodiments, the register filtering rules can be prohibitive filtering rules, that is, registers within the prohibitive filtering rules are excluded. Of course, the register filtering rules can also adopt other types of rules. In addition, the register filtering rules can be updated according to changes in the type of SOC chip to be tested, the type of registers in the SOC chip, the verification content, etc.

[0053] See also Figure 4, which is a schematic diagram showing a register access operation performed by a register perturbation device based on UVM in one embodiment of the present application. The register perturbation device 1 can be implemented as follows after startup: Figure 4 As shown in the random perturbation access operation for registers in the SOC chip, the single register random perturbation access time is t (represented by a column), and there is a random perturbation interval T between two adjacent register random perturbation access times. During each register random perturbation access time, a register is randomly selected as the target register within a controlled range and an access operation of a random operation mode (e.g., read, write, read and write, write and read) is performed on the target register until a safe exit is received after an access exit instruction is received.

[0054] like Figure 1 As shown, the register perturbation device and chip verification system provided by the present application (the chip verification system includes a UVM register model and a perturbation generating device) are based on the random testing concept of UVM methodology to construct a register chip verification environment including a UVM register model and at least one perturbation generating device, which can initiate random perturbation access operations to the chip under test, and can be combined with a large number of regression tests to initiate various types and combinations of perturbations to verify the robustness of the chip under test.

[0055] See also Figure 5 , which is a schematic diagram of the application of the chip verification system provided by the present application in another embodiment. Figure 5 As shown, there are multiple external physical interfaces (peripheral interfaces for short) provided to users for accessing internal registers by the SOC chip as the chip to be tested. Taking two peripheral interfaces as examples, they are respectively represented as peripheral interface A and peripheral interface B. Therefore, in the chip verification system provided in this embodiment, a register perturbation device A corresponding to the peripheral interface A and a register perturbation device B corresponding to the peripheral interface B are included. That is to say, the chip verification system includes a register perturbation device A1, a register perturbation device B1', and a UVM register model 2, wherein the register perturbation device A1 corresponds to the peripheral interface A through the UVM register model 2, and the register perturbation device B1' corresponds to the peripheral interface B through the UVM register model 2. The register perturbation device A1 may include a register pool A and a perturbation generator A, and the register perturbation device B1' may include a register pool B and a perturbation generator B. The configuration of the register pool A and the perturbation generator A in the register perturbation device A1 and the configuration of the register pool B and the perturbation generator B in the register perturbation device B1' may have different configurations according to changes in the verification environment. In this way, during the verification process, different UVM register models 2 can be additionally specified to different register perturbation devices, so that perturbative access operations can be initiated to registers in the SOC chip through different peripheral interfaces.

[0056] This application also provides a chip verification method, see Figure 6 , which is a schematic diagram of the flow chart of the chip verification method of the present application in one embodiment.

[0057] See also Figure 6 Combined with Figure 1 and Figure 3 In some embodiments, the chip verification method includes the following steps:

[0058] Step S601, creating a UVM register model and creating at least one disturbance generating device.

[0059] The UVM register model is connected to the chip to be tested.

[0060] In some embodiments, the disturbance generating device includes a register pool and a disturbance generator. Therefore, creating the disturbance generating device at least includes: creating a register pool and creating a disturbance generator, wherein the memory pool stores register information associated with one or more registers that can be securely accessed in the chip under test, and the disturbance generator is connected to the register pool and the UVM register model.

[0061] In such Figure 3 In the illustrated embodiment, when the disturbance generator includes module components such as a disturbance interval calculation unit, a target register selection unit, a disturbance operation generation unit, a safe exit control unit, and a dynamic control unit, the step of creating the disturbance generator includes creating these module components. Creating these module components also includes configuring these module components accordingly, for example, configuring the maximum disturbance interval time and the minimum disturbance interval time applied to the disturbance interval calculation unit, configuring register filtering rules through the dynamic control unit, etc.

[0062] Through the above step S601, the following can be constructed: Figure 1 and Figure 3 The chip verification system shown.

[0063] Step S603, based on the base class use case verified by simulation, start the disturbance generator, select the target register that meets the register filtering rule from the register pool, call the UVM register model based on the calculated disturbance interval time and the selected operation mode to initiate a perturbative access operation to the target register in the selected chip under test; wherein the operation mode includes a write operation, a read operation, a read and write operation, and a write and read operation.

[0064] Generally, in a base class use case based on simulation verification, the above-mentioned calculation of the disturbance interval time, selection of the target register that meets the register filtering rules from the register pool, and calling the UVM register model based on the calculated disturbance interval time and the selected operation mode to initiate a perturbative access operation to the target register in the selected chip under test are executed in a loop.

[0065] In step S603, based on the base class use case verified by simulation, it also includes: the disturbance generator generates an access exit instruction and waits for a safe exit after the current access operation is completed according to the access exit instruction.

[0066] In addition, the chip verification method also includes: based on a special use case of simulation verification, the disturbance generator generates a control instruction and performs a control operation according to the control instruction. In some embodiments, the control instruction may be, for example, access suspension, access reply, etc., to achieve autonomous control, and to deal with special scenarios such as the reset and resetting of the target register being accessed. For example, when the CPU program runs to a certain moment, it needs to read the value of a register to perform the next operation, and there are strict timeliness requirements. At this time, the register is occupied through the peripheral interface. In this case, the disturbance generator can generate an access suspension instruction and respond to the access suspension instruction to suspend the ongoing access operation until the CPU program completes the reading of the target register, and then the disturbance generator generates an access recovery instruction and responds to the access recovery instruction to resume the access operation.

[0067] Generally, when verifying SOC chips, regression testing methods are usually used to perform a large number of simulations on developed use cases, and through continuous iterations, the error rate and coverage of the use cases converge. The chip verification method provided in this application can be applied to most test cases, running in the background process in a user-imperceptible manner, and initiating random perturbative access to the chip under test. After being integrated in the verification environment, by turning on the disturbance generating device during regression testing, the disturbance generator can easily initiate various types and combinations of disturbances, and can increase the coverage of random disturbances with the help of the regression test process, thereby greatly increasing the probability of exposure of system defects to test the robustness of the system.

[0068] Based on the above embodiments, the present application also provides a chip verification device based on UVM. Figure 7 , which is a schematic diagram of the structure of a UVM-based chip verification device in one embodiment of the present application. The UVM-based chip verification device 7 includes: a processor 71, a memory 73, and a computer program 75 stored in the memory 73 and executable on the processor 71. When the processor 71 executes the computer program 75, the steps in the above chip verification method embodiment are implemented.

[0069] The processor 71 may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or the processor may be any conventional processor, etc.

[0070] The memory 73 may be an internal storage unit of the chip verification device 7, such as a hard disk or memory of the chip verification device 7. The memory 73 may also be an external storage device of the chip verification device 7, such as a plug-in hard disk, a smart memory card (Smart Media Card, SMC), a secure digital (Secure Digital, SD) card, a flash card (Flash Card), etc. equipped on the chip verification device 7. Further, the memory 73 may also include both an internal storage unit of the chip verification device 7 and an external storage device. The memory 73 is used to store computer programs and other programs and data required by the chip verification device. The memory 73 may also be used to temporarily store data that has been output or is to be output.

[0071] The computer program 75 may be divided into one or more modules / units. The one or more modules / units may be a series of computer program instruction segments capable of completing specific functions. The instruction segments are used to describe the execution process of the computer program 75 in the chip verification device 6 .

[0072] In addition to the above structure, those skilled in the art can understand that Figure 7 It is only an example of the chip verification device 7 and does not constitute a limitation of the chip verification device 7. The chip verification device 7 may include more or fewer components than shown in the figure, or a combination of certain components, or different components. For example, the chip verification device may also include input and output devices, network access devices, buses, etc.

[0073] Those skilled in the art can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional units and modules is used as an example for illustration. In actual applications, the above-mentioned functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units. In addition, the specific names of the functional units and modules are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of this application. The specific working process of the units and modules in the above-mentioned system can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here.

[0074] Based on the above embodiments, the present application also provides a computer-readable storage medium on which at least one computer program is stored. When the computer program is executed by a processor, the vehicle control method in the above embodiments is implemented.

[0075] A person of ordinary skill in the art can understand that all or part of the steps in the method for implementing the above-mentioned embodiment can be completed by instructing a processor through a program, and the program can be stored in a computer-readable storage medium, and the storage medium is a non-transitory medium, such as a random access memory, a read-only memory, a flash memory, a hard disk, a solid-state hard disk, a magnetic tape, a floppy disk, an optical disc, and any combination thereof. The above-mentioned storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or a data center that includes one or more available media. The available medium can be a magnetic medium (for example, a floppy disk, a hard disk, a tape), an optical medium (for example, a digital video disc (DVD)), or a semiconductor medium (for example, a solid-state disk (SSD)), etc.

[0076] The descriptions of the processes or structures corresponding to the above-mentioned figures have different emphases. For parts that are not described in detail in a certain process or structure, please refer to the relevant descriptions of other processes or structures.

[0077] The above embodiments are merely illustrative of the principles and effects of the present application and are not intended to limit the present application. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed in the present application shall still be covered by the claims of the present application.

Claims

1. A register perturbation device based on UVM, suitable for verifying a chip under test, wherein the chip under test has at least one register, characterized in that: The register disturbance device comprises: a register pool storing register information associated with one or more registers in the chip under test that can be securely accessed; and A disturbance generator is connected to the register pool, and is used to select a target register that meets the register filtering rule from the register pool, and call the connected UVM register model based on the calculated disturbance interval time and the selected operation mode to initiate a perturbative access operation to the target register in the selected chip under test; wherein the UVM register model is connected to the chip under test, and the operation mode includes a write operation, a read operation, a read and write operation, and a write and read operation.

2. The register perturbation device based on UVM according to claim 1, characterized in that, The disturbance generator comprises: A disturbance interval calculation unit, used to calculate the disturbance time interval between the occurrence of the current disturbance and the occurrence of the previous disturbance according to the configured maximum disturbance time interval and minimum disturbance time interval; a register selection unit, configured to randomly select a register that meets the register filtering rule from the register pool as a target register; and A disturbance operation generating unit is connected to the disturbance interval calculating unit, the register selecting unit, and the UVM register model, and is used to randomly select an operation mode from multiple configured operation modes after receiving the disturbance time interval output by the disturbance interval calculating unit, and call the UVM register model to initiate a disturbing access operation to the target register selected by the register selecting unit in the connected chip to be tested.

3. The register perturbation device based on UVM according to claim 2, characterized in that, The disturbance generator also includes: a safe exit control unit, which is connected to the disturbance operation generating unit and is used to generate an access exit instruction and send the access exit instruction to the disturbance operation generating unit so that the disturbance operation generating unit waits for the current access operation to end and then safely exits according to the access exit instruction.

4. The register perturbation device based on UVM according to claim 2, characterized in that, The disturbance generator further includes: a dynamic control unit connected to the disturbance operation generating unit, configured to generate a control instruction and send the control instruction to the disturbance operation generating unit so that the disturbance operation generating unit responds to the control instruction to perform a control operation.

5. The register perturbation device based on UVM according to claim 4, characterized in that, The dynamic control unit also includes a filter for configuring registers.

6. A chip verification method based on UVM, suitable for verifying a chip to be tested, wherein the chip to be tested has at least one register, characterized in that: The chip verification method comprises the following steps: Creating a UVM register model to create at least one register perturbation device as described in any one of claims 1 to 5, wherein the UVM register model is connected to the chip under test, and the creating at least one register perturbation device comprises: creating a register pool, wherein the register pool stores register information associated with one or more registers that can be securely accessed in the chip under test; creating a perturbation generator, wherein the perturbation generator is connected to the register pool and the UVM register model; and Based on the base class use case verified by simulation, the disturbance generator is started, a target register that meets the register filtering rule is selected from the register pool, and the UVM register model is called based on the calculated disturbance interval time and the selected operation mode to initiate a perturbative access operation to the target register in the selected chip under test; wherein the operation mode includes a write operation, a read operation, a read and write operation, and a write and read operation.

7. The chip verification method based on UVM according to claim 6, characterized in that, It also includes a base class use case based on simulation verification, in which the disturbance generator generates an access exit instruction and waits for the current access operation to end before safely exiting according to the access exit instruction.

8. The chip verification method based on UVM according to claim 6, characterized in that, It also includes special use cases based on simulation verification, in which the disturbance generator generates control instructions and performs control operations according to the control instructions.

9. A chip verification system based on UVM, suitable for verifying a chip to be tested, wherein the chip to be tested has at least one register, characterized in that: The chip verification system comprises: A UVM register model, wherein the UVM register model is connected to the chip to be tested; and At least one register perturbation device according to any one of claims 1 to 5, the register perturbation device comprising a register pool and a perturbation generator, the register pool storing register information associated with one or more registers that can be safely accessed in the chip under test, the perturbation generator being connected to the register pool and the UVM register model, for selecting a target register that meets a register filtering rule from the register pool, and calling the UVM register model based on a calculated perturbation interval time and a selected operation mode to initiate a perturbative access operation to the target register in the selected chip under test; wherein the UVM register model is connected to the chip under test, and the operation mode comprises a write operation, a read operation, a read and write operation, and a write and read operation.

10. A chip verification device based on UVM, characterized in that: include: A memory for storing at least one computer program; as well as A processor, connected to the memory, is used to execute the at least one computer program to implement the UVM-based chip verification method as described in any one of claims 6 to 8.

11. A computer-readable storage medium, characterized in that: At least one computer program is stored, and when the computer program is executed by a processor, the UVM-based chip verification method as described in any one of claims 6 to 8 is implemented.

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