ADC sampling data output method, device and chip

Abstract

The present invention discloses an ADC sampling data output method, device and chip, the method comprising: after the ADC module completes periodic sampling, the sampling data obtained by sampling in the period is sent to a register; wherein the register is set in the ADC module; before the ADC module performs the next period of sampling, the register is controlled to select a universal input and output port, thereby obtaining a target universal input and output port, and the sampling data obtained by the periodic sampling is output to the target universal input and output port through the register; wherein the universal input and output ports are several. The present invention solves the technical problems of low accuracy and low efficiency of sampling data output in the prior art.

Description

Technical Field

[0001] The present invention relates to the field of ADC detection technology, and in particular to an ADC sampling data output method, device and chip. Background Art

[0002] Currently, many MCUs have ADC sampling modules, and the ADC sampling accuracy needs to be measured in real time, which requires the ADC sampling value to be output in real time. At present, the existing solution uses the ADC sampling value to be output on the GPIO pin, an external FPGA chip, and the GPIO pin level. At the same time, the ADC value needs to be output to the pin using software control. In this state, there is a limit on the ADC sampling rate.

[0003] When the ADC sampling rate is too high, the software controls the output of the ADC value to the GPIO pin. Since the chip under test needs to execute multiple statements such as detecting whether the sampling is completed, assigning the sampling value to the GPIO, clearing the sampling flag, and providing the sampling clock, when the ADC sampling rate is too high, the next sampling may be completed, but the previous ADC value has not been output, resulting in low accuracy of the sampled data output, which in turn leads to low accuracy of the real-time measurement sampling precision. The too low sampling rate leads to low efficiency of the sampled data output. Summary of the invention

[0004] The present invention provides a method, device, equipment and storage medium for measuring ADC sampling accuracy, so as to solve the technical problems of low accuracy and low efficiency of sampling data output in the prior art.

[0005] In order to solve the above technical problems, an embodiment of the present invention provides an ADC sampling data output method, comprising:

[0006] After the ADC module completes periodic sampling, the sampling data obtained during the periodic sampling is sent to a register; wherein the register is set in the ADC module;

[0007] Before the ADC module performs sampling in the next cycle, the register is controlled to select a universal input / output port, thereby obtaining a target universal input / output port, and the sampling data obtained by sampling in the cycle is output to the target universal input / output port through the register; wherein there are several universal input / output ports.

[0008] As a preferred solution, it also includes:

[0009] After the sampled data obtained by the periodic sampling is output to the target general purpose input / output port, the control enable bit of the register is kept at a high level, so that when the ADC module performs sampling in any subsequent period, the data obtained by the corresponding periodic sampling is output to the target general purpose input / output port.

[0010] As a preferred solution, after the ADC module completes periodic sampling, the sampled data obtained in the periodic sampling is sent to the register, specifically:

[0011] Control the channel that sends the sampled data to the register to be at a low level;

[0012] After the ADC module completes periodic sampling, the channel for sending the sampled data to the register is controlled to be at a high level, and the sampled data obtained by sampling in the period is sent to the register; wherein the duration of the channel for sending the sampled data to the register being at a high level is a fixed preset time;

[0013] Since the channel for controlling the sending of the sampled data to the register is at a high level, after the fixed preset time has passed, the channel for controlling the sending of the sampled data to the register is restored to a low level.

[0014] As a preferred solution, after the sampled data sampled in the period is sent to the register, the method further includes:

[0015] Controlling the clock bit of the register to be at a low level, and keeping the clock bit of the register at a low level for a fixed preset time;

[0016] Since the clock bit controlling the register is at a low level, after the fixed preset time has passed, the clock bit controlling the register is at a high level.

[0017] Accordingly, the present invention also provides an ADC sampling data output device, comprising: a sampling and sending module and a selection and output module;

[0018] The sampling and sending module is used to send the sampling data obtained by the periodic sampling to the register after the ADC module completes the periodic sampling; wherein the register is set in the ADC module;

[0019] The output selection module is used to control the register to select a general input / output port before the ADC module performs sampling in the next cycle, thereby obtaining a target general input / output port, and output the sampled data obtained by sampling in the cycle to the target general input / output port through the register; wherein there are several general input / output ports.

[0020] As a preferred solution, it also includes:

[0021] After the sampled data obtained by the periodic sampling is output to the target general purpose input / output port, the control enable bit of the register is kept at a high level, so that when the ADC module performs sampling in any subsequent period, the data obtained by the corresponding periodic sampling is output to the target general purpose input / output port.

[0022] As a preferred solution, after the ADC module completes periodic sampling, the sampled data obtained in the periodic sampling is sent to the register, specifically:

[0023] Control the channel that sends the sampled data to the register to be at a low level;

[0024] After the ADC module completes periodic sampling, the channel for sending the sampled data to the register is controlled to be at a high level, and the sampled data obtained by sampling in the period is sent to the register; wherein the duration of the channel for sending the sampled data to the register being at a high level is a fixed preset time;

[0025] Since the channel for controlling the sending of the sampled data to the register is at a high level, after the fixed preset time has passed, the channel for controlling the sending of the sampled data to the register is restored to a low level.

[0026] As a preferred solution, after the sampled data sampled in the period is sent to the register, the method further includes:

[0027] Controlling the clock bit of the register to be at a low level, and keeping the clock bit of the register at a low level for a fixed preset time;

[0028] Since the clock bit controlling the register is at a low level, after the fixed preset time has passed, the clock bit controlling the register is at a high level.

[0029] Accordingly, the present invention also provides a chip, comprising: an ADC module;

[0030] The ADC module is used to execute the ADC sampling data output method as described in any one of the above.

[0031] As a preferred solution, the ADC module includes a register, and the setting information of the register includes the control enable bit, the clock bit and the selection of the general input and output port.

[0032] Compared with the prior art, the embodiments of the present invention have the following beneficial effects:

[0033] The technical solution of the present invention ensures real-time update of data by sending the sampled data obtained by the ADC module in the periodic sampling to the register after the ADC module completes the periodic sampling, and periodically outputting the sampled data to the corresponding general input and output port through the register, so that the sampled data is immediately sent to the register after each period is completed, so that data processing can be carried out continuously, avoiding the need to execute multiple software control statements such as detecting whether the sampling is completed, assigning the sampled value to the GPIO, clearing the sampling flag, providing the sampling clock, etc., reducing delay, and when the ADC sampling rate is high, it can still ensure that the previous ADC sampling value can be output before the next sampling, avoiding the problem of not being able to output the sampled data in real time and accurately, and improving the output efficiency and accuracy of the sampled data. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 :It is a wiring diagram for real-time measurement of ADC sampling accuracy in the prior art;

[0035] Figure 2 : It is a schematic diagram of the software implementation flow of the chip under test in the prior art;

[0036] Figure 3 : A flow chart of the ADC sampling data output method provided by an embodiment of the present invention;

[0037] Figure 4 : A timing diagram of ADC sampling data output provided by an embodiment of the present invention;

[0038] Figure 5 : A structural diagram of an ADC sampling data output device provided in an embodiment of the present invention;

[0039] Figure 6 : A structural diagram of a chip provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0040] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0041] At present, the real-time measurement of ADC sampling accuracy is achieved by connecting the chip under test to an external test device (e.g., FPGA) so that the ADC sampling data is output to the pin of the GPIO (general purpose input and output port) (e.g., Figure 1 As shown), the FPGA is used to input the sampling data to measure the sampling accuracy of the chip under test.

[0042] However, the way in which ADC sampling data is output to the GPIO pin is mainly achieved through software control. Figure 2 As shown, it is necessary to judge whether the sampling is completed by continuous sampling and causing the clock pin of the chip under test to have a rising edge, and then read the sampled value in the register, obtain the sampled data and assign it to the GPIO register and then output it to the GPIO, so that the clock pin outputs a falling edge, and then clear the sampling completion flag to complete a complete process of outputting the sampled value to the GPIO. Since the chip under test needs to execute multiple statements such as detecting whether the sampling is completed, assigning the sampled value to the GPIO, clearing the sampling flag, and providing the sampling clock. At the same time, the sampled value after the ADC sampling is completed needs to be implemented in embedded software code, detecting the sampling completion flag, then reading the ADC FIFO value, and then assigning it to the GPIO register, which requires dozens of machine cycles. When the ADC sampling rate is too high, there will be a situation where the next sampling has been completed, but the previous ADC value has not been output.

[0043] Embodiment 1

[0044] Please refer to Figure 3 , an ADC sampling data output method provided by an embodiment of the present invention, which is used in an ADC module of a chip to be measured, comprises the following steps S101-S102:

[0045] Step S101: After the ADC module completes periodic sampling, the sampling data obtained in the periodic sampling is sent to a register; wherein the register is set in the ADC module;.

[0046] As a preferred solution of this embodiment, after the ADC module completes periodic sampling, the sampled data obtained in the periodic sampling is sent to the register, specifically:

[0047] The channel for sending the sampled data to the register is controlled to be at a low level; after the ADC module completes periodic sampling, the channel for sending the sampled data to the register is controlled to be at a high level, and the sampled data obtained by sampling in this period is sent to the register; wherein, the duration of the channel for sending the sampled data to the register being at a high level is a fixed preset time; since the channel for sending the sampled data to the register is controlled to be at a high level, after the fixed preset time has passed, the channel for sending the sampled data to the register is controlled to return to a low level.

[0048] In this example, see Figure 4, which is a timing diagram of the ADC sampling data output provided by the embodiment of the present invention. When the ADC module sampling is not completed, the channel that sends the sampled data to the register is continuously at a low level. Once the sampling completion flag appears, it means that the data of the current cycle of the ADC module has been sampled, that is, the data collected in the current cycle can be sent to the register, and the register uses the first-in-first-out (FIFO, First In First Out) logic to further output the sampled data to the corresponding general input and output port (GPIO).

[0049] It should be noted that the duration of the high level of the channel that sends the sampled data to the register is a fixed preset time, which can preferably be set according to actual needs. Within the fixed preset time, the ADC module can completely output the sampled data to the GPIO through the register. After the fixed preset time, it is necessary to control the channel that sends the sampled data to the register to return to a low level to indicate that the ADC module performs data sampling for the next cycle.

[0050] As a preferred solution of this embodiment, after the sampled data obtained by sampling in the period is sent to the register, the following is further included:

[0051] The clock bit of the register is controlled to be at a low level, and the time for which the clock bit of the register is kept at a low level is a fixed preset time; after the fixed preset time has passed since the clock bit of the register is controlled to be at a low level, the clock bit of the register is controlled to be at a high level.

[0052] In this embodiment, after the sampled data obtained by the periodic sampling is sent to the register, the register provides the selection of the CLK (clock) pin, which is then used as a clock bit and output to the external test equipment. CLK controls enable and disable. When sampling is completed, the chip fixed pin outputs the falling edge. In this stage, the register and the external test equipment perform the sampled data output of this cycle or the previous cycle, and the time maintained during the entire stage of the register and the external test equipment performing the sampled data output is a fixed preset time, which is the same as the time maintained by the data sampling. At the same time, since the register sends the sampled data read by the cycle, through the selection of the general input and output port GPIO, to the final output, there is a time difference in the chip hardware processing in the middle, so the appearance of the CLK clock falling edge is later than the time when the flag mark appears when the sampling is completed.

[0053] Step S102: before the ADC module executes sampling of the next cycle, the register is controlled to select a universal input / output port, thereby obtaining a target universal input / output port, and the sampling data obtained by sampling the cycle is output to the target universal input / output port through the register; wherein there are several universal input / output ports.

[0054] In this embodiment, before the ADC module executes the sampling of the next cycle, in order to ensure that the sampled data of the previous cycle can be sent out, it is necessary to select a general input and output port, and there are several general input and output ports. Preferably, the setting information name of the register corresponding to the selection of the general input and output port can be ADC_GPIO_PORT, and the GPIO port selection of the ADC sampled data output can include: 00: GPIOA, 01: GPIOB, 10: GPIOC and 11: GPIOD. Due to the implementation of the PORT selector. It can be understood that the PORT selector has two pins, which are respectively connected to the bit0 end and the bit1 end. For example, when the bit0 end and the bit1 end output 00 together, it means that the sampled data of this cycle needs to be output to GPIOA; when the bit0 end and the bit1 end output 10 together, it means that the sampled data of this cycle needs to be output to GPIOC.

[0055] Preferably, the register setting information can be set according to the following Table 1.

[0056]

[0057] Table 1

[0058] As a preferred solution of this embodiment, it also includes:

[0059] After the sampled data obtained by the periodic sampling is output to the target general purpose input / output port, the control enable bit of the register is kept at a high level, so that when the ADC module performs sampling in any subsequent period, the data obtained by the corresponding periodic sampling is output to the target general purpose input / output port.

[0060] In this embodiment, after the sampled data obtained by sampling in the waiting period is output to the target general purpose input and output port, in order to ensure that the PORT selector continues to work, that is, the ADC module continues to sample data, and then by keeping the control enable bit of the register at a high level, it is ensured that there is a corresponding GPIO, and the sampled data can be output accordingly.

[0061] It can be understood that the output of ADC sampled data to the GPIO pin in the embodiment of the present invention is a hardware behavior of the chip, that is, a hardware execution behavior of the ADC module, and the corresponding sampled data output function can be realized through the level signal of its pin without the need for software control and intervention of an external processor, and the ADC module has the function of outputting sampled data to the GPIO. After the ADC module completes data sampling, the data is transmitted to the GPIO pin in the next clock cycle, wherein only one clock cycle is required at most.

[0062] In this embodiment, in the method for testing the sampling accuracy of the chip ADC, when the ADC module completes sampling, the sampled data is connected to the GPIO pin, and CLK is provided at the same time for the external test equipment to sample the data. The register in the chip to be tested provides an enable bit, a GPIO PORT selection bit, and a CLK pin selection. Through register control, select the GPIO port, such as GPIOB; select the CLK pin, such as PA11; control the enable bit to enable the ADC value (sampled data) output GPIO function. After the register setting is completed, the chip to be tested enables continuous sampling, and the ADC sampling value is output to the GPIO.

[0063] Implementing the above embodiments has the following effects:

[0064] The technical solution of the present invention ensures real-time update of data by sending the sampled data obtained by the ADC module in the periodic sampling to the register after the ADC module completes the periodic sampling, and periodically outputting the sampled data to the corresponding general input and output port through the register, so that the sampled data is immediately sent to the register after each period is completed, so that data processing can be carried out continuously, avoiding the need to execute multiple software control statements such as detecting whether the sampling is completed, assigning the sampled value to the GPIO, clearing the sampling flag, providing the sampling clock, etc., reducing delay, and when the ADC sampling rate is high, it can still ensure that the previous ADC sampling value can be output before the next sampling, avoiding the problem of not being able to output the sampled data in real time and accurately, and improving the output efficiency and accuracy of the sampled data.

[0065] Embodiment 2

[0066] See also Figure 5 , which is an ADC sampling data output device provided by the present invention, comprising: a sampling sending module 201 and a selection output module 202;

[0067] The sampling and sending module 201 is used to send the sampling data obtained by the periodic sampling to the register after the ADC module completes the periodic sampling; wherein the register is set in the ADC module;

[0068] The output selection module 202 is used to control the register to select a general input / output port before the ADC module performs sampling in the next cycle, thereby obtaining a target general input / output port, and output the sampled data obtained by sampling in the cycle to the target general input / output port through the register; wherein there are several general input / output ports.

[0069] As a preferred solution, it also includes:

[0070] After the sampled data obtained by the periodic sampling is output to the target general purpose input / output port, the control enable bit of the register is kept at a high level, so that when the ADC module performs sampling in any subsequent period, the data obtained by the corresponding periodic sampling is output to the target general purpose input / output port.

[0071] As a preferred solution, after the ADC module completes periodic sampling, the sampled data obtained in the periodic sampling is sent to the register, specifically:

[0072] Control the channel that sends the sampled data to the register to be at a low level;

[0073] After the ADC module completes periodic sampling, the channel for sending the sampled data to the register is controlled to be at a high level, and the sampled data obtained by sampling in the period is sent to the register; wherein the duration of the channel for sending the sampled data to the register being at a high level is a fixed preset time;

[0074] Since the channel for controlling the sending of the sampled data to the register is at a high level, after the fixed preset time has passed, the channel for controlling the sending of the sampled data to the register is restored to a low level.

[0075] As a preferred solution, after the sampled data sampled in the period is sent to the register, the method further includes:

[0076] Controlling the clock bit of the register to be at a low level, and keeping the clock bit of the register at a low level for a fixed preset time;

[0077] Since the clock bit controlling the register is at a low level, after the fixed preset time has passed, the clock bit controlling the register is at a high level.

[0078] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the device described above can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here.

[0079] Implementing the above embodiments has the following effects:

[0080] The technical solution of the present invention ensures real-time update of data by sending the sampled data obtained by the ADC module in the periodic sampling to the register after the ADC module completes the periodic sampling, and periodically outputting the sampled data to the corresponding general input and output port through the register, so that the sampled data is immediately sent to the register after each period is completed, so that data processing can be carried out continuously, avoiding the need to execute multiple software control statements such as detecting whether the sampling is completed, assigning the sampled value to the GPIO, clearing the sampling flag, providing the sampling clock, etc., reducing delay, and when the ADC sampling rate is high, it can still ensure that the previous ADC sampling value can be output before the next sampling, avoiding the problem of not being able to output the sampled data in real time and accurately, and improving the output efficiency and accuracy of the sampled data.

[0081] Embodiment 3

[0082] See also Figure 6 , which is a chip provided by the present invention. The present invention also provides a chip, including: an ADC module.

[0083] The ADC module is used to execute the ADC sampling data output method described in the first embodiment above.

[0084] As a preferred solution of this embodiment, the ADC module includes a register, and the setting information of the register includes the control enable bit, the clock bit and the selection of the general input and output port.

[0085] In this embodiment, the register further includes a PORT selector, and the PORT selector is connected to a plurality of general purpose input and output ports (GPIOs) so that the register can output corresponding sampled data to corresponding GPIOs.

[0086] It should be noted that the register is an ADC FIFO register, which is a register for ADC values ​​that executes a first-in, first-out logic.

[0087] Implementing the above embodiments has the following effects:

[0088] The technical solution of the present invention ensures real-time update of data by sending the sampled data obtained by the ADC module in the periodic sampling to the register after the ADC module completes the periodic sampling, and periodically outputting the sampled data to the corresponding general input and output port through the register, so that the sampled data is immediately sent to the register after each period is completed, so that data processing can be carried out continuously, avoiding the need to execute multiple software control statements such as detecting whether the sampling is completed, assigning the sampled value to the GPIO, clearing the sampling flag, providing the sampling clock, etc., reducing delay, and when the ADC sampling rate is high, it can still ensure that the previous ADC sampling value can be output before the next sampling, avoiding the problem of not being able to output the sampled data in real time and accurately, and improving the output efficiency and accuracy of the sampled data.

[0089] The specific embodiments described above further illustrate the purpose, technical solutions and beneficial effects of the present invention. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. It is particularly pointed out that for those skilled in the art, any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the scope of protection of the present invention.

Claims

1. An ADC sampling data output method, characterized in that: include: After the ADC module completes periodic sampling, the sampling data obtained during the periodic sampling is sent to a register; wherein the register is set in the ADC module; Before the ADC module performs sampling in the next cycle, the register is controlled to select a universal input / output port, thereby obtaining a target universal input / output port, and the sampled data obtained by sampling in the cycle is output to the target universal input / output port through the register; wherein there are several universal input / output ports; After the sampled data obtained by the periodic sampling is output to the target general purpose input / output port, the control enable bit of the register is kept at a high level, so that when the ADC module performs sampling in any subsequent period, the data obtained by the corresponding periodic sampling is output to the target general purpose input / output port.

2. The ADC sampling data output method according to claim 1, characterized in that: After the ADC module completes periodic sampling, the sampled data obtained during the periodic sampling is sent to the register, specifically: Control the channel that sends the sampled data to the register to be at a low level; After the ADC module completes periodic sampling, the channel for sending the sampled data to the register is controlled to be at a high level, and the sampled data obtained by sampling in the period is sent to the register; wherein the duration of the channel for sending the sampled data to the register being at a high level is a fixed preset time; Since the channel for controlling the sending of the sampled data to the register is at a high level, after the fixed preset time has passed, the channel for controlling the sending of the sampled data to the register is restored to a low level.

3. The ADC sampling data output method according to claim 2, characterized in that: After the sampled data sampled in the cycle is sent to the register, it also includes: Controlling the clock bit of the register to be at a low level, and keeping the clock bit of the register at a low level for a fixed preset time; Since the clock bit controlling the register is at a low level, after the fixed preset time has passed, the clock bit controlling the register is at a high level.

4. An ADC sampling data output device, characterized in that: include: Sampling sending module and selecting output module; The sampling and sending module is used to send the sampling data obtained by the periodic sampling to the register after the ADC module completes the periodic sampling; wherein the register is set in the ADC module; The output selection module is used to control the register to select the general input and output port before the ADC module executes the sampling of the next cycle, thereby obtaining the target general input and output port, and output the sampled data obtained by the sampling of the cycle to the target general input and output port through the register; wherein, there are several general input and output ports; and is also used to keep the control enable bit of the register at a high level after the sampled data obtained by the sampling of the cycle is output to the target general input and output port, so that when the ADC module executes the sampling of any cycle subsequently, the data obtained by the sampling of the corresponding cycle is output to the target general input and output port.

5. The ADC sampling data output device according to claim 4, characterized in that: After the ADC module completes periodic sampling, the sampled data obtained during the periodic sampling is sent to the register, specifically: Control the channel that sends the sampled data to the register to be at a low level; After the ADC module completes periodic sampling, the channel for sending the sampled data to the register is controlled to be at a high level, and the sampled data obtained by sampling in the period is sent to the register; wherein the duration of the channel for sending the sampled data to the register being at a high level is a fixed preset time; Since the channel for controlling the sending of the sampled data to the register is at a high level, after the fixed preset time has passed, the channel for controlling the sending of the sampled data to the register is restored to a low level.

6. The ADC sampling data output device according to claim 5, characterized in that: After the sampled data sampled in the cycle is sent to the register, it also includes: Controlling the clock bit of the register to be at a low level, and keeping the clock bit of the register at a low level for a fixed preset time; Since the clock bit controlling the register is at a low level, after the fixed preset time has passed, the clock bit controlling the register is at a high level.

7. A chip, characterized in that: include: ADC module; The ADC module is used to execute the ADC sampling data output method according to any one of claims 1 to 3.

8. A chip as claimed in claim 7, characterized in that: The ADC module includes a register, and setting information of the register includes a control enable bit, a clock bit, and selection of a general input and output port.

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