Shared amplifier circuit and pipeline analog-to-digital converter using the same

Abstract

The present invention discloses a circuit of a shared amplifier and a pipeline analog-to-digital converter using the circuit, wherein the circuit of the shared amplifier includes: an op amp unit, which includes an op amp input stage circuit and an op amp post-stage circuit; a comparator unit, which includes a comparator pre-amplifier stage circuit and a latch circuit; a differential amplifier, whose output end is respectively connected to the op amp post-stage circuit and the latch circuit through a switch, and whose input end is respectively connected to the op amp signal input circuit and the comparator signal input circuit through a switch, and the differential amplifier can be switchably connected to the op amp input stage circuit or the comparator pre-amplifier stage circuit. The circuit of this shared amplifier overcomes the problems of aperture error between signal paths of the existing pipeline analog-to-digital converter, large layout area occupied by the stage circuit, high power consumption, large parasitic capacitance, etc., and the aperture error is completely eliminated by time-division multiplexing the same differential amplifier, and the power consumption, layout area and parasitic capacitance of the stage circuit can be effectively reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a circuit of a shared amplifier and a pipeline analog-to-digital converter using the circuit. Background Art

[0002] An analog-to-digital converter is an electronic device that converts an input analog signal into a digital signal. A common pipeline analog-to-digital converter is composed of multiple analog-to-digital conversion stage circuits with similar structures. The performance of the stage circuit will affect the conversion efficiency, conversion accuracy and other indicators of the analog-to-digital converter. Most instrument circuits have very high requirements on the conversion effect of the analog-to-digital converter.

[0003] In the prior art, in order to eliminate the power consumption, noise and nonlinear distortion introduced by the sample-and-hold amplifier, the pipeline analog-to-digital converter usually adopts the non-sample-and-hold technology. Since there is a mismatch in the time constant of the signal path between the sub-ADC and the MDAC in the pipeline stage circuit, a larger aperture error will be introduced as the input frequency increases, thereby reducing the performance of the pipeline analog-to-digital converter. Figure 3 As shown in the prior art, a pipeline circuit sampling network using a passive RC sampling network is used. The sub-ADC and MDAC sampling paths use the same type of RC network, so a better match can be achieved. The MDAC sampling path consists of a MOS sampling switch and a sampling capacitor C S The sub-ADC sampling path consists of a MOS sampling switch and a sampling capacitor C COMP The two devices are of the same type and therefore have similar time constants. However, after chip processing, the two sampling paths are prone to mismatch. It is necessary to adjust the sub-ADC sampling time to improve the performance of the pipelined analog-to-digital converter, which increases the complexity of factory calibration and cannot guarantee complete calibration. Mismatch may occur again after calibration. Figure 4 As shown, a pipeline stage circuit sampling network in the prior art that merges the sub-ADC and MDAC sampling paths merges the sub-ADC and MDAC sampling paths in order to reduce aperture error. However, in order to meet the high-frequency signal input, a pre-amplification stage using multiple comparators requires greater power consumption and layout area. In addition, the first-stage circuit uses more comparators, which introduces a larger parasitic capacitance on the layout, reduces the feedback coefficient of the MDAC, and further deteriorates the performance of the pipelined analog-to-digital converter. Summary of the invention

[0004] The present invention overcomes the problems of aperture error between sub-ADC and MDAC signal paths of the existing pipeline analog-to-digital converter, large layout area occupied by the stage circuit, high power consumption, large parasitic capacitance, etc., and provides a shared amplifier circuit and a pipeline analog-to-digital converter using the circuit, wherein the shared amplifier circuit performs time-division multiplexing on the same differential amplifier, connects the differential amplifier to the comparator pre-amplification stage circuit during the comparison phase, and connects the differential amplifier to the operational amplifier input stage circuit during the amplification phase, so that the time constants of the sub-ADC and MDAC signal paths are kept in a matching state, the aperture error is completely eliminated, and the power consumption, layout area and parasitic capacitance of the stage circuit can be effectively reduced.

[0005] In order to achieve the above object, the present invention adopts the following scheme:

[0006] A shared amplifier circuit comprising:

[0007] An operational amplifier unit, comprising an operational amplifier input stage circuit and an operational amplifier post-stage circuit;

[0008] A comparator unit, comprising a comparator pre-amplifier stage circuit and a latch circuit;

[0009] A differential amplifier, whose output end is connected to the operational amplifier post-stage circuit and the latch circuit respectively through a switch, and whose input end is connected to the operational amplifier signal input circuit and the comparator signal input circuit respectively through a switch, and the differential amplifier can be switchably connected to the operational amplifier input stage circuit or the comparator pre-amplifier stage circuit;

[0010] The differential amplifier includes a P-terminal input transistor M1, an N-terminal input transistor M2, a current mirror load M3, a current mirror load M4 and a current mirror transistor MC. The input signals IP and IN are respectively connected to the G-terminals of M1 and M2 for signal amplification. The D-terminals of M1 and M2 are respectively connected to the first-stage N-phase output signal ON1 and the first-stage P-phase output signal OP1 to provide a differential output voltage. The S-terminals of M1 and M2 are connected to the D-terminal of MC to form a differential input tube structure. The G-terminal of MC is connected to the current mirror bias voltage VBN. The D-terminals of M3 and M4 are respectively connected to ON1. and OP1 to generate a differential output voltage. The G terminals of M3 and M4 are connected to a common-mode feedback signal line VCMFB for adjusting the output common-mode voltage. OP1 and ON1 are also respectively connected to a pseudo-differential P-terminal input transistor M5 and a pseudo-differential N-terminal input transistor M6 for converting the first-stage output voltage signals ON1 and OP1 into current signals. The current signals converted by M5 and M6 are divided into two outputs, one of which is connected to the post-stage circuit of the operational amplifier through a switch to further amplify the input signal, and the other is connected to the latch circuit through a switch to generate a comparator output digital code.

[0011] Preferably, the operational amplifier signal input circuit and the comparator signal input circuit both include the same capacitive DAC, the output of the capacitive DAC is connected to the input of the differential amplifier, and the input of the capacitive DAC is connected to V providing the ADC reference common mode voltage. CM pin, forming part of the comparator signal input circuit; the input end of the capacitive DAC is also connected to V which provides the ADC reference voltage RP pin and V RN Pin, constituting a part of the operational amplifier signal input circuit.

[0012] Preferably, the differential amplifier adopts a differential common-source amplifier structure with a current mirror as a load, and the output common-mode voltage of the operational amplifier post-stage circuit is adjusted by a common-mode feedback circuit.

[0013] Preferably, the operational amplifier post-stage circuit adopts a pseudo-differential sleeve structure, and the operational amplifier post-stage circuit includes an NMOS common-gate tube, and the NMOS common-gate tube is connected to the current mirror bias voltage VBN through a switch.

[0014] The present application also provides a pipeline analog-to-digital converter, which is composed of multiple stage circuit unit modules, wherein the stage circuit unit module includes a sampling unit and a shared amplifier circuit as described in any of the above schemes, wherein the sampling unit is used to sample the signal to be converted and the comparator threshold, and the output end of the sampling unit is connected to the input end of the differential amplifier, and the differential amplifier input ends of two adjacent stage circuit unit modules are connected through an inter-stage switch, and the inter-stage switch is closed when the stage circuit unit module is in the amplification phase.

[0015] Preferably, the operational amplifier signal input circuit and the comparator signal input circuit both include the same capacitive DAC, the output of the capacitive DAC is connected to the input of the differential amplifier, and the input of the capacitive DAC is connected to V providing the ADC reference common mode voltage. CM pin, forming part of the comparator signal input circuit; the input end of the capacitive DAC is also connected to V which provides the ADC reference voltage RP pin and V RN The pins constitute a part of the operational amplifier signal input circuit, the sampling unit comprises a parallel-connected signal sampling circuit to be converted and a comparator threshold sampling circuit, the signal sampling circuit to be converted comprises a sampling capacitor Cs connected between the input signal source and the differential amplifier input terminal, the comparator threshold sampling circuit comprises the capacitive DAC and a V connected to its input terminal for providing a comparator threshold voltage TH Pin.

[0016] The present invention includes at least the following beneficial effects: (1) the operational amplifier input stage circuit and the comparator prevention large stage circuit share a differential amplifier and use the same time constant, which completely eliminates the aperture error and ensures the stable performance of the analog-to-digital converter; (2) through circuit sharing, fewer components are used to achieve complete circuit functions, which improves the utilization rate of components and reduces the overall power consumption and occupied layout area of ​​the circuit; (3) the number of components is small, the circuit is easy to arrange, and the parasitic capacitance can be effectively reduced, so that the conversion accuracy of the pipeline analog-to-digital converter is higher. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 A schematic diagram of the structural principle of a shared amplifier circuit provided by the present invention;

[0018] Figure 2 A schematic diagram of a circuit structure of a pipeline analog-to-digital converter of the present invention;

[0019] Figure 3 A schematic diagram of a sampling network of a stage circuit of an existing pipeline analog-to-digital converter;

[0020] Figure 4 The schematic diagram is a sampling network diagram of another existing pipeline analog-to-digital converter stage circuit. DETAILED DESCRIPTION

[0021] The present invention is further described in detail below in conjunction with the accompanying drawings so that those skilled in the art can implement the invention with reference to the description.

[0022] like Figure 1-2 As shown, the circuit of the shared amplifier provided by the present invention comprises:

[0023] The operational amplifier unit includes an operational amplifier input stage circuit and an operational amplifier post-stage circuit; Figure 1 As shown, the entire operational amplifier unit OTA consists of an operational amplifier input stage circuit OTA Part I and an operational amplifier post-stage circuit OTA Part II connected front and back, which are used to amplify the residual voltage in the circuit during the amplification phase.

[0024] A comparator unit, comprising a comparator pre-amplifier circuit and a latch circuit; Figure 1 As shown in the figure, the complete comparator unit consists of a comparator pre-amplifier circuit Comp.Pre-amp and a latch circuit Latch connected front and back, which generates a comparator output digital code Do for amplifying the phase when comparing the phase. The latch circuit Latch is a level-triggered storage unit. The data storage action depends on the level value of the input clock or enable signal. Only when the latch is in the enabled state, the output will change with the data input.

[0025] The differential amplifier has an output end connected to the operational amplifier post-stage circuit and the latch circuit through a switch, and an input end connected to the operational amplifier signal input circuit and the comparator signal input circuit through a switch, and the differential amplifier can be switchably connected to the operational amplifier input stage circuit or the comparator pre-amplifier stage circuit. Figure 1 As shown, the multiple switches connected to the input and output of the differential amplifier are divided into a comparison phase switch group CK2a and an amplification phase switch group CK2b. The two switch groups are used to control the access state of the differential amplifier. The comparison phase switch group CK2a includes switches SW5 and SW8, wherein the input of the differential comparator is connected to the capacitor Cdac and then connected to the ADC reference common mode voltage VCM pin through switch SW5, and the output of the differential comparator is connected to the latch circuit Latch through switch SW8. When all the switches in the comparison phase switch group CK2a are closed, the pipeline analog-to-digital converter is in the comparison phase state, and the comparator unit of its stage circuit compares the input signal to obtain the output digital code Do signal. The amplification phase switch group CK2b includes switches SW6, SW7 and SW9, wherein the output of the differential comparator is connected to the operational amplifier post-stage circuit OTA Part II through switch SW9, and the input of the differential amplifier is connected to the capacitor Cdac and then selectively connected to V through switch SW6. RP pin or V RN The pin of switch SW6 is controlled by the Do signal. Switch SW7 is used to connect the input of the differential amplifier of the upper and lower circuits. When the switches of the amplification phase switch group CK2b are all closed, the pipeline analog-to-digital converter is in the amplification phase state, and the operational amplifier unit of the stage circuit amplifies the residual voltage. By controlling the opening or closing of the front and rear end switches of the differential amplifier, the same differential amplifier can be quickly switched between the comparator unit and the operational amplifier unit, and the differential amplifier can work stably and continuously in the comparison phase and amplification phase of the analog-to-digital converter.

[0026] The circuit operates in a pipeline analog-to-digital converter. During the sampling phase, the input signal is sampled using a common signal sampling circuit. The sampling capacitor Cdac is used to sample the comparator threshold V TH For sampling, the summing node sn at the input of the differential amplifier is connected to the op amp input common mode voltage V CMI In the comparison phase, the comparison phase switch group CK2a is closed, the differential amplifier is switched to the comparator preamplifier circuit, connected to the latch circuit Latch of the subsequent stage, and the sampling capacitor Cdac is connected to V CM level, the comparator unit completes the comparison between the input signal and the comparator threshold V TH The comparison is performed to obtain the output digital code Do signal; in the amplification phase, the amplification phase switch group CK2b is closed, wherein the switch SW6 selects to connect V according to the Do signal. RP or V RN, the differential amplifier switches to the op amp input stage circuit, which is connected to the op amp post-stage circuit to amplify the residual voltage, and the switch SW7 connects the op amp input stage circuits of all stage circuit units in parallel.

[0027] In this circuit, the op amp input stage circuit and the comparator pre-amplifier stage circuit share a differential amplifier, merge the two sampling paths of the two states, use the same time constant, completely eliminate the aperture error, and ensure the stable and reliable performance of the analog-to-digital converter; a differential amplifier is connected to different lines under the control of a switch, and switches between different working states, realizing circuit sharing, and the complete circuit function can be realized with fewer components. Compared with the intermittent operation of two differential amplifiers, the continuous operation of a single differential amplifier improves the utilization rate of components, reduces the overall power consumption of the circuit and the occupied layout area, and is more suitable for designing small-size and low-energy pipeline analog-to-digital converters; through the merging of sampling paths and the reuse of circuits, the number of components used is small, the circuit arrangement method is more flexible, the circuit layout is easier to adjust and optimize, and the parasitic capacitance in the circuit can be effectively reduced, so that the conversion accuracy of the pipeline analog-to-digital converter is higher.

[0028] It should be noted that Figure 1-2 SW1_1, SW2_1, Latch_1, etc. represent the marks of components or connection nodes, and the underscore plus number format in the suffix part is used to distinguish the circuits at each level. In the description of the embodiments, it is obvious that the marking formats such as SW1, SW2, Latch, etc. are simplified general expressions applicable to circuits at each level.

[0029] In another technical solution, Figure 1 As shown, the operational amplifier signal input circuit and the comparator signal input circuit both include the same capacitive DAC, the output end of the capacitive DAC is connected to the input end of the differential amplifier, and the input end of the capacitive DAC is connected to V that provides the ADC reference common mode voltage. CM pin, forming part of the comparator signal input circuit; the input end of the capacitive DAC is also connected to V which provides the ADC reference voltage RP pin and V RN Pin, constituting a part of the operational amplifier signal input circuit. Figure 1 The Cdac in the figure is the capacitive DAC, which is connected to each reference voltage pin through a switch, and samples and converts the reference voltage to realize the input of the comparison signal. TH The switch SW4 is connected to the bottom plate of Cdac to complete the sampling of the comparator threshold voltage signal; V CM The switch SW5 is connected to the bottom plate of Cdac to determine the bottom plate voltage of Cdac during the phase comparison; V RP and VRN Through SW6, the bottom plate voltage of Cdac is determined during the amplification phase to generate a residual voltage. The signal source in the comparator signal input circuit includes the signal to be converted V I , comparator threshold voltage V TH and ADC reference voltage V CM The signal source of the op amp input circuit includes the signal to be converted V I ,ADC reference voltage V RP and ADC reference voltage V RN .

[0030] In another technical solution, the differential amplifier adopts a differential common source amplifier structure with a current mirror as a load, and the output common mode voltage of the operational amplifier rear circuit is adjusted by a common mode feedback circuit. The common mode feedback circuit compares the input signal and outputs a signal proportional to the input signal to correct and adjust the output common mode voltage value of the operational amplifier rear circuit.

[0031] The operational amplifier back-stage circuit adopts a pseudo-differential sleeve structure, and the operational amplifier back-stage circuit includes an NMOS common-gate tube, and the NMOS common-gate tube is connected to the current mirror bias voltage VBN through a switch. The operational amplifier back-stage circuit adopts a pseudo-differential sleeve structure, which can achieve a large output gain with low energy consumption, and the working state is stable and reliable.

[0032] In another technical solution, Figure 2 As shown, the differential amplifier includes a P-terminal input transistor M1, an N-terminal input transistor M2, a current mirror load M3, a current mirror load M4 and a current mirror transistor MC, the input signals IP and IN are respectively connected to the G-terminals of M1 and M2 for signal amplification, the D-terminals of M1 and M2 are respectively connected to the first-stage N-phase output signal ON1 and the first-stage P-phase output signal OP1 to provide a differential output voltage, the S-terminals of M1 and M2 are connected to the D-terminal of MC to form a differential input tube structure, the G-terminal of MC is connected to the current mirror bias voltage VBN, and the D-terminals of M3 and M4 are respectively connected to ON 1 and OP1, generate a differential output voltage, the G terminals of M3 and M4 are connected to a common-mode feedback signal line VCMFB for adjusting the output common-mode voltage, OP1 and ON1 are also respectively connected to a pseudo-differential P-terminal input transistor M5 and a pseudo-differential N-terminal input transistor M6 for converting the first-stage output voltage signals ON1 and OP1 into current signals, and the current signals converted by M5 and M6 are divided into two outputs, one of which is connected to the post-stage circuit of the operational amplifier through a switch to further amplify the input signal, and the other is connected to the latch circuit through a switch to generate a comparator output digital code.

[0033] The present application also provides a pipeline analog-to-digital converter, which is composed of multiple stage circuit unit modules, wherein the stage circuit unit module includes a sampling unit and a shared amplifier circuit as described in any of the above schemes, wherein the sampling unit is used to sample the signal to be converted and the comparator threshold, and the output end of the sampling unit is connected to the input end of the differential amplifier, and the differential amplifier input ends of two adjacent stage circuit unit modules are connected through an inter-stage switch, and the inter-stage switch is closed when the stage circuit unit module is in the amplification phase.

[0034] During the operation cycle of analog-to-digital conversion using this pipeline analog-to-digital converter, in the sampling phase, the sampling unit samples the input signal to be converted, and samples the comparator threshold of the comparator unit and the reference voltage of the operational amplifier unit; in the comparison phase, the differential amplifier is switched to the comparator pre-amplification stage circuit by adjusting the front and rear connection relationship, and connected with the latch circuit of the rear stage to form a normally operating comparator unit, and the comparator unit completes the comparison of the input signal and the comparator threshold to obtain the comparator output digital code Do signal; in the amplification phase, the connection relationship between the front and rear end circuits of the differential amplifier is adjusted according to the Do signal value, the differential amplifier is switched to the operational amplifier input stage circuit, and connected with the operational amplifier rear stage circuit to form a complete operational amplifier unit, and the residual voltage is amplified. At the same time, the inter-stage switch is closed to connect the operational amplifier input stage circuits of all stage circuit unit modules in parallel.

[0035] The operational amplifier unit and the comparator unit in the same level circuit of this pipeline digital-to-analog converter share a differential amplifier, merge the two sampling paths, and use the same time constant for the two signal paths, completely eliminating the aperture error and ensuring the stable and reliable performance of the analog-to-digital converter; a differential amplifier is connected to different lines under the control of a switch and switches between different working states, realizing the sharing of key circuit parts, and the complete circuit function can be achieved with fewer components. The continuous operation of a single differential amplifier improves the utilization rate of components compared to the intermittent operation of two differential amplifiers, reduces the overall power consumption of the circuit and the occupied layout area, so this pipeline analog-to-digital converter has the advantages of smaller size and lower energy consumption, and can improve the integration of equipment components; by merging sampling paths and reusing key circuits, the number of components used is small, the circuit layout is more flexible, and the circuit layout is easier to adjust and optimize, which can effectively reduce the parasitic capacitance in the circuit, so that the conversion accuracy of the pipeline analog-to-digital converter is higher and more in line with production needs.

[0036] Preferably, the sampling unit comprises a to-be-converted signal sampling circuit and a comparator threshold sampling circuit connected in parallel, wherein the to-be-converted signal sampling circuit comprises a sampling capacitor C connected between an input signal source and an input terminal of a differential amplifier. S The comparator threshold sampling circuit includes the capacitive DAC and a V connected to its input terminal for providing a comparator threshold voltage.TH Pin.

[0037] It should be noted that the number of devices and processing scale described here are used to simplify the description of the present invention, and the application, modification and variation of the present invention are obvious to those skilled in the art.

[0038] Although the embodiments of the present invention have been disclosed as above, they are not limited to the applications listed in the specification and the implementation modes, and they can be fully applied to various fields suitable for the present invention. For those familiar with the art, additional modifications can be easily implemented. Therefore, without departing from the general concept defined by the claims and the scope of equivalents, the present invention is not limited to the specific details and the illustrations shown and described herein.

Claims

1. A shared amplifier circuit, characterized in that include: An operational amplifier unit, comprising an operational amplifier input stage circuit and an operational amplifier post-stage circuit; A comparator unit, comprising a comparator pre-amplifier stage circuit and a latch circuit; A differential amplifier, whose output end is connected to the operational amplifier post-stage circuit and the latch circuit respectively through a switch, and whose input end is connected to the operational amplifier signal input circuit and the comparator signal input circuit respectively through a switch, and the differential amplifier can be switchably connected to the operational amplifier input stage circuit or the comparator pre-amplifier stage circuit; The differential amplifier includes a P-terminal input transistor M1, an N-terminal input transistor M2, a current mirror load M3, a current mirror load M4 and a current mirror transistor MC. The input signals IP and IN are respectively connected to the G-terminals of M1 and M2 for signal amplification. The D-terminals of M1 and M2 are respectively connected to the first-stage N-phase output signal ON1 and the first-stage P-phase output signal OP1 to provide a differential output voltage. The S-terminals of M1 and M2 are connected to the D-terminal of MC to form a differential input tube structure. The G-terminal of MC is connected to the current mirror bias voltage VBN. The D-terminals of M3 and M4 are respectively connected to ON1. and OP1 to generate a differential output voltage. The G terminals of M3 and M4 are connected to a common-mode feedback signal line VCMFB for adjusting the output common-mode voltage. OP1 and ON1 are also respectively connected to a pseudo-differential P-terminal input transistor M5 and a pseudo-differential N-terminal input transistor M6 for converting the first-stage output voltage signals ON1 and OP1 into current signals. The current signals converted by M5 and M6 are divided into two outputs, one of which is connected to the post-stage circuit of the operational amplifier through a switch to further amplify the input signal, and the other is connected to the latch circuit through a switch to generate a comparator output digital code.

2. The shared amplifier circuit according to claim 1, characterized in that: The operational amplifier signal input circuit and the comparator signal input circuit both include the same capacitive DAC, the output of the capacitive DAC is connected to the input of the differential amplifier, and the input of the capacitive DAC is connected to V that provides the ADC reference common mode voltage. CM pin, forming part of the comparator signal input circuit; the input end of the capacitive DAC is also connected to V which provides the ADC reference voltage RP pin and V RN Pin, constituting a part of the operational amplifier signal input circuit.

3. The shared amplifier circuit according to claim 1, characterized in that: The differential amplifier adopts a differential common-source amplifier structure with a current mirror as a load, and the output common-mode voltage of the operational amplifier rear-stage circuit is adjusted through the action of a common-mode feedback circuit.

4. The shared amplifier circuit according to claim 1, characterized in that: The operational amplifier back-end circuit adopts a pseudo-differential sleeve structure, and the operational amplifier back-end circuit includes an NMOS common-gate tube, and the NMOS common-gate tube is connected to a current mirror bias voltage VBN through a switch.

5. A pipeline analog-to-digital converter, consisting of a plurality of stage circuit unit modules, characterized in that: The stage circuit unit module includes a sampling unit and a shared amplifier circuit as described in any one of claims 1-4, the sampling unit is used to sample the conversion signal and the comparator threshold, the output end of the sampling unit is connected to the input end of the differential amplifier, the differential amplifier input ends of two adjacent stage circuit unit modules are connected through an inter-stage switch, and the inter-stage switch is closed when the stage circuit unit module is in the amplification phase.

6. The pipeline analog-to-digital converter according to claim 5, characterized in that: The operational amplifier signal input circuit and the comparator signal input circuit both include the same capacitive DAC, the output end of the capacitive DAC is connected to the input end of the differential amplifier, and the input end of the capacitive DAC is connected to V that provides the ADC reference common mode voltage. CM pin, forming part of the comparator signal input circuit; the input end of the capacitive DAC is also connected to V which provides the ADC reference voltage RP pin and V RN The sampling unit comprises a parallel-connected signal sampling circuit for a signal to be converted and a comparator threshold sampling circuit, and the signal sampling circuit for a signal to be converted comprises a sampling capacitor C connected between an input signal source and an input terminal of a differential amplifier. S The comparator threshold sampling circuit includes the capacitive DAC and a V connected to its input terminal for providing a comparator threshold voltage. TH Pin.

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